From: Andrew Jones <ajones@ventanamicro.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org, Conor Dooley <conor@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Alexandre Ghiti <alexghiti@rivosinc.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Emil Renner Berthing <kernel@esmil.dk>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>
Subject: Re: [PATCH 08/11] riscv: alternative: Add an ALTERNATIVE_3 macro
Date: Fri, 15 Nov 2024 14:05:32 +0100 [thread overview]
Message-ID: <20241115-1c2467159f117132dc94db26@orel> (raw)
In-Reply-To: <20241102000843.1301099-9-samuel.holland@sifive.com>
On Fri, Nov 01, 2024 at 05:08:02PM -0700, Samuel Holland wrote:
> ALT_FIXUP_PMA() is already using ALTERNATIVE_2(), but needs to be
> extended to handle a fourth case. Add ALTERNATIVE_3(), which extends
> ALTERNATIVE_2() with another block of new content.
>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>
> arch/riscv/include/asm/alternative-macros.h | 45 ++++++++++++++++++---
> 1 file changed, 40 insertions(+), 5 deletions(-)
>
> diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
> index 721ec275ce57..b6027a8b6b50 100644
> --- a/arch/riscv/include/asm/alternative-macros.h
> +++ b/arch/riscv/include/asm/alternative-macros.h
> @@ -50,8 +50,17 @@
> ALT_NEW_CONTENT \vendor_id_2, \patch_id_2, \enable_2, "\new_c_2"
> .endm
>
> +.macro ALTERNATIVE_CFG_3 old_c, new_c_1, vendor_id_1, patch_id_1, enable_1, \
> + new_c_2, vendor_id_2, patch_id_2, enable_2, \
> + new_c_3, vendor_id_3, patch_id_3, enable_3
> + ALTERNATIVE_CFG_2 "\old_c", "\new_c_1", \vendor_id_1, \patch_id_1, \enable_1 \
> + "\new_c_2", \vendor_id_2, \patch_id_2, \enable_2 \
We don't want the '\' on the end of the above line.
> + ALT_NEW_CONTENT \vendor_id_3, \patch_id_3, \enable_3, "\new_c_3"
> +.endm
> +
> #define __ALTERNATIVE_CFG(...) ALTERNATIVE_CFG __VA_ARGS__
> #define __ALTERNATIVE_CFG_2(...) ALTERNATIVE_CFG_2 __VA_ARGS__
> +#define __ALTERNATIVE_CFG_3(...) ALTERNATIVE_CFG_3 __VA_ARGS__
>
> #else /* !__ASSEMBLY__ */
>
> @@ -98,6 +107,13 @@
> __ALTERNATIVE_CFG(old_c, new_c_1, vendor_id_1, patch_id_1, enable_1) \
> ALT_NEW_CONTENT(vendor_id_2, patch_id_2, enable_2, new_c_2)
>
> +#define __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, patch_id_1, enable_1, \
> + new_c_2, vendor_id_2, patch_id_2, enable_2, \
> + new_c_3, vendor_id_3, patch_id_3, enable_3) \
> + __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, patch_id_1, enable_1, \
> + new_c_2, vendor_id_2, patch_id_2, enable_2) \
> + ALT_NEW_CONTENT(vendor_id_3, patch_id_3, enable_3, new_c_3)
> +
> #endif /* __ASSEMBLY__ */
>
> #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, patch_id, CONFIG_k) \
> @@ -108,6 +124,13 @@
> __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, patch_id_1, IS_ENABLED(CONFIG_k_1), \
> new_c_2, vendor_id_2, patch_id_2, IS_ENABLED(CONFIG_k_2))
>
> +#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, patch_id_1, CONFIG_k_1, \
> + new_c_2, vendor_id_2, patch_id_2, CONFIG_k_2, \
> + new_c_3, vendor_id_3, patch_id_3, CONFIG_k_3) \
> + __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, patch_id_1, IS_ENABLED(CONFIG_k_1), \
> + new_c_2, vendor_id_2, patch_id_2, IS_ENABLED(CONFIG_k_2), \
> + new_c_3, vendor_id_3, patch_id_3, IS_ENABLED(CONFIG_k_3))
> +
> #else /* CONFIG_RISCV_ALTERNATIVE */
> #ifdef __ASSEMBLY__
>
> @@ -121,6 +144,9 @@
> #define _ALTERNATIVE_CFG_2(old_c, ...) \
> ALTERNATIVE_CFG old_c
>
> +#define _ALTERNATIVE_CFG_3(old_c, ...) \
> + ALTERNATIVE_CFG old_c
> +
> #else /* !__ASSEMBLY__ */
>
> #define __ALTERNATIVE_CFG(old_c) \
> @@ -132,6 +158,9 @@
> #define _ALTERNATIVE_CFG_2(old_c, ...) \
> __ALTERNATIVE_CFG(old_c)
>
> +#define _ALTERNATIVE_CFG_3(old_c, ...) \
> + __ALTERNATIVE_CFG(old_c)
> +
> #endif /* __ASSEMBLY__ */
> #endif /* CONFIG_RISCV_ALTERNATIVE */
>
> @@ -152,15 +181,21 @@
> _ALTERNATIVE_CFG(old_content, new_content, vendor_id, patch_id, CONFIG_k)
>
> /*
> - * A vendor wants to replace an old_content, but another vendor has used
> - * ALTERNATIVE() to patch its customized content at the same location. In
> - * this case, this vendor can create a new macro ALTERNATIVE_2() based
> - * on the following sample code and then replace ALTERNATIVE() with
> - * ALTERNATIVE_2() to append its customized content.
> + * Variant of ALTERNATIVE() that supports two sets of replacement content.
> */
> #define ALTERNATIVE_2(old_content, new_content_1, vendor_id_1, patch_id_1, CONFIG_k_1, \
> new_content_2, vendor_id_2, patch_id_2, CONFIG_k_2) \
> _ALTERNATIVE_CFG_2(old_content, new_content_1, vendor_id_1, patch_id_1, CONFIG_k_1, \
> new_content_2, vendor_id_2, patch_id_2, CONFIG_k_2)
>
> +/*
> + * Variant of ALTERNATIVE() that supports three sets of replacement content.
> + */
> +#define ALTERNATIVE_3(old_content, new_content_1, vendor_id_1, patch_id_1, CONFIG_k_1, \
> + new_content_2, vendor_id_2, patch_id_2, CONFIG_k_2, \
> + new_content_3, vendor_id_3, patch_id_3, CONFIG_k_3) \
> + _ALTERNATIVE_CFG_3(old_content, new_content_1, vendor_id_1, patch_id_1, CONFIG_k_1, \
> + new_content_2, vendor_id_2, patch_id_2, CONFIG_k_2, \
> + new_content_3, vendor_id_3, patch_id_3, CONFIG_k_3)
> +
> #endif
> --
> 2.45.1
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2024-11-15 13:05 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-02 0:07 [PATCH 00/11] riscv: Memory type control for platforms with physical memory aliases Samuel Holland
2024-11-02 0:07 ` [PATCH 01/11] dt-bindings: riscv: Describe physical memory regions Samuel Holland
2024-11-02 1:31 ` Rob Herring (Arm)
2024-11-02 0:07 ` [PATCH 02/11] riscv: mm: Increment PFN in place when splitting mappings Samuel Holland
2024-11-05 10:25 ` Alexandre Ghiti
2024-11-02 0:07 ` [PATCH 03/11] riscv: mm: Deduplicate pgtable address conversion functions Samuel Holland
2024-11-05 9:58 ` Alexandre Ghiti
2024-11-02 0:07 ` [PATCH 04/11] riscv: mm: Deduplicate _PAGE_CHG_MASK definition Samuel Holland
2024-11-05 10:00 ` Alexandre Ghiti
2024-11-02 0:07 ` [PATCH 05/11] riscv: ptdump: Only show N and MT bits when enabled in the kernel Samuel Holland
2024-11-05 10:06 ` Alexandre Ghiti
2024-11-02 0:08 ` [PATCH 06/11] riscv: mm: Fix up memory types when writing page tables Samuel Holland
2024-11-05 11:03 ` Alexandre Ghiti
2025-10-09 2:12 ` Samuel Holland
2024-11-02 0:08 ` [PATCH 07/11] riscv: mm: Expose all page table bits to assembly code Samuel Holland
2024-11-02 0:08 ` [PATCH 08/11] riscv: alternative: Add an ALTERNATIVE_3 macro Samuel Holland
2024-11-15 13:05 ` Andrew Jones [this message]
2024-11-02 0:08 ` [PATCH 09/11] riscv: alternative: Allow calls with alternate link registers Samuel Holland
2024-11-02 0:08 ` [PATCH 10/11] riscv: mm: Use physical memory aliases to apply PMAs Samuel Holland
2024-11-02 15:28 ` kernel test robot
2024-11-05 13:21 ` Emil Renner Berthing
2024-11-02 0:08 ` [PATCH 11/11] riscv: dts: starfive: jh7100: Use physical memory ranges for DMA Samuel Holland
2024-11-04 15:26 ` Emil Renner Berthing
2025-09-22 23:55 ` [PATCH 00/11] riscv: Memory type control for platforms with physical memory aliases Bo Gan
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