From: Samuel Holland <samuel.holland@sifive.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org, Conor Dooley <conor@kernel.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Alexandre Ghiti <alexghiti@rivosinc.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Emil Renner Berthing <kernel@esmil.dk>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Samuel Holland <samuel.holland@sifive.com>
Subject: [PATCH 02/11] riscv: mm: Increment PFN in place when splitting mappings
Date: Fri, 1 Nov 2024 17:07:56 -0700 [thread overview]
Message-ID: <20241102000843.1301099-3-samuel.holland@sifive.com> (raw)
In-Reply-To: <20241102000843.1301099-1-samuel.holland@sifive.com>
The current code separates page table entry values into a PFN and a
pgprot_t before incrementing the PFN and combining the two parts using
pfn_pXX(). On some hardware with custom page table formats or memory
aliases, the pfn_pXX() functions need to transform the PTE value, so
these functions would need to apply the opposite transformation when
breaking apart the PTE value.
However, both transformations can be avoided by incrementing the PFN in
place, as done by pte_advance_pfn() and set_ptes().
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
arch/riscv/mm/pageattr.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/mm/pageattr.c b/arch/riscv/mm/pageattr.c
index 271d01a5ba4d..335060adc1a6 100644
--- a/arch/riscv/mm/pageattr.c
+++ b/arch/riscv/mm/pageattr.c
@@ -109,9 +109,8 @@ static int __split_linear_mapping_pmd(pud_t *pudp,
continue;
if (pmd_leaf(pmdp_get(pmdp))) {
+ pte_t pte = pmd_pte(pmdp_get(pmdp));
struct page *pte_page;
- unsigned long pfn = _pmd_pfn(pmdp_get(pmdp));
- pgprot_t prot = __pgprot(pmd_val(pmdp_get(pmdp)) & ~_PAGE_PFN_MASK);
pte_t *ptep_new;
int i;
@@ -121,7 +120,7 @@ static int __split_linear_mapping_pmd(pud_t *pudp,
ptep_new = (pte_t *)page_address(pte_page);
for (i = 0; i < PTRS_PER_PTE; ++i, ++ptep_new)
- set_pte(ptep_new, pfn_pte(pfn + i, prot));
+ set_pte(ptep_new, pte_advance_pfn(pte, i));
smp_wmb();
@@ -149,9 +148,8 @@ static int __split_linear_mapping_pud(p4d_t *p4dp,
continue;
if (pud_leaf(pudp_get(pudp))) {
+ pmd_t pmd = __pmd(pud_val(pudp_get(pudp)));
struct page *pmd_page;
- unsigned long pfn = _pud_pfn(pudp_get(pudp));
- pgprot_t prot = __pgprot(pud_val(pudp_get(pudp)) & ~_PAGE_PFN_MASK);
pmd_t *pmdp_new;
int i;
@@ -162,7 +160,8 @@ static int __split_linear_mapping_pud(p4d_t *p4dp,
pmdp_new = (pmd_t *)page_address(pmd_page);
for (i = 0; i < PTRS_PER_PMD; ++i, ++pmdp_new)
set_pmd(pmdp_new,
- pfn_pmd(pfn + ((i * PMD_SIZE) >> PAGE_SHIFT), prot));
+ __pmd(pmd_val(pmd) +
+ (i << (PMD_SHIFT - PAGE_SHIFT + PFN_PTE_SHIFT))));
smp_wmb();
@@ -198,9 +197,8 @@ static int __split_linear_mapping_p4d(pgd_t *pgdp,
continue;
if (p4d_leaf(p4dp_get(p4dp))) {
+ pud_t pud = __pud(p4d_val(p4dp_get(p4dp)));
struct page *pud_page;
- unsigned long pfn = _p4d_pfn(p4dp_get(p4dp));
- pgprot_t prot = __pgprot(p4d_val(p4dp_get(p4dp)) & ~_PAGE_PFN_MASK);
pud_t *pudp_new;
int i;
@@ -215,7 +213,8 @@ static int __split_linear_mapping_p4d(pgd_t *pgdp,
pudp_new = (pud_t *)page_address(pud_page);
for (i = 0; i < PTRS_PER_PUD; ++i, ++pudp_new)
set_pud(pudp_new,
- pfn_pud(pfn + ((i * PUD_SIZE) >> PAGE_SHIFT), prot));
+ __pud(pud_val(pud) +
+ (i << (PUD_SHIFT - PAGE_SHIFT + PFN_PTE_SHIFT))));
/*
* Make sure the pud filling is not reordered with the
--
2.45.1
next prev parent reply other threads:[~2024-11-02 0:08 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-02 0:07 [PATCH 00/11] riscv: Memory type control for platforms with physical memory aliases Samuel Holland
2024-11-02 0:07 ` [PATCH 01/11] dt-bindings: riscv: Describe physical memory regions Samuel Holland
2024-11-02 1:31 ` Rob Herring (Arm)
2024-11-02 0:07 ` Samuel Holland [this message]
2024-11-05 10:25 ` [PATCH 02/11] riscv: mm: Increment PFN in place when splitting mappings Alexandre Ghiti
2024-11-02 0:07 ` [PATCH 03/11] riscv: mm: Deduplicate pgtable address conversion functions Samuel Holland
2024-11-05 9:58 ` Alexandre Ghiti
2024-11-02 0:07 ` [PATCH 04/11] riscv: mm: Deduplicate _PAGE_CHG_MASK definition Samuel Holland
2024-11-05 10:00 ` Alexandre Ghiti
2024-11-02 0:07 ` [PATCH 05/11] riscv: ptdump: Only show N and MT bits when enabled in the kernel Samuel Holland
2024-11-05 10:06 ` Alexandre Ghiti
2024-11-02 0:08 ` [PATCH 06/11] riscv: mm: Fix up memory types when writing page tables Samuel Holland
2024-11-05 11:03 ` Alexandre Ghiti
2025-10-09 2:12 ` Samuel Holland
2024-11-02 0:08 ` [PATCH 07/11] riscv: mm: Expose all page table bits to assembly code Samuel Holland
2024-11-02 0:08 ` [PATCH 08/11] riscv: alternative: Add an ALTERNATIVE_3 macro Samuel Holland
2024-11-15 13:05 ` Andrew Jones
2024-11-02 0:08 ` [PATCH 09/11] riscv: alternative: Allow calls with alternate link registers Samuel Holland
2024-11-02 0:08 ` [PATCH 10/11] riscv: mm: Use physical memory aliases to apply PMAs Samuel Holland
2024-11-02 15:28 ` kernel test robot
2024-11-05 13:21 ` Emil Renner Berthing
2024-11-02 0:08 ` [PATCH 11/11] riscv: dts: starfive: jh7100: Use physical memory ranges for DMA Samuel Holland
2024-11-04 15:26 ` Emil Renner Berthing
2025-09-22 23:55 ` [PATCH 00/11] riscv: Memory type control for platforms with physical memory aliases Bo Gan
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