[PATCH v4 0/5] Fix sd card support for RK3576 platform

[PATCH v4 0/5] Fix sd card support for RK3576 platform

[Shawn Lin]

Marco reported a problem[1] for his FriendlyElec NanoPi R76S board. The problem
is becuase after runtime suspend, the associated power domain is powered off, which
resets the registers including power control bit, card detection logic and internal
phase registers. This leads to three problems need to be solved.

1. hot-plug broken:

SD card hot-plug support for RK3576 boards is broken, because sd slot should try to
use slot-gpio(cd-gpios) instead of function IO for supporting runtime PM. In order
to support slot-gpio detection method, we should disable jtag switching for RK3576.

But the rockchip_grf_init fails to handle this because it couldn't handle
multiple grf nodes. In this case, iocgrf is in behind of sysgrf, so only
sysgrf is handled. We should scan all possible nodes.

Moreover, the offset is wrong as well. Per the TRM, the address of
TOP_IOC_IOC_MISC_CON is 0x260440F0, which means the offset if 0x40F0
instead of 0x040F.

2. cards lost power:

When powering off the power domain during runtime suspend, the controller fails to
maintain the power control status as all the registers is cleared. This results in
power lost for cards during runtime suspend and have to reset the card each time
exiting from runtime supended state. Should use gpio-based regulator for vmmc-suppy
for the boards.

3. controller lost internal phases/mem-clock settings

As the same reason mentioned above, should invent rockchip specific runtime PM
callbacks to save and restore internal phase related settings.

Note: An examination of the RK3576 related dts files suggests that several other boards
may also not function correctly, because I noticed signs of copy-pasting, but I don't have
the schematics to confirm it, I've cc'ed the users of these boards. I hope they can verify
their own boards and submit separate patches if fixes are needed.

Please help review and test.

[1] https://lore.kernel.org/all/20260110010715.1610159-1-mschirrmeister@gmail.com/T/#t


Changes in v4
- add fix patches for RK3576 EVB1 and NanoPi R76S

Changes in v3:
- remove of_node_put() (Heiko)

Changes in v2:
- use for_each_matching_node_and_match(Heiko)

Shawn Lin (5):
  soc: rockchip: grf: Fix wrong RK3576_IOCGRF_MISC_CON definition
  soc: rockchip: grf: Support multiple grf to be handled
  mmc: dw_mmc-rockchip: Fix runtime PM support for internal phase
    support
  arm64: dts: rockchip: Fix SD card support for RK3576 EVB1
  arm64: dts: rockchip: Fix SD card support for RK3576 Nanopi R76s

 arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts   | 22 +++++++++
 .../arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts | 23 ++++++++-
 drivers/mmc/host/dw_mmc-rockchip.c                 | 38 ++++++++++++++-
 drivers/soc/rockchip/grf.c                         | 57 +++++++++++-----------
 4 files changed, 109 insertions(+), 31 deletions(-)

-- 
2.7.4

[PATCH v4 1/5] soc: rockchip: grf: Fix wrong RK3576_IOCGRF_MISC_CON definition

[Shawn Lin]

RK3576_IOCGRF_MISC_CON is IOC_GRF + 0x40F0, fix it.

Fixes: e1aaecacfa13 ("soc: rockchip: grf: Add rk3576 default GRF values")
Cc: Detlev Casanova <detlev.casanova@collabora.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Tested-by: Marco Schirrmeister <mschirrmeister@gmail.com>
---

Changes in v3: None
Changes in v2: None

 drivers/soc/rockchip/grf.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c
index 27bfa09..8974d1c 100644
--- a/drivers/soc/rockchip/grf.c
+++ b/drivers/soc/rockchip/grf.c
@@ -146,7 +146,7 @@ static const struct rockchip_grf_info rk3576_sysgrf __initconst = {
 	.num_values = ARRAY_SIZE(rk3576_defaults_sys_grf),
 };
 
-#define RK3576_IOCGRF_MISC_CON		0x04F0
+#define RK3576_IOCGRF_MISC_CON		0x40F0
 
 static const struct rockchip_grf_value rk3576_defaults_ioc_grf[] __initconst = {
 	{ "jtag switching", RK3576_IOCGRF_MISC_CON, FIELD_PREP_WM16_CONST(BIT(1), 0) },
-- 
2.7.4

[PATCH v4 2/5] soc: rockchip: grf: Support multiple grf to be handled

[Shawn Lin]

Currently, only the first matched node will be handled. This leads
to jtag switching broken for RK3576, as rk3576-sys-grf is found before
rk3576-ioc-grf. Change the code to scan all the possible node to fix
the problem.

Fixes: e1aaecacfa13 ("soc: rockchip: grf: Add rk3576 default GRF values")
Cc: Detlev Casanova <detlev.casanova@collabora.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Tested-by: Marco Schirrmeister <mschirrmeister@gmail.com>
---

Changes in v4:
- none

Changes in v3:
- remove of_node_put() (Heiko)

Changes in v2:
- use for_each_matching_node_and_match(Heiko)

 drivers/soc/rockchip/grf.c | 55 +++++++++++++++++++++++-----------------------
 1 file changed, 27 insertions(+), 28 deletions(-)

diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c
index 8974d1c..04937c4 100644
--- a/drivers/soc/rockchip/grf.c
+++ b/drivers/soc/rockchip/grf.c
@@ -217,34 +217,33 @@ static int __init rockchip_grf_init(void)
 	struct regmap *grf;
 	int ret, i;
 
-	np = of_find_matching_node_and_match(NULL, rockchip_grf_dt_match,
-					     &match);
-	if (!np)
-		return -ENODEV;
-	if (!match || !match->data) {
-		pr_err("%s: missing grf data\n", __func__);
-		of_node_put(np);
-		return -EINVAL;
-	}
-
-	grf_info = match->data;
-
-	grf = syscon_node_to_regmap(np);
-	of_node_put(np);
-	if (IS_ERR(grf)) {
-		pr_err("%s: could not get grf syscon\n", __func__);
-		return PTR_ERR(grf);
-	}
-
-	for (i = 0; i < grf_info->num_values; i++) {
-		const struct rockchip_grf_value *val = &grf_info->values[i];
-
-		pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__,
-			val->desc, val->reg, val->val);
-		ret = regmap_write(grf, val->reg, val->val);
-		if (ret < 0)
-			pr_err("%s: write to %#6x failed with %d\n",
-			       __func__, val->reg, ret);
+	for_each_matching_node_and_match(np, rockchip_grf_dt_match, &match) {
+		if (!of_device_is_available(np))
+			continue;
+		if (!match || !match->data) {
+			pr_err("%s: missing grf data\n", __func__);
+			of_node_put(np);
+			return -EINVAL;
+		}
+
+		grf_info = match->data;
+
+		grf = syscon_node_to_regmap(np);
+		if (IS_ERR(grf)) {
+			pr_err("%s: could not get grf syscon\n", __func__);
+			return PTR_ERR(grf);
+		}
+
+		for (i = 0; i < grf_info->num_values; i++) {
+			const struct rockchip_grf_value *val = &grf_info->values[i];
+
+			pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__,
+				val->desc, val->reg, val->val);
+			ret = regmap_write(grf, val->reg, val->val);
+			if (ret < 0)
+				pr_err("%s: write to %#6x failed with %d\n",
+					__func__, val->reg, ret);
+		}
 	}
 
 	return 0;
-- 
2.7.4

[PATCH v4 3/5] mmc: dw_mmc-rockchip: Fix runtime PM support for internal phase support

[Shawn Lin]

RK3576 is the first platform to introduce internal phase support, and
subsequent platforms are expected to adopt a similar design. In this
architecture, runtime suspend powers off the attached power domain, which
resets registers, including vendor-specific ones such as SDMMC_TIMING_CON0,
SDMMC_TIMING_CON1, and SDMMC_MISC_CON. These registers must be saved and
restored, a requirement that falls outside the scope of the dw_mmc core.

Fixes: 59903441f5e4 ("mmc: dw_mmc-rockchip: Add internal phase support")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Tested-by: Marco Schirrmeister <mschirrmeister@gmail.com>
---

Changes in v3: None
Changes in v2: None

 drivers/mmc/host/dw_mmc-rockchip.c | 38 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
index 879188f..2fe0896 100644
--- a/drivers/mmc/host/dw_mmc-rockchip.c
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
@@ -36,6 +36,8 @@ struct dw_mci_rockchip_priv_data {
 	int			default_sample_phase;
 	int			num_phases;
 	bool			internal_phase;
+	int                     sample_phase;
+	int                     drv_phase;
 };
 
 /*
@@ -573,9 +575,43 @@ static void dw_mci_rockchip_remove(struct platform_device *pdev)
 	dw_mci_pltfm_remove(pdev);
 }
 
+static int dw_mci_rockchip_runtime_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct dw_mci *host = platform_get_drvdata(pdev);
+	struct dw_mci_rockchip_priv_data *priv = host->priv;
+
+	if (priv->internal_phase) {
+		priv->sample_phase = rockchip_mmc_get_phase(host, true);
+		priv->drv_phase = rockchip_mmc_get_phase(host, false);
+	}
+
+	return dw_mci_runtime_suspend(dev);
+}
+
+static int dw_mci_rockchip_runtime_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct dw_mci *host = platform_get_drvdata(pdev);
+	struct dw_mci_rockchip_priv_data *priv = host->priv;
+	int ret;
+
+	ret = dw_mci_runtime_resume(dev);
+	if (ret)
+		return ret;
+
+	if (priv->internal_phase) {
+		rockchip_mmc_set_phase(host, true, priv->sample_phase);
+		rockchip_mmc_set_phase(host, false, priv->drv_phase);
+		mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE);
+	}
+
+	return ret;
+}
+
 static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
 	SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
-	RUNTIME_PM_OPS(dw_mci_runtime_suspend, dw_mci_runtime_resume, NULL)
+	RUNTIME_PM_OPS(dw_mci_rockchip_runtime_suspend, dw_mci_rockchip_runtime_resume, NULL)
 };
 
 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
-- 
2.7.4

Re: [PATCH v4 3/5] mmc: dw_mmc-rockchip: Fix runtime PM support for internal phase support

[Heiko Stübner]

Am Freitag, 16. Januar 2026, 01:55:30 Mitteleuropäische Normalzeit schrieb Shawn Lin:
> RK3576 is the first platform to introduce internal phase support, and
> subsequent platforms are expected to adopt a similar design. In this
> architecture, runtime suspend powers off the attached power domain, which
> resets registers, including vendor-specific ones such as SDMMC_TIMING_CON0,
> SDMMC_TIMING_CON1, and SDMMC_MISC_CON. These registers must be saved and
> restored, a requirement that falls outside the scope of the dw_mmc core.
> 
> Fixes: 59903441f5e4 ("mmc: dw_mmc-rockchip: Add internal phase support")
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> Tested-by: Marco Schirrmeister <mschirrmeister@gmail.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> ---
> 
> Changes in v3: None
> Changes in v2: None
> 
>  drivers/mmc/host/dw_mmc-rockchip.c | 38 +++++++++++++++++++++++++++++++++++++-
>  1 file changed, 37 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
> index 879188f..2fe0896 100644
> --- a/drivers/mmc/host/dw_mmc-rockchip.c
> +++ b/drivers/mmc/host/dw_mmc-rockchip.c
> @@ -36,6 +36,8 @@ struct dw_mci_rockchip_priv_data {
>  	int			default_sample_phase;
>  	int			num_phases;
>  	bool			internal_phase;
> +	int                     sample_phase;
> +	int                     drv_phase;
>  };
>  
>  /*
> @@ -573,9 +575,43 @@ static void dw_mci_rockchip_remove(struct platform_device *pdev)
>  	dw_mci_pltfm_remove(pdev);
>  }
>  
> +static int dw_mci_rockchip_runtime_suspend(struct device *dev)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct dw_mci *host = platform_get_drvdata(pdev);
> +	struct dw_mci_rockchip_priv_data *priv = host->priv;
> +
> +	if (priv->internal_phase) {
> +		priv->sample_phase = rockchip_mmc_get_phase(host, true);
> +		priv->drv_phase = rockchip_mmc_get_phase(host, false);
> +	}
> +
> +	return dw_mci_runtime_suspend(dev);
> +}
> +
> +static int dw_mci_rockchip_runtime_resume(struct device *dev)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct dw_mci *host = platform_get_drvdata(pdev);
> +	struct dw_mci_rockchip_priv_data *priv = host->priv;
> +	int ret;
> +
> +	ret = dw_mci_runtime_resume(dev);
> +	if (ret)
> +		return ret;
> +
> +	if (priv->internal_phase) {
> +		rockchip_mmc_set_phase(host, true, priv->sample_phase);
> +		rockchip_mmc_set_phase(host, false, priv->drv_phase);
> +		mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE);
> +	}
> +
> +	return ret;
> +}
> +
>  static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
>  	SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
> -	RUNTIME_PM_OPS(dw_mci_runtime_suspend, dw_mci_runtime_resume, NULL)
> +	RUNTIME_PM_OPS(dw_mci_rockchip_runtime_suspend, dw_mci_rockchip_runtime_resume, NULL)
>  };
>  
>  static struct platform_driver dw_mci_rockchip_pltfm_driver = {
> 

Re: [PATCH v4 3/5] mmc: dw_mmc-rockchip: Fix runtime PM support for internal phase support

[Ulf Hansson]

On Fri, 16 Jan 2026 at 01:56, Shawn Lin <shawn.lin@rock-chips.com> wrote:
>
> RK3576 is the first platform to introduce internal phase support, and
> subsequent platforms are expected to adopt a similar design. In this
> architecture, runtime suspend powers off the attached power domain, which
> resets registers, including vendor-specific ones such as SDMMC_TIMING_CON0,
> SDMMC_TIMING_CON1, and SDMMC_MISC_CON. These registers must be saved and
> restored, a requirement that falls outside the scope of the dw_mmc core.
>
> Fixes: 59903441f5e4 ("mmc: dw_mmc-rockchip: Add internal phase support")
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> Tested-by: Marco Schirrmeister <mschirrmeister@gmail.com>

Following Heiko's approach, applied for next and by adding a stable-tag, thanks!

Kind regards
Uffe


> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  drivers/mmc/host/dw_mmc-rockchip.c | 38 +++++++++++++++++++++++++++++++++++++-
>  1 file changed, 37 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
> index 879188f..2fe0896 100644
> --- a/drivers/mmc/host/dw_mmc-rockchip.c
> +++ b/drivers/mmc/host/dw_mmc-rockchip.c
> @@ -36,6 +36,8 @@ struct dw_mci_rockchip_priv_data {
>         int                     default_sample_phase;
>         int                     num_phases;
>         bool                    internal_phase;
> +       int                     sample_phase;
> +       int                     drv_phase;
>  };
>
>  /*
> @@ -573,9 +575,43 @@ static void dw_mci_rockchip_remove(struct platform_device *pdev)
>         dw_mci_pltfm_remove(pdev);
>  }
>
> +static int dw_mci_rockchip_runtime_suspend(struct device *dev)
> +{
> +       struct platform_device *pdev = to_platform_device(dev);
> +       struct dw_mci *host = platform_get_drvdata(pdev);
> +       struct dw_mci_rockchip_priv_data *priv = host->priv;
> +
> +       if (priv->internal_phase) {
> +               priv->sample_phase = rockchip_mmc_get_phase(host, true);
> +               priv->drv_phase = rockchip_mmc_get_phase(host, false);
> +       }
> +
> +       return dw_mci_runtime_suspend(dev);
> +}
> +
> +static int dw_mci_rockchip_runtime_resume(struct device *dev)
> +{
> +       struct platform_device *pdev = to_platform_device(dev);
> +       struct dw_mci *host = platform_get_drvdata(pdev);
> +       struct dw_mci_rockchip_priv_data *priv = host->priv;
> +       int ret;
> +
> +       ret = dw_mci_runtime_resume(dev);
> +       if (ret)
> +               return ret;
> +
> +       if (priv->internal_phase) {
> +               rockchip_mmc_set_phase(host, true, priv->sample_phase);
> +               rockchip_mmc_set_phase(host, false, priv->drv_phase);
> +               mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE);
> +       }
> +
> +       return ret;
> +}
> +
>  static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
>         SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
> -       RUNTIME_PM_OPS(dw_mci_runtime_suspend, dw_mci_runtime_resume, NULL)
> +       RUNTIME_PM_OPS(dw_mci_rockchip_runtime_suspend, dw_mci_rockchip_runtime_resume, NULL)
>  };
>
>  static struct platform_driver dw_mci_rockchip_pltfm_driver = {
> --
> 2.7.4
>

[PATCH v4 4/5] arm64: dts: rockchip: Fix SD card support for RK3576 EVB1

[Shawn Lin]

When runtime suspend is enabled, the associated power domain is powered
off, which resets the registers, including the power control bit. As a result,
the card loses power during runtime suspend. The card should still be able
to process I/O with the help of mmc_blk_mq_rw_recovery(), which is suboptimal.
To address this issue, we must use vmmc-supply with a GPIO based method to
maintain power to the card. Also, add cd-gpios method to make hot-plug work
correctly during idle periods.

Fixes: f135a1a07352 ("arm64: dts: rockchip: Add rk3576 evb1 board")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

Changes in v3: None
Changes in v2: None

 arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts
index 0789733..f5746bc 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts
@@ -223,6 +223,18 @@
 		vin-supply = <&vcc_3v3_s3>;
 	};
 
+	vcc3v3_sd: regulator-vcc-3v3-sd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwren>;
+		regulator-name = "vcc3v3_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s0>;
+	};
+
 	vcc_ufs_s0: regulator-vcc-ufs-s0 {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc_ufs_s0";
@@ -904,6 +916,12 @@
 		};
 	};
 
+	sdmmc {
+		sdmmc_pwren: sdmmc-pwren {
+			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	usb {
 		usb_host_pwren: usb-host-pwren {
 			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -958,11 +976,15 @@
 	bus-width = <4>;
 	cap-mmc-highspeed;
 	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
 	disable-wp;
 	max-frequency = <200000000>;
 	no-sdio;
 	no-mmc;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
 	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
 	vqmmc-supply = <&vccio_sd_s0>;
 	status = "okay";
 };
-- 
2.7.4

[PATCH v4 5/5] arm64: dts: rockchip: Fix SD card support for RK3576 Nanopi R76s

[Shawn Lin]

When runtime suspend is enabled, the associated power domain is powered
off, which resets the registers, including the power control bit. As a result,
the card loses power during runtime suspend. The card should still be able
to process I/O with the help of mmc_blk_mq_rw_recovery(), which is suboptimal.
To address this issue, we must use vmmc-supply with a GPIO based method to
maintain power to the card and store valid tuning phases. Also, add cd-gpios
method to make hot-plug work correctly during idle periods.

Fixes: 7fee88882704 ("arm64: dts: rockchip: Add devicetree for the FriendlyElec NanoPi R76S")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Tested-by: Marco Schirrmeister <mschirrmeister@gmail.com>
---

Changes in v3: None
Changes in v2: None

 .../arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts | 23 +++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
index 31fbefa..7ec27b0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
@@ -192,6 +192,18 @@
 		regulator-name = "vcc_3v3_s0";
 		vin-supply = <&vcc_3v3_s3>;
 	};
+
+	vcc3v3_sd: regulator-vcc-3v3-sd {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwren>;
+		regulator-name = "vcc3v3_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s0>;
+	};
 };
 
 &combphy0_ps {
@@ -726,6 +738,12 @@
 		};
 	};
 
+	sdmmc {
+		sdmmc_pwren: sdmmc-pwren {
+			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	usb {
 		usb_otg0_pwren_h: usb-otg0-pwren-h {
 			rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -751,11 +769,14 @@
 	bus-width = <4>;
 	cap-mmc-highspeed;
 	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
 	disable-wp;
 	no-mmc;
 	no-sdio;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
 	sd-uhs-sdr104;
-	vmmc-supply = <&vcc_3v3_s3>;
+	vmmc-supply = <&vcc3v3_sd>;
 	vqmmc-supply = <&vccio_sd_s0>;
 	status = "okay";
 };
-- 
2.7.4

Re: (subset) [PATCH v4 0/5] Fix sd card support for RK3576 platform

[Heiko Stuebner]

On Fri, 16 Jan 2026 08:55:27 +0800, Shawn Lin wrote:
> Marco reported a problem[1] for his FriendlyElec NanoPi R76S board. The problem
> is becuase after runtime suspend, the associated power domain is powered off, which
> resets the registers including power control bit, card detection logic and internal
> phase registers. This leads to three problems need to be solved.
> 
> 1. hot-plug broken:
> 
> [...]

Applied, thanks!

[1/5] soc: rockchip: grf: Fix wrong RK3576_IOCGRF_MISC_CON definition
      commit: 3cdc30c42d4a87444f6c7afbefd6a9381c4caa27
[2/5] soc: rockchip: grf: Support multiple grf to be handled
      commit: 75fb63ae031211e9264ac888fabc2ca9cd3fcccf
[4/5] arm64: dts: rockchip: Fix SD card support for RK3576 EVB1
      commit: 7226664bf952c4cfddccd74b154a7d994608d153
[5/5] arm64: dts: rockchip: Fix SD card support for RK3576 Nanopi R76s
      commit: a9c1acebfe0484343a443d082e039ca77186ed22

I've queued them for 6.20 because I'd like them to marinate a bit longer
due to the size of the changes, but added Cc-stable tags so that they
then can make their way into stable kernels.

Depending if MMC maintainers see patch3, you might want to resend it
individually at some point.


Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

Re: (subset) [PATCH v4 0/5] Fix sd card support for RK3576 platform

[Shawn Lin]

在 2026/01/16 星期五 22:04, Heiko Stuebner 写道:
> 
> On Fri, 16 Jan 2026 08:55:27 +0800, Shawn Lin wrote:
>> Marco reported a problem[1] for his FriendlyElec NanoPi R76S board. The problem
>> is becuase after runtime suspend, the associated power domain is powered off, which
>> resets the registers including power control bit, card detection logic and internal
>> phase registers. This leads to three problems need to be solved.
>>
>> 1. hot-plug broken:
>>
>> [...]
> 
> Applied, thanks!
> 
> [1/5] soc: rockchip: grf: Fix wrong RK3576_IOCGRF_MISC_CON definition
>        commit: 3cdc30c42d4a87444f6c7afbefd6a9381c4caa27
> [2/5] soc: rockchip: grf: Support multiple grf to be handled
>        commit: 75fb63ae031211e9264ac888fabc2ca9cd3fcccf
> [4/5] arm64: dts: rockchip: Fix SD card support for RK3576 EVB1
>        commit: 7226664bf952c4cfddccd74b154a7d994608d153
> [5/5] arm64: dts: rockchip: Fix SD card support for RK3576 Nanopi R76s
>        commit: a9c1acebfe0484343a443d082e039ca77186ed22
> 
> I've queued them for 6.20 because I'd like them to marinate a bit longer
> due to the size of the changes, but added Cc-stable tags so that they
> then can make their way into stable kernels.
> 

Sure, thanks Heiko.

> Depending if MMC maintainers see patch3, you might want to resend it
> individually at some point.
> 
> 
> Best regards,