[PATCH v2 0/2] PCI: qcom-ep: Add QCS9100 PCIe ep compatible

[PATCH v2 0/2] PCI: qcom-ep: Add QCS9100 PCIe ep compatible

[Tengfei Fan]

Introduce support for the QCS9100 SoC device tree (DTSI) and the
QCS9100 RIDE board DTS. The QCS9100 is a variant of the SA8775p.
While the QCS9100 platform is still in the early design stage, the
QCS9100 RIDE board is identical to the SA8775p RIDE board, except it
mounts the QCS9100 SoC instead of the SA8775p SoC.

The QCS9100 SoC DTSI is directly renamed from the SA8775p SoC DTSI, and
all the compatible strings will be updated from "SA8775p" to "QCS9100".
The QCS9100 device tree patches will be pushed after all the device tree
bindings and device driver patches are reviewed.

The final dtsi will like:
https://lore.kernel.org/linux-arm-msm/20240703025850.2172008-3-quic_tengfan@quicinc.com/

The detailed cover letter reference:
https://lore.kernel.org/linux-arm-msm/20240703025850.2172008-1-quic_tengfan@quicinc.com/

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
Changes in v2:
  - Split huge patch series into different patch series according to
    subsytems
  - Update patch commit message

prevous disscussion here:
[1] v1: https://lore.kernel.org/linux-arm-msm/20240703025850.2172008-1-quic_tengfan@quicinc.com/

---
Tengfei Fan (2):
      dt-bindings: PCI: qcom-ep: Add support for QCS9100 SoC
      PCI: qcom-ep: Add HDMA support for QCS9100 SoC

 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++
 drivers/pci/controller/dwc/pcie-qcom-ep.c               | 1 +
 2 files changed, 3 insertions(+)
---
base-commit: 0b58e108042b0ed28a71cd7edf5175999955b233
change-id: 20240709-add_qcs9100_pcie_ep_compatible-c5a9eb2324ac

Best regards,
-- 
Tengfei Fan <quic_tengfan@quicinc.com>

[PATCH v2 1/2] dt-bindings: PCI: qcom-ep: Add support for QCS9100 SoC

[Tengfei Fan]

Add devicetree bindings support for QCS9100 SoC. It has DMA register
space and dma interrupt to support HDMA.
QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p
platform use non-SCMI resource. In the future, the SA8775p platform will
move to use SCMI resources and it will have new sa8775p-related device
tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to describe non-SCMI
based PCIe.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index 46802f7d9482..8012663e7efc 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -13,6 +13,7 @@ properties:
   compatible:
     oneOf:
       - enum:
+          - qcom,qcs9100-pcie-ep
           - qcom,sa8775p-pcie-ep
           - qcom,sdx55-pcie-ep
           - qcom,sm8450-pcie-ep
@@ -203,6 +204,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,qcs9100-pcie-ep
               - qcom,sa8775p-pcie-ep
     then:
       properties:

-- 
2.25.1

[PATCH v2 2/2] PCI: qcom-ep: Add HDMA support for QCS9100 SoC

[Tengfei Fan]

QCS9100 SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP,
so add support for it by passing the mapping format and the number of
read/write channels count.

The PCIe EP controller used on this SoC is of version 1.34.0, so a separate
config struct is introduced for the sake of enabling HDMA conditionally.

It should be noted that for the eDMA support (predecessor of HDMA), there
are no mapping format and channels count specified. That is because eDMA
supports auto detection of both parameters, whereas HDMA doesn't.

QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p
platform use non-SCMI resource. In the future, the SA8775p platform will
move to use SCMI resources and it will have new sa8775p-related device
tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to the PCIe device
match table.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 236229f66c80..e2775f4ca7ee 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -904,6 +904,7 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = {
 };
 
 static const struct of_device_id qcom_pcie_ep_match[] = {
+	{ .compatible = "qcom,qcs9100-pcie-ep", .data = &cfg_1_34_0},
 	{ .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0},
 	{ .compatible = "qcom,sdx55-pcie-ep", },
 	{ .compatible = "qcom,sm8450-pcie-ep", },

-- 
2.25.1

Re: [PATCH v2 2/2] PCI: qcom-ep: Add HDMA support for QCS9100 SoC

[Bjorn Helgaas]

On Tue, Jul 09, 2024 at 10:53:44PM +0800, Tengfei Fan wrote:
> QCS9100 SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP,
> so add support for it by passing the mapping format and the number of
> read/write channels count.
> 
> The PCIe EP controller used on this SoC is of version 1.34.0, so a separate
> config struct is introduced for the sake of enabling HDMA conditionally.

This patch doesn't add a new config struct.

> It should be noted that for the eDMA support (predecessor of HDMA), there
> are no mapping format and channels count specified. That is because eDMA
> supports auto detection of both parameters, whereas HDMA doesn't.
> 
> QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p
> platform use non-SCMI resource. In the future, the SA8775p platform will
> move to use SCMI resources and it will have new sa8775p-related device
> tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to the PCIe device
> match table.

This series doesn't add the new SCMI stuff you mention.  It sounds
like this should be deferred and added when you actually move to using
SCMI resources.

> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index 236229f66c80..e2775f4ca7ee 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -904,6 +904,7 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = {
>  };
>  
>  static const struct of_device_id qcom_pcie_ep_match[] = {
> +	{ .compatible = "qcom,qcs9100-pcie-ep", .data = &cfg_1_34_0},
>  	{ .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0},
>  	{ .compatible = "qcom,sdx55-pcie-ep", },
>  	{ .compatible = "qcom,sm8450-pcie-ep", },
> 
> -- 
> 2.25.1
> 

Re: [PATCH v2 1/2] dt-bindings: PCI: qcom-ep: Add support for QCS9100 SoC

[Bjorn Helgaas]

On Tue, Jul 09, 2024 at 10:53:43PM +0800, Tengfei Fan wrote:
> Add devicetree bindings support for QCS9100 SoC. It has DMA register
> space and dma interrupt to support HDMA.

s/dma/DMA/ above for consistency.

Add blank line here if this is a paragraph break.

> QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p
> platform use non-SCMI resource. In the future, the SA8775p platform will
> move to use SCMI resources and it will have new sa8775p-related device
> tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to describe non-SCMI
> based PCIe.

s/drived/derived/

This patch doesn't add anything related to SCMI, so this paragraph
seems like a distraction.

The first paragraph seems a bit of a distraction too, since the patch
doesn't say anything about DMA register space or interrupt.

> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>  Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> index 46802f7d9482..8012663e7efc 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> @@ -13,6 +13,7 @@ properties:
>    compatible:
>      oneOf:
>        - enum:
> +          - qcom,qcs9100-pcie-ep
>            - qcom,sa8775p-pcie-ep
>            - qcom,sdx55-pcie-ep
>            - qcom,sm8450-pcie-ep
> @@ -203,6 +204,7 @@ allOf:
>          compatible:
>            contains:
>              enum:
> +              - qcom,qcs9100-pcie-ep
>                - qcom,sa8775p-pcie-ep
>      then:
>        properties:
> 
> -- 
> 2.25.1
> 

Re: [PATCH v2 1/2] dt-bindings: PCI: qcom-ep: Add support for QCS9100 SoC

[Tengfei Fan]

On 7/10/2024 12:28 AM, Bjorn Helgaas wrote:
> On Tue, Jul 09, 2024 at 10:53:43PM +0800, Tengfei Fan wrote:
>> Add devicetree bindings support for QCS9100 SoC. It has DMA register
>> space and dma interrupt to support HDMA.
> 
> s/dma/DMA/ above for consistency.
This update will be included in the next verion of the patch series.

> 
> Add blank line here if this is a paragraph break.

A blank line will be added in the next verion of the patch series.

> 
>> QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p
>> platform use non-SCMI resource. In the future, the SA8775p platform will
>> move to use SCMI resources and it will have new sa8775p-related device
>> tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to describe non-SCMI
>> based PCIe.
> 
> s/drived/derived/

This update will be included in the next verion of the patch series

> 
> This patch doesn't add anything related to SCMI, so this paragraph
> seems like a distraction.

This patch is used to support QSC9100. QCS9100 uses non-SCMI resources, 
so there is nothing related to SCMI in this patch.

Only SA8775p will move to use SCMI resources in the future.

> 
> The first paragraph seems a bit of a distraction too, since the patch
> doesn't say anything about DMA register space or interrupt.
I will update this commit message as follows in the next version of the 
patch series.

"Add devicetree bindings support for QCS9100 PCIe EP compatible."


> 
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
>> index 46802f7d9482..8012663e7efc 100644
>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
>> @@ -13,6 +13,7 @@ properties:
>>     compatible:
>>       oneOf:
>>         - enum:
>> +          - qcom,qcs9100-pcie-ep
>>             - qcom,sa8775p-pcie-ep
>>             - qcom,sdx55-pcie-ep
>>             - qcom,sm8450-pcie-ep
>> @@ -203,6 +204,7 @@ allOf:
>>           compatible:
>>             contains:
>>               enum:
>> +              - qcom,qcs9100-pcie-ep
>>                 - qcom,sa8775p-pcie-ep
>>       then:
>>         properties:
>>
>> -- 
>> 2.25.1
>>

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH v2 2/2] PCI: qcom-ep: Add HDMA support for QCS9100 SoC

[Tengfei Fan]

On 7/10/2024 12:26 AM, Bjorn Helgaas wrote:
> On Tue, Jul 09, 2024 at 10:53:44PM +0800, Tengfei Fan wrote:
>> QCS9100 SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP,
>> so add support for it by passing the mapping format and the number of
>> read/write channels count.
>>
>> The PCIe EP controller used on this SoC is of version 1.34.0, so a separate
>> config struct is introduced for the sake of enabling HDMA conditionally.
> 
> This patch doesn't add a new config struct.

Thank you for pointing out this. I will remove this commit message in 
the next version patch series.

> 
>> It should be noted that for the eDMA support (predecessor of HDMA), there
>> are no mapping format and channels count specified. That is because eDMA
>> supports auto detection of both parameters, whereas HDMA doesn't.
>>
>> QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p
>> platform use non-SCMI resource. In the future, the SA8775p platform will
>> move to use SCMI resources and it will have new sa8775p-related device
>> tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to the PCIe device
>> match table.
> 
> This series doesn't add the new SCMI stuff you mention.  It sounds
> like this should be deferred and added when you actually move to using
> SCMI resources.

This patch shouldn't be deferred.

This patch is used to support QSC9100. QCS9100 uses non-SCMI resources, 
so there is nothing related to SCMI in this patch.

Only SA8775p will move to use SCMI resources in the future.


> 
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
>> index 236229f66c80..e2775f4ca7ee 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
>> @@ -904,6 +904,7 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = {
>>   };
>>   
>>   static const struct of_device_id qcom_pcie_ep_match[] = {
>> +	{ .compatible = "qcom,qcs9100-pcie-ep", .data = &cfg_1_34_0},
>>   	{ .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0},
>>   	{ .compatible = "qcom,sdx55-pcie-ep", },
>>   	{ .compatible = "qcom,sm8450-pcie-ep", },
>>
>> -- 
>> 2.25.1
>>

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH v2 1/2] dt-bindings: PCI: qcom-ep: Add support for QCS9100 SoC

[Aiqun Yu (Maria)]

On 7/10/2024 12:28 AM, Bjorn Helgaas wrote:
> On Tue, Jul 09, 2024 at 10:53:43PM +0800, Tengfei Fan wrote:
>> Add devicetree bindings support for QCS9100 SoC. It has DMA register
>> space and dma interrupt to support HDMA.
> 
> s/dma/DMA/ above for consistency.
> 
> Add blank line here if this is a paragraph break.
> 
>> QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p
>> platform use non-SCMI resource. In the future, the SA8775p platform will
>> move to use SCMI resources and it will have new sa8775p-related device
>> tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to describe non-SCMI
>> based PCIe.
> 
> s/drived/derived/
> 
> This patch doesn't add anything related to SCMI, so this paragraph
> seems like a distraction.

The paragraph can be removed from the commit message in next patchsets.
Let me know if others looks good to you or not.
> 
> The first paragraph seems a bit of a distraction too, since the patch
> doesn't say anything about DMA register space or interrupt.

agree. Suggest to remove the first paragraph as well.
> 
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>  Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
>> index 46802f7d9482..8012663e7efc 100644
>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
>> @@ -13,6 +13,7 @@ properties:
>>    compatible:
>>      oneOf:
>>        - enum:
>> +          - qcom,qcs9100-pcie-ep
>>            - qcom,sa8775p-pcie-ep
>>            - qcom,sdx55-pcie-ep
>>            - qcom,sm8450-pcie-ep
>> @@ -203,6 +204,7 @@ allOf:
>>          compatible:
>>            contains:
>>              enum:
>> +              - qcom,qcs9100-pcie-ep
>>                - qcom,sa8775p-pcie-ep
>>      then:
>>        properties:
>>
>> -- 
>> 2.25.1
>>

-- 
Thx and BRs,
Aiqun(Maria) Yu

Re: [PATCH v2 2/2] PCI: qcom-ep: Add HDMA support for QCS9100 SoC

[Aiqun Yu (Maria)]

On 7/10/2024 12:26 AM, Bjorn Helgaas wrote:
> On Tue, Jul 09, 2024 at 10:53:44PM +0800, Tengfei Fan wrote:
>> QCS9100 SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP,
>> so add support for it by passing the mapping format and the number of
>> read/write channels count.
>>
>> The PCIe EP controller used on this SoC is of version 1.34.0, so a separate
>> config struct is introduced for the sake of enabling HDMA conditionally.
> 
> This patch doesn't add a new config struct.
> 
>> It should be noted that for the eDMA support (predecessor of HDMA), there
>> are no mapping format and channels count specified. That is because eDMA
>> supports auto detection of both parameters, whereas HDMA doesn't.
>>
>> QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p
>> platform use non-SCMI resource. In the future, the SA8775p platform will
>> move to use SCMI resources and it will have new sa8775p-related device
>> tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to the PCIe device
>> match table.
> 
> This series doesn't add the new SCMI stuff you mention.  It sounds
> like this should be deferred and added when you actually move to using
> SCMI resources.

We can rename "sa8775p" to "qcs9100" compatible name in next patchset
for this driver. Let's know if this is reasonable from your point of view?

SCMI resource solution will come in a later point, and at that time it
can have scmi related resource operations in this driver and add
"sa8775p" compatible with correct resources ops at that time.

More background:
We want to make QCS9100 non-SCMI resources not blocking by current SCMI
resources changes, since SCMI changes are also pending to merge in order
to not blocking non-scmi resource platforms like current QCS9100
project. So the splitting base device trees are pending here. Don't want
to have a circular dependency loop. :)
> 
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>  drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
>> index 236229f66c80..e2775f4ca7ee 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
>> @@ -904,6 +904,7 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = {
>>  };
>>  
>>  static const struct of_device_id qcom_pcie_ep_match[] = {
>> +	{ .compatible = "qcom,qcs9100-pcie-ep", .data = &cfg_1_34_0},
>>  	{ .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0},
>>  	{ .compatible = "qcom,sdx55-pcie-ep", },
>>  	{ .compatible = "qcom,sm8450-pcie-ep", },
>>
>> -- 
>> 2.25.1
>>

-- 
Thx and BRs,
Aiqun(Maria) Yu

Re: [PATCH v2 2/2] PCI: qcom-ep: Add HDMA support for QCS9100 SoC

[Tengfei Fan]

On 7/10/2024 6:40 PM, Aiqun Yu (Maria) wrote:
> 
> 
> On 7/10/2024 12:26 AM, Bjorn Helgaas wrote:
>> On Tue, Jul 09, 2024 at 10:53:44PM +0800, Tengfei Fan wrote:
>>> QCS9100 SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP,
>>> so add support for it by passing the mapping format and the number of
>>> read/write channels count.
>>>
>>> The PCIe EP controller used on this SoC is of version 1.34.0, so a separate
>>> config struct is introduced for the sake of enabling HDMA conditionally.
>>
>> This patch doesn't add a new config struct.
>>
>>> It should be noted that for the eDMA support (predecessor of HDMA), there
>>> are no mapping format and channels count specified. That is because eDMA
>>> supports auto detection of both parameters, whereas HDMA doesn't.
>>>
>>> QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p
>>> platform use non-SCMI resource. In the future, the SA8775p platform will
>>> move to use SCMI resources and it will have new sa8775p-related device
>>> tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to the PCIe device
>>> match table.
>>
>> This series doesn't add the new SCMI stuff you mention.  It sounds
>> like this should be deferred and added when you actually move to using
>> SCMI resources.
> 
> We can rename "sa8775p" to "qcs9100" compatible name in next patchset
> for this driver. Let's know if this is reasonable from your point of view?
> 
> SCMI resource solution will come in a later point, and at that time it
> can have scmi related resource operations in this driver and add
> "sa8775p" compatible with correct resources ops at that time.
> 
> More background:
> We want to make QCS9100 non-SCMI resources not blocking by current SCMI
> resources changes, since SCMI changes are also pending to merge in order
> to not blocking non-scmi resource platforms like current QCS9100
> project. So the splitting base device trees are pending here. Don't want
> to have a circular dependency loop. :)

After considering the feedback provided on the subject, We have decided
to keep current SA8775p compatible and ABI compatibility in drivers.
Let's close this session and ignore all the current patches here.
Thank you for your input.

>>
>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>> ---
>>>   drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
>>> index 236229f66c80..e2775f4ca7ee 100644
>>> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
>>> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
>>> @@ -904,6 +904,7 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = {
>>>   };
>>>   
>>>   static const struct of_device_id qcom_pcie_ep_match[] = {
>>> +	{ .compatible = "qcom,qcs9100-pcie-ep", .data = &cfg_1_34_0},
>>>   	{ .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0},
>>>   	{ .compatible = "qcom,sdx55-pcie-ep", },
>>>   	{ .compatible = "qcom,sm8450-pcie-ep", },
>>>
>>> -- 
>>> 2.25.1
>>>
> 

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH v2 1/2] dt-bindings: PCI: qcom-ep: Add support for QCS9100 SoC

[Tengfei Fan]

On 7/10/2024 6:31 PM, Aiqun Yu (Maria) wrote:
> 
> 
> On 7/10/2024 12:28 AM, Bjorn Helgaas wrote:
>> On Tue, Jul 09, 2024 at 10:53:43PM +0800, Tengfei Fan wrote:
>>> Add devicetree bindings support for QCS9100 SoC. It has DMA register
>>> space and dma interrupt to support HDMA.
>>
>> s/dma/DMA/ above for consistency.
>>
>> Add blank line here if this is a paragraph break.
>>
>>> QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p
>>> platform use non-SCMI resource. In the future, the SA8775p platform will
>>> move to use SCMI resources and it will have new sa8775p-related device
>>> tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to describe non-SCMI
>>> based PCIe.
>>
>> s/drived/derived/
>>
>> This patch doesn't add anything related to SCMI, so this paragraph
>> seems like a distraction.
> 
> The paragraph can be removed from the commit message in next patchsets.
> Let me know if others looks good to you or not.
>>
>> The first paragraph seems a bit of a distraction too, since the patch
>> doesn't say anything about DMA register space or interrupt.
> 
> agree. Suggest to remove the first paragraph as well.

After considering the feedback provided on the subject, We have decided
to keep current SA8775p compatible and ABI compatibility in drivers.
Let's close this session and ignore all the current patches here.
Thank you for your input.

>>
>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>> ---
>>>   Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++
>>>   1 file changed, 2 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
>>> index 46802f7d9482..8012663e7efc 100644
>>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
>>> @@ -13,6 +13,7 @@ properties:
>>>     compatible:
>>>       oneOf:
>>>         - enum:
>>> +          - qcom,qcs9100-pcie-ep
>>>             - qcom,sa8775p-pcie-ep
>>>             - qcom,sdx55-pcie-ep
>>>             - qcom,sm8450-pcie-ep
>>> @@ -203,6 +204,7 @@ allOf:
>>>           compatible:
>>>             contains:
>>>               enum:
>>> +              - qcom,qcs9100-pcie-ep
>>>                 - qcom,sa8775p-pcie-ep
>>>       then:
>>>         properties:
>>>
>>> -- 
>>> 2.25.1
>>>
> 

-- 
Thx and BRs,
Tengfei Fan