[PATCH v2 0/6] Add and fix ESM nodes

[PATCH v2 0/6] Add and fix ESM nodes

[Judith Mendez]

The following patch adds ESM nodes and fixes ESM source
interrupts for Sitara K3 platforms. Currently watchdog cannot
reset the CPU because of misconfiguration or missing ESM node
in DT.

ESM node was added for am62ax and am65x. For am62px ESM source
interrupts are fixed. Comments were also added for clarity on what
source interrupts are routed to ESM based on device TRM.

ESM nodes like MCU ESM for am65x are added for device completion,
currently, some ESM0 events are not routed to MCU ESM, so watchdog
cannot reset the CPU using the current implementation.

Changes since v1:
- Remove watchdog patch
- Add am64x patch 5/6
- Add am65x patch 6/6
- Add missing bootph flag

Judith Mendez (5):
  arm64: dts: ti: k3-am62a: Add ESM nodes
  arm64: dts: ti: k3-am62p: Fix ESM interrupt sources
  arm64: dts: ti: k3-am62: Add comments to ESM nodes
  arm64: dts: ti: k3-am64: Add more ESM interrupt sources
  arm64: dts: ti: k3-am65: Add ESM nodes

Santhosh Kumar K (1):
  arm64: dts: ti: k3-am62p: Remove 'reserved' status for ESM

 arch/arm64/boot/dts/ti/k3-am62-main.dtsi               | 1 +
 arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi                | 1 +
 arch/arm64/boot/dts/ti/k3-am62a-main.dtsi              | 8 ++++++++
 arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi               | 8 ++++++++
 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 3 ++-
 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi  | 4 ++--
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi               | 3 ++-
 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi                | 3 ++-
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi               | 8 ++++++++
 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi                | 8 ++++++++
 10 files changed, 42 insertions(+), 5 deletions(-)


base-commit: e3cce1229c34b5c28f103361c4d6b3ef17302d5d
-- 
2.46.0

[PATCH v2 1/6] arm64: dts: ti: k3-am62a: Add ESM nodes

[Judith Mendez]

Add Error Signaling Module (ESM) instances in MCU and MAIN
domains, set ESM interrupt sources for rti as per TRM [0] 10.4
Interrupt Sources.

Add comments to describe what interrupt sources are routed to
ESM modules.

[0] https://www.ti.com/lit/ug/spruj16b/spruj16b.pdf

Signed-off-by: Judith Mendez <jm@ti.com>
---
Changes since v1:
- Add bootph flag
- Add comment to ESM nodes
---
 arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 8 ++++++++
 arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi  | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
index 916fcf3cc57d1..8c35293c3d2b0 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
@@ -265,6 +265,14 @@ main_pmx0: pinctrl@f4000 {
 		pinctrl-single,function-mask = <0xffffffff>;
 	};
 
+	main_esm: esm@420000 {
+		compatible = "ti,j721e-esm";
+		reg = <0x0 0x420000 0x0 0x1000>;
+		/* Interrupt sources: rti0, rti1, wrti0, rti4, rti2, rti3 */
+		ti,esm-pins = <192>, <193>, <195>, <204>, <209>, <210>;
+		bootph-pre-ram;
+	};
+
 	main_timer0: timer@2400000 {
 		compatible = "ti,am654-timer";
 		reg = <0x00 0x2400000 0x00 0x400>;
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
index 8c36e56f41388..a5ca4ce523a46 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
@@ -15,6 +15,14 @@ mcu_pmx0: pinctrl@4084000 {
 		status = "disabled";
 	};
 
+	mcu_esm: esm@4100000 {
+		compatible = "ti,j721e-esm";
+		reg = <0x0 0x4100000 0x0 0x1000>;
+		/* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */
+		ti,esm-pins = <0>, <1>, <2>, <85>;
+		bootph-pre-ram;
+	};
+
 	/*
 	 * The MCU domain timer interrupts are routed only to the ESM module,
 	 * and not currently available for Linux. The MCU domain timers are
-- 
2.46.0

[PATCH v2 2/6] arm64: dts: ti: k3-am62p: Fix ESM interrupt sources

[Judith Mendez]

Fix interrupt sources for rti routed to the ESM0 as per [0], in
10.4 Interrupt Sources

Add comments to describe what interrupt sources are routed to
ESM modules.

[0] https://www.ti.com/lit/ug/spruj83/spruj83.pdf

Fixes: b5080c7c1f7e ("arm64: dts: ti: k3-am62p: Add nodes for more IPs")
Signed-off-by: Judith Mendez <jm@ti.com>
---
Changes since v1:
- Add comment to ESM nodes
- Add more interrupt sources to ESM nodes
---
 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 3 ++-
 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi  | 5 +++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
index 9701fc69aed94..7941aab09cf72 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
@@ -260,7 +260,8 @@ main_pmx0: pinctrl@f4000 {
 	main_esm: esm@420000 {
 		compatible = "ti,j721e-esm";
 		reg = <0x00 0x420000 0x00 0x1000>;
-		ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
+		/* Interrupt sources: rti0, rti1, wrti0 rti2, rti3, rti15 */
+		ti,esm-pins = <224>, <225>, <227>, <241>, <242>, <248>;
 		bootph-pre-ram;
 	};
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
index df7945156397b..49dda340752aa 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
@@ -26,9 +26,10 @@ mcu_pmx_range: gpio-range {
 	mcu_esm: esm@4100000 {
 		compatible = "ti,j721e-esm";
 		reg = <0x00 0x4100000 0x00 0x1000>;
-		ti,esm-pins = <0>, <1>, <2>, <85>;
-		status = "reserved";
+		/* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0, wrti0 */
+		ti,esm-pins = <0>, <1>, <2>, <85>, <86>;
 		bootph-pre-ram;
+		status = "reserved";
 	};
 
 	/*
-- 
2.46.0

[PATCH v2 3/6] arm64: dts: ti: k3-am62p: Remove 'reserved' status for ESM

[Judith Mendez]

From: Santhosh Kumar K <s-k6@ti.com>

Remove 'reserved' status for MCU ESM node. Watchdog
reset is propagated through ESM0 to MCU ESM to reset
the CPU, so enable MCU ESM to reset the CPU with
watchdog timeout.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
[Judith: Fix commit message]
Signed-off-by: Judith Mendez <jm@ti.com>
---
Changes since v1:
- Fix commit mesage
---
 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
index 49dda340752aa..625d353b97600 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
@@ -29,7 +29,6 @@ mcu_esm: esm@4100000 {
 		/* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0, wrti0 */
 		ti,esm-pins = <0>, <1>, <2>, <85>, <86>;
 		bootph-pre-ram;
-		status = "reserved";
 	};
 
 	/*
-- 
2.46.0

[PATCH v2 4/6] arm64: dts: ti: k3-am62: Add comments to ESM nodes

[Judith Mendez]

Add comments to describe what interrupt sources are routed to
ESM modules.

There is no functional change.

Signed-off-by: Judith Mendez <jm@ti.com>
---
Changes since v1:
- Add comment to ESM nodes
---
 arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 1 +
 arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index 328929c740dc0..5b92aef5b284b 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -241,6 +241,7 @@ main_esm: esm@420000 {
 		bootph-pre-ram;
 		compatible = "ti,j721e-esm";
 		reg = <0x00 0x420000 0x00 0x1000>;
+		/* Interrupt sources: rti0, rti1, rti15, wrti0, rti2, rti3 */
 		ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
 	};
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
index e66d486ef1f21..bb43a411f59b2 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
@@ -19,6 +19,7 @@ mcu_esm: esm@4100000 {
 		bootph-pre-ram;
 		compatible = "ti,j721e-esm";
 		reg = <0x00 0x4100000 0x00 0x1000>;
+		/* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */
 		ti,esm-pins = <0>, <1>, <2>, <85>;
 	};
 
-- 
2.46.0

[PATCH v2 5/6] arm64: dts: ti: k3-am64: Add more ESM interrupt sources

[Judith Mendez]

Add ESM interrupt sources for rti as per TRM [0] in 9.4
Interrupt Sources.

[0] https://www.ti.com/lit/ug/spruim2h/spruim2h.pdf

Signed-off-by: Judith Mendez <jm@ti.com>
---
Changes since v1:
- Add patch 5/6 for am64x
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 3 ++-
 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi  | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index f8370dd033502..652653bb24f26 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -389,7 +389,8 @@ main_esm: esm@420000 {
 		bootph-pre-ram;
 		compatible = "ti,j721e-esm";
 		reg = <0x00 0x420000 0x00 0x1000>;
-		ti,esm-pins = <160>, <161>;
+		/* Interrupt sources: rti0, rti1, rti8, rti9, rti10, rti11 */
+		ti,esm-pins = <160>, <161>, <162>, <163>, <164>, <165>;
 	};
 
 	main_uart0: serial@2800000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
index ec17285869da6..ad4bed5d3f9eb 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
@@ -158,6 +158,7 @@ mcu_esm: esm@4100000 {
 		bootph-pre-ram;
 		compatible = "ti,j721e-esm";
 		reg = <0x00 0x4100000 0x00 0x1000>;
-		ti,esm-pins = <0>, <1>;
+		/* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */
+		ti,esm-pins = <0>, <1>, <2>, <85>;
 	};
 };
-- 
2.46.0

[PATCH v2 6/6] arm64: dts: ti: k3-am65: Add ESM nodes

[Judith Mendez]

Add Error Signaling Module (ESM) instances in MCU and MAIN
domains, set ESM interrupt sources for rti as per TRM [0] 9.4
Interrupt Sources.

Add comments to describe what interrupt sources are routed to
ESM modules.

[0] https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf

Signed-off-by: Judith Mendez <jm@ti.com>
---
Changes since v1:
- Add patch 6/6 for am65x
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++++++
 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 1af3dedde1f67..07c9f043dac0b 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -54,6 +54,14 @@ gic_its: msi-controller@1820000 {
 		};
 	};
 
+	main_esm: esm@700000 {
+		compatible = "ti,j721e-esm";
+		reg = <0x00 0x700000 0x00 0x1000>;
+		/* Interrupt sources: rti0, rti1, rti2, rti3 */
+		ti,esm-pins = <224>, <225>, <226>, <227>;
+		bootph-pre-ram;
+	};
+
 	serdes0: serdes@900000 {
 		compatible = "ti,phy-am654-serdes";
 		reg = <0x0 0x900000 0x0 0x2000>;
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index 43c6118d2bf0f..e10cb9f483698 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -440,6 +440,14 @@ mcu_r5fss0_core1: r5f@41400000 {
 		};
 	};
 
+	mcu_esm: esm@40800000 {
+		compatible = "ti,j721e-esm";
+		reg = <0x00 0x40800000 0x00 0x1000>;
+		/* Interrupt sources: mrti0, mrti1 */
+		ti,esm-pins = <104>, <105>;
+		bootph-pre-ram;
+	};
+
 	mcu_rti1: watchdog@40610000 {
 		compatible = "ti,j7-rti-wdt";
 		reg = <0x0 0x40610000 0x0 0x100>;
-- 
2.46.0

Re: [PATCH v2 6/6] arm64: dts: ti: k3-am65: Add ESM nodes

[Judith Mendez]

Hi all,

On 8/13/24 6:03 PM, Judith Mendez wrote:
> Add Error Signaling Module (ESM) instances in MCU and MAIN
> domains, set ESM interrupt sources for rti as per TRM [0] 9.4
> Interrupt Sources.
> 
> Add comments to describe what interrupt sources are routed to
> ESM modules.
> 
> [0] https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
> 
> Signed-off-by: Judith Mendez <jm@ti.com>
> ---
> Changes since v1:
> - Add patch 6/6 for am65x
> ---
>   arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++++++
>   arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  | 8 ++++++++
>   2 files changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> index 1af3dedde1f67..07c9f043dac0b 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -54,6 +54,14 @@ gic_its: msi-controller@1820000 {
>   		};
>   	};
>   
> +	main_esm: esm@700000 {
> +		compatible = "ti,j721e-esm";
> +		reg = <0x00 0x700000 0x00 0x1000>;
> +		/* Interrupt sources: rti0, rti1, rti2, rti3 */
> +		ti,esm-pins = <224>, <225>, <226>, <227>;

I am not sure if someone knows the answer to this question, but..

I noticed that for rti, the interrupt source id's are different
for SR1 vs SR2, so which should be used here in k3-am65-main?

Here, I assumed SR2.

~ Judith


> +		bootph-pre-ram;
> +	};
> +
>   	serdes0: serdes@900000 {
>   		compatible = "ti,phy-am654-serdes";
>   		reg = <0x0 0x900000 0x0 0x2000>;
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
> index 43c6118d2bf0f..e10cb9f483698 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
> @@ -440,6 +440,14 @@ mcu_r5fss0_core1: r5f@41400000 {
>   		};
>   	};
>   
> +	mcu_esm: esm@40800000 {
> +		compatible = "ti,j721e-esm";
> +		reg = <0x00 0x40800000 0x00 0x1000>;
> +		/* Interrupt sources: mrti0, mrti1 */
> +		ti,esm-pins = <104>, <105>;
> +		bootph-pre-ram;
> +	};
> +
>   	mcu_rti1: watchdog@40610000 {
>   		compatible = "ti,j7-rti-wdt";
>   		reg = <0x0 0x40610000 0x0 0x100>;

Re: [PATCH v2 6/6] arm64: dts: ti: k3-am65: Add ESM nodes

[Nishanth Menon]

On 09:05-20240814, Judith Mendez wrote:
> Hi all,
> 
> On 8/13/24 6:03 PM, Judith Mendez wrote:
> > Add Error Signaling Module (ESM) instances in MCU and MAIN
> > domains, set ESM interrupt sources for rti as per TRM [0] 9.4
> > Interrupt Sources.
> > 
> > Add comments to describe what interrupt sources are routed to
> > ESM modules.
> > 
> > [0] https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf

As mentioned[1], please update the commit message

> > 
> > Signed-off-by: Judith Mendez <jm@ti.com>
> > ---
> > Changes since v1:
> > - Add patch 6/6 for am65x
> > ---
> >   arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++++++
> >   arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  | 8 ++++++++
> >   2 files changed, 16 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > index 1af3dedde1f67..07c9f043dac0b 100644
> > --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > @@ -54,6 +54,14 @@ gic_its: msi-controller@1820000 {
> >   		};
> >   	};
> > +	main_esm: esm@700000 {
> > +		compatible = "ti,j721e-esm";
> > +		reg = <0x00 0x700000 0x00 0x1000>;
> > +		/* Interrupt sources: rti0, rti1, rti2, rti3 */
> > +		ti,esm-pins = <224>, <225>, <226>, <227>;
> 
> I am not sure if someone knows the answer to this question, but..
> 
> I noticed that for rti, the interrupt source id's are different
> for SR1 vs SR2, so which should be used here in k3-am65-main?
> 
> Here, I assumed SR2.

The only production board with SR1.0 that I am aware of is
arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi I think - Jan can
clarify. The technique used is to do an override in the dtsi if I am not
mistaken.

[1] https://lore.kernel.org/all/20240815122928.4i2yob5aj5ssqhzw@reply/
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v2 6/6] arm64: dts: ti: k3-am65: Add ESM nodes

[Jan Kiszka]

On 15.08.24 14:32, Nishanth Menon wrote:
> On 09:05-20240814, Judith Mendez wrote:
>> Hi all,
>>
>> On 8/13/24 6:03 PM, Judith Mendez wrote:
>>> Add Error Signaling Module (ESM) instances in MCU and MAIN
>>> domains, set ESM interrupt sources for rti as per TRM [0] 9.4
>>> Interrupt Sources.
>>>
>>> Add comments to describe what interrupt sources are routed to
>>> ESM modules.
>>>
>>> [0] https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
> 
> As mentioned[1], please update the commit message
> 
>>>
>>> Signed-off-by: Judith Mendez <jm@ti.com>
>>> ---
>>> Changes since v1:
>>> - Add patch 6/6 for am65x
>>> ---
>>>   arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++++++
>>>   arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  | 8 ++++++++
>>>   2 files changed, 16 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>>> index 1af3dedde1f67..07c9f043dac0b 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>>> @@ -54,6 +54,14 @@ gic_its: msi-controller@1820000 {
>>>   		};
>>>   	};
>>> +	main_esm: esm@700000 {
>>> +		compatible = "ti,j721e-esm";
>>> +		reg = <0x00 0x700000 0x00 0x1000>;
>>> +		/* Interrupt sources: rti0, rti1, rti2, rti3 */
>>> +		ti,esm-pins = <224>, <225>, <226>, <227>;
>>
>> I am not sure if someone knows the answer to this question, but..
>>
>> I noticed that for rti, the interrupt source id's are different
>> for SR1 vs SR2, so which should be used here in k3-am65-main?
>>
>> Here, I assumed SR2.
> 
> The only production board with SR1.0 that I am aware of is
> arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi I think - Jan can
> clarify. The technique used is to do an override in the dtsi if I am not
> mistaken.
> 
> [1] https://lore.kernel.org/all/20240815122928.4i2yob5aj5ssqhzw@reply/

Yes, we have to boards with SR1.0 in field, k3-am6528-iot2050-basic.dts
and k3-am6548-iot2050-advanced.dts (which include the above dtsi).

But given that AM65 is not benefiting from all these changes anyway if I
got the reply correctly, why do we care?

Jan

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Siemens AG, Technology
Linux Expert Center

Re: [PATCH v2 0/6] Add and fix ESM nodes

[Jan Kiszka]

On 14.08.24 01:03, Judith Mendez wrote:
> The following patch adds ESM nodes and fixes ESM source
> interrupts for Sitara K3 platforms. Currently watchdog cannot
> reset the CPU because of misconfiguration or missing ESM node
> in DT.
> 
> ESM node was added for am62ax and am65x. For am62px ESM source
> interrupts are fixed. Comments were also added for clarity on what
> source interrupts are routed to ESM based on device TRM.
> 
> ESM nodes like MCU ESM for am65x are added for device completion,
> currently, some ESM0 events are not routed to MCU ESM, so watchdog
> cannot reset the CPU using the current implementation.

Yes, that's why there is https://github.com/siemens/k3-rti-wdt and
probably similar bits in other R5 firmware. I was always told that is
the only way to reset the /system/ (CPU alone would not help). That
information is still correct?

Jan

> 
> Changes since v1:
> - Remove watchdog patch
> - Add am64x patch 5/6
> - Add am65x patch 6/6
> - Add missing bootph flag
> 
> Judith Mendez (5):
>   arm64: dts: ti: k3-am62a: Add ESM nodes
>   arm64: dts: ti: k3-am62p: Fix ESM interrupt sources
>   arm64: dts: ti: k3-am62: Add comments to ESM nodes
>   arm64: dts: ti: k3-am64: Add more ESM interrupt sources
>   arm64: dts: ti: k3-am65: Add ESM nodes
> 
> Santhosh Kumar K (1):
>   arm64: dts: ti: k3-am62p: Remove 'reserved' status for ESM
> 
>  arch/arm64/boot/dts/ti/k3-am62-main.dtsi               | 1 +
>  arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi                | 1 +
>  arch/arm64/boot/dts/ti/k3-am62a-main.dtsi              | 8 ++++++++
>  arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi               | 8 ++++++++
>  arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 3 ++-
>  arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi  | 4 ++--
>  arch/arm64/boot/dts/ti/k3-am64-main.dtsi               | 3 ++-
>  arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi                | 3 ++-
>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi               | 8 ++++++++
>  arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi                | 8 ++++++++
>  10 files changed, 42 insertions(+), 5 deletions(-)
> 
> 
> base-commit: e3cce1229c34b5c28f103361c4d6b3ef17302d5d

-- 
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Linux Expert Center

Re: [PATCH v2 0/6] Add and fix ESM nodes

[Judith Mendez]

Hi Jan,

On 8/13/24 11:04 PM, Jan Kiszka wrote:
> On 14.08.24 01:03, Judith Mendez wrote:
>> The following patch adds ESM nodes and fixes ESM source
>> interrupts for Sitara K3 platforms. Currently watchdog cannot
>> reset the CPU because of misconfiguration or missing ESM node
>> in DT.
>>
>> ESM node was added for am62ax and am65x. For am62px ESM source
>> interrupts are fixed. Comments were also added for clarity on what
>> source interrupts are routed to ESM based on device TRM.
>>
>> ESM nodes like MCU ESM for am65x are added for device completion,
>> currently, some ESM0 events are not routed to MCU ESM, so watchdog
>> cannot reset the CPU using the current implementation.
> 
> Yes, that's why there is https://github.com/siemens/k3-rti-wdt and
> probably similar bits in other R5 firmware. I was always told that is
> the only way to reset the /system/ (CPU alone would not help). That
> information is still correct?

If you look at 9.4.14 MCU_ESM0 Interrupt Map, ESM0_ESM_INT_CFG_LVL_0,
ESM0_ESM_INT_HI_LVL_0, and ESM0_ESM_INT_LOW_LVL_0 are not routed to
MCU_ESM0. So the current implementation to route events from ESM0 to
MCU_ESM0 to reset the CPU will not work for AM65x, this is the
implementation on other K3 Sitara platforms and how watchdog can reset
the cpu.

I did find MAIN_ESM_ERROR_INT which should be SOC_SAFETY_ERRORn, look
at Figure 12-3690. Perhaps the ESMs could be configured to use
SOC_SAFETY_ERRORn instead, not sure.

The above should apply to both SR1 and SR2 devices according to the TRM.

~ Judith

> 
> Jan
> 
>>
>> Changes since v1:
>> - Remove watchdog patch
>> - Add am64x patch 5/6
>> - Add am65x patch 6/6
>> - Add missing bootph flag
>>
>> Judith Mendez (5):
>>    arm64: dts: ti: k3-am62a: Add ESM nodes
>>    arm64: dts: ti: k3-am62p: Fix ESM interrupt sources
>>    arm64: dts: ti: k3-am62: Add comments to ESM nodes
>>    arm64: dts: ti: k3-am64: Add more ESM interrupt sources
>>    arm64: dts: ti: k3-am65: Add ESM nodes
>>
>> Santhosh Kumar K (1):
>>    arm64: dts: ti: k3-am62p: Remove 'reserved' status for ESM
>>
>>   arch/arm64/boot/dts/ti/k3-am62-main.dtsi               | 1 +
>>   arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi                | 1 +
>>   arch/arm64/boot/dts/ti/k3-am62a-main.dtsi              | 8 ++++++++
>>   arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi               | 8 ++++++++
>>   arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 3 ++-
>>   arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi  | 4 ++--
>>   arch/arm64/boot/dts/ti/k3-am64-main.dtsi               | 3 ++-
>>   arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi                | 3 ++-
>>   arch/arm64/boot/dts/ti/k3-am65-main.dtsi               | 8 ++++++++
>>   arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi                | 8 ++++++++
>>   10 files changed, 42 insertions(+), 5 deletions(-)
>>
>>
>> base-commit: e3cce1229c34b5c28f103361c4d6b3ef17302d5d
> 

Re: [PATCH v2 0/6] Add and fix ESM nodes

[Nishanth Menon]

On 08:59-20240814, Judith Mendez wrote:
> Hi Jan,
> 
> On 8/13/24 11:04 PM, Jan Kiszka wrote:
> > On 14.08.24 01:03, Judith Mendez wrote:
> > > The following patch adds ESM nodes and fixes ESM source
> > > interrupts for Sitara K3 platforms. Currently watchdog cannot
> > > reset the CPU because of misconfiguration or missing ESM node
> > > in DT.
> > > 
> > > ESM node was added for am62ax and am65x. For am62px ESM source
> > > interrupts are fixed. Comments were also added for clarity on what
> > > source interrupts are routed to ESM based on device TRM.
> > > 
> > > ESM nodes like MCU ESM for am65x are added for device completion,
> > > currently, some ESM0 events are not routed to MCU ESM, so watchdog
> > > cannot reset the CPU using the current implementation.
> > 
> > Yes, that's why there is https://github.com/siemens/k3-rti-wdt and
> > probably similar bits in other R5 firmware. I was always told that is
> > the only way to reset the /system/ (CPU alone would not help). That
> > information is still correct?
> 
> If you look at 9.4.14 MCU_ESM0 Interrupt Map, ESM0_ESM_INT_CFG_LVL_0,
> ESM0_ESM_INT_HI_LVL_0, and ESM0_ESM_INT_LOW_LVL_0 are not routed to
> MCU_ESM0. So the current implementation to route events from ESM0 to
> MCU_ESM0 to reset the CPU will not work for AM65x, this is the
> implementation on other K3 Sitara platforms and how watchdog can reset
> the cpu.
> 
> I did find MAIN_ESM_ERROR_INT which should be SOC_SAFETY_ERRORn, look
> at Figure 12-3690. Perhaps the ESMs could be configured to use
> SOC_SAFETY_ERRORn instead, not sure.
> 
> The above should apply to both SR1 and SR2 devices according to the TRM.

Thanks for clarifying - you should add that in the commit message.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v2 0/6] Add and fix ESM nodes

[Jan Kiszka]

On 15.08.24 14:29, Nishanth Menon wrote:
> On 08:59-20240814, Judith Mendez wrote:
>> Hi Jan,
>>
>> On 8/13/24 11:04 PM, Jan Kiszka wrote:
>>> On 14.08.24 01:03, Judith Mendez wrote:
>>>> The following patch adds ESM nodes and fixes ESM source
>>>> interrupts for Sitara K3 platforms. Currently watchdog cannot
>>>> reset the CPU because of misconfiguration or missing ESM node
>>>> in DT.
>>>>
>>>> ESM node was added for am62ax and am65x. For am62px ESM source
>>>> interrupts are fixed. Comments were also added for clarity on what
>>>> source interrupts are routed to ESM based on device TRM.
>>>>
>>>> ESM nodes like MCU ESM for am65x are added for device completion,
>>>> currently, some ESM0 events are not routed to MCU ESM, so watchdog
>>>> cannot reset the CPU using the current implementation.
>>>
>>> Yes, that's why there is https://github.com/siemens/k3-rti-wdt and
>>> probably similar bits in other R5 firmware. I was always told that is
>>> the only way to reset the /system/ (CPU alone would not help). That
>>> information is still correct?
>>
>> If you look at 9.4.14 MCU_ESM0 Interrupt Map, ESM0_ESM_INT_CFG_LVL_0,
>> ESM0_ESM_INT_HI_LVL_0, and ESM0_ESM_INT_LOW_LVL_0 are not routed to
>> MCU_ESM0. So the current implementation to route events from ESM0 to
>> MCU_ESM0 to reset the CPU will not work for AM65x, this is the
>> implementation on other K3 Sitara platforms and how watchdog can reset
>> the cpu.
>>
>> I did find MAIN_ESM_ERROR_INT which should be SOC_SAFETY_ERRORn, look
>> at Figure 12-3690. Perhaps the ESMs could be configured to use
>> SOC_SAFETY_ERRORn instead, not sure.
>>
>> The above should apply to both SR1 and SR2 devices according to the TRM.
> 
> Thanks for clarifying - you should add that in the commit message.
> 

So the short answer to my question is "yes".

Jan

-- 
Siemens AG, Technology
Linux Expert Center

Re: [PATCH v2 0/6] Add and fix ESM nodes

[Judith Mendez]

Hi Nishanth,

On 8/15/24 7:29 AM, Nishanth Menon wrote:
> On 08:59-20240814, Judith Mendez wrote:
>> Hi Jan,
>>
>> On 8/13/24 11:04 PM, Jan Kiszka wrote:
>>> On 14.08.24 01:03, Judith Mendez wrote:
>>>> The following patch adds ESM nodes and fixes ESM source
>>>> interrupts for Sitara K3 platforms. Currently watchdog cannot
>>>> reset the CPU because of misconfiguration or missing ESM node
>>>> in DT.
>>>>
>>>> ESM node was added for am62ax and am65x. For am62px ESM source
>>>> interrupts are fixed. Comments were also added for clarity on what
>>>> source interrupts are routed to ESM based on device TRM.
>>>>
>>>> ESM nodes like MCU ESM for am65x are added for device completion,
>>>> currently, some ESM0 events are not routed to MCU ESM, so watchdog
>>>> cannot reset the CPU using the current implementation.
>>>
>>> Yes, that's why there is https://github.com/siemens/k3-rti-wdt and
>>> probably similar bits in other R5 firmware. I was always told that is
>>> the only way to reset the /system/ (CPU alone would not help). That
>>> information is still correct?
>>
>> If you look at 9.4.14 MCU_ESM0 Interrupt Map, ESM0_ESM_INT_CFG_LVL_0,
>> ESM0_ESM_INT_HI_LVL_0, and ESM0_ESM_INT_LOW_LVL_0 are not routed to
>> MCU_ESM0. So the current implementation to route events from ESM0 to
>> MCU_ESM0 to reset the CPU will not work for AM65x, this is the
>> implementation on other K3 Sitara platforms and how watchdog can reset
>> the cpu.
>>
>> I did find MAIN_ESM_ERROR_INT which should be SOC_SAFETY_ERRORn, look
>> at Figure 12-3690. Perhaps the ESMs could be configured to use
>> SOC_SAFETY_ERRORn instead, not sure.
>>
>> The above should apply to both SR1 and SR2 devices according to the TRM.
> 
> Thanks for clarifying - you should add that in the commit message.
> 

Sure, I can send v3 with another commit message fixup.

~ Judith