[PATCH v5 0/8] add Voyager board support

[PATCH v5 0/8] add Voyager board support

[Ben Zong-You Xie]

The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
including Andes QiLai SoC. This patch series adds minimal device tree
files for the QiLai SoC and the Voyager board [1].

Now only support basic uart drivers to boot up into a basic console. Other
features will be added later.

[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
---
Changelog from v4 to v5:
  - Rebase the series on torvalds/master
  - Clarify the patch dependencies (2 <- 4 <- 5 <- 6) in the patch description

v4: https://lore.kernel.org/all/20250514095350.3765716-1-ben717@andestech.com/

Changelog from v3 to v4:
  - Restore the modification to cache-sets and cache-size in patch 6
  - Do not constrain renesas,r9a07g043f-ax45mp-cache since it's independent to
    this series.
  - Delete the redundant example added by patch 6

v3: https://lore.kernel.org/all/20250513094933.1631493-1-ben717@andestech.com/

Changelog from v2 to v3:
  - Rebase the series on Conor/riscv-soc-for-next
  - Reform patch 6 as suggested by Conor
  - Modify l2_cache's compatible in qilai.dtsi due to patch 6
  - Add Conor's Acked-by tag to patch 4
  - Add Conor's Acked-by tag to patch 5
  - Add Conor's Acked-by tag to patch 9

v2: https://lore.kernel.org/all/20250503151829.605006-5-ben717@andestech.com/

Changelog from v1 to v2:
  - Add detailed descriptions to PLIC_SW and PLMT0
  - Move the aliases node and memory node from qilai.dtsi to qilai-voyager.dts
  - Drop "status = okay" in each CPU node since the status property is by
    default "okay"
  - Reorder the nodes in qilai.dtsi by unit address in ascending order
  - Add myself as the maintainer of Andes's SoC tree
  - Add Rob's Reviewed-by tag to patch 2
  - Add Rob's Acked-by tag to patch 3
  - Add Rob's Acked-by tag to patch 6.

v1: https://lore.kernel.org/all/20250407104937.315783-1-ben717@andestech.com/

---
Ben Zong-You Xie (8):
  riscv: add Andes SoC family Kconfig support
  dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
  dt-bindings: interrupt-controller: add Andes QiLai PLIC
  dt-bindings: interrupt-controller: add Andes machine-level software
    interrupt controller
  dt-bindings: timer: add Andes machine timer
  riscv: dts: andes: add QiLai SoC device tree
  riscv: dts: andes: add Voyager board device tree
  riscv: defconfig: enable Andes SoC

 .../andestech,plicsw.yaml                     |  54 +++++
 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../devicetree/bindings/riscv/andes.yaml      |  25 +++
 .../bindings/timer/andestech,plmt0.yaml       |  53 +++++
 MAINTAINERS                                   |   9 +
 arch/riscv/Kconfig.errata                     |   2 +-
 arch/riscv/Kconfig.socs                       |   9 +
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/andes/Makefile            |   2 +
 arch/riscv/boot/dts/andes/qilai-voyager.dts   |  28 +++
 arch/riscv/boot/dts/andes/qilai.dtsi          | 186 ++++++++++++++++++
 arch/riscv/configs/defconfig                  |   1 +
 12 files changed, 370 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml
 create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
 create mode 100644 arch/riscv/boot/dts/andes/Makefile
 create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts
 create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi

--
2.34.1

[PATCH v5 1/8] riscv: add Andes SoC family Kconfig support

[Ben Zong-You Xie]

The first SoC in the Andes series is QiLai. It includes a high-performance
quad-core RISC-V AX45MP cluster and one NX27V vector processor.

For further information, refer to [1].

[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
 arch/riscv/Kconfig.errata | 2 +-
 arch/riscv/Kconfig.socs   | 9 +++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index e318119d570d..be76883704a6 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -12,7 +12,7 @@ config ERRATA_ANDES
 
 config ERRATA_ANDES_CMO
 	bool "Apply Andes cache management errata"
-	depends on ERRATA_ANDES && ARCH_R9A07G043
+	depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES)
 	select RISCV_DMA_NONCOHERENT
 	default y
 	help
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 8b503e54fa1b..2f1626daaad1 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,14 @@
 menu "SoC selection"
 
+config ARCH_ANDES
+	bool "Andes SoCs"
+	depends on MMU && !XIP_KERNEL
+	select ERRATA_ANDES
+	select ERRATA_ANDES_CMO
+	select AX45MP_L2_CACHE
+	help
+	  This enables support for Andes SoC platform hardware.
+
 config ARCH_MICROCHIP_POLARFIRE
 	def_bool ARCH_MICROCHIP
 
-- 
2.34.1

[PATCH v5 2/8] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings

[Ben Zong-You Xie]

Add DT binding documentation for the Andes QiLai SoC and the
Voyager development board.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
 .../devicetree/bindings/riscv/andes.yaml      | 25 +++++++++++++++++++
 MAINTAINERS                                   |  5 ++++
 2 files changed, 30 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml

diff --git a/Documentation/devicetree/bindings/riscv/andes.yaml b/Documentation/devicetree/bindings/riscv/andes.yaml
new file mode 100644
index 000000000000..aa1edf1fdec7
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/andes.yaml
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/andes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes SoC-based boards
+
+maintainers:
+  - Ben Zong-You Xie <ben717@andestech.com>
+
+description:
+  Andes SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - andestech,voyager
+          - const: andestech,qilai
+
+additionalProperties: true
diff --git a/MAINTAINERS b/MAINTAINERS
index e45559690b28..3777a6e83a6b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20947,6 +20947,11 @@ F:	drivers/irqchip/irq-riscv-intc.c
 F:	include/linux/irqchip/riscv-aplic.h
 F:	include/linux/irqchip/riscv-imsic.h
 
+RISC-V ANDES SoC Support
+M:	Ben Zong-You Xie <ben717@andestech.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/riscv/andes.yaml
+
 RISC-V ARCHITECTURE
 M:	Paul Walmsley <paul.walmsley@sifive.com>
 M:	Palmer Dabbelt <palmer@dabbelt.com>
-- 
2.34.1

[PATCH v5 3/8] dt-bindings: interrupt-controller: add Andes QiLai PLIC

[Ben Zong-You Xie]

Add a new compatible string for Andes QiLai PLIC.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 3dfe425909d1..7ae61518e9b7 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -53,6 +53,7 @@ properties:
     oneOf:
       - items:
           - enum:
+              - andestech,qilai-plic
               - renesas,r9a07g043-plic
           - const: andestech,nceplic100
       - items:
-- 
2.34.1

[PATCH v5 4/8] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller

[Ben Zong-You Xie]

Add the DT binding documentation for Andes machine-level software
interrupt controller.

In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
second time with all interrupt sources tied to zero as the software
interrupt controller (PLICSW). PLICSW can generate machine-level software
interrupts through programming its registers.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
This patch depends on patch 2
---
 .../andestech,plicsw.yaml                     | 54 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 55 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
new file mode 100644
index 000000000000..eb2eb611ac09
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes machine-level software interrupt controller
+
+description:
+  In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
+  second time with all interrupt sources tied to zero as the software interrupt
+  controller (PLIC_SW). PLIC_SW directly connects to the machine-mode
+  inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt
+  controller is the parent interrupt controller for PLIC_SW. PLIC_SW can
+  generate machine-mode inter-processor interrupts through programming its
+  registers.
+
+maintainers:
+  - Ben Zong-You Xie <ben717@andestech.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - andestech,qilai-plicsw
+      - const: andestech,plicsw
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 15872
+    description:
+      Specifies which harts are connected to the PLIC_SW. Each item must points
+      to a riscv,cpu-intc node, which has a riscv cpu node as parent.
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+
+examples:
+  - |
+    interrupt-controller@400000 {
+      compatible = "andestech,qilai-plicsw", "andestech,plicsw";
+      reg = <0x400000 0x400000>;
+      interrupts-extended = <&cpu0intc 3>,
+                            <&cpu1intc 3>,
+                            <&cpu2intc 3>,
+                            <&cpu3intc 3>;
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 3777a6e83a6b..b79cdd43fe37 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20950,6 +20950,7 @@ F:	include/linux/irqchip/riscv-imsic.h
 RISC-V ANDES SoC Support
 M:	Ben Zong-You Xie <ben717@andestech.com>
 S:	Maintained
+F:	Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
 F:	Documentation/devicetree/bindings/riscv/andes.yaml

 RISC-V ARCHITECTURE
--
2.34.1

[PATCH v5 5/8] dt-bindings: timer: add Andes machine timer

[Ben Zong-You Xie]

Add the DT binding documentation for Andes machine timer.

The RISC-V architecture defines a machine timer that provides a real-time
counter and generates timer interrupts. Andes machiner timer (PLMT0) is
the implementation of the machine timer, and it contains memory-mapped
registers (mtime and mtimecmp). This device supports up to 32 cores.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
This patch depends on patch 2 and patch 4
---
 .../bindings/timer/andestech,plmt0.yaml       | 53 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 54 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0.yaml

diff --git a/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml b/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
new file mode 100644
index 000000000000..90b612096004
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes machine-level timer
+
+description:
+  The Andes machine-level timer device (PLMT0) provides machine-level timer
+  functionality for a set of HARTs on a RISC-V platform. It has a single
+  fixed-frequency monotonic time counter (MTIME) register and a time compare
+  register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is
+  generated if MTIME >= MTIMECMP.
+
+maintainers:
+  - Ben Zong-You Xie <ben717@andestech.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - andestech,qilai-plmt
+      - const: andestech,plmt0
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 32
+    description:
+      Specifies which harts are connected to the PLMT0. Each item must points
+      to a riscv,cpu-intc node, which has a riscv cpu node as parent. The
+      PLMT0 supports 1 hart up to 32 harts.
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+
+examples:
+  - |
+    interrupt-controller@100000 {
+      compatible = "andestech,qilai-plmt", "andestech,plmt0";
+      reg = <0x100000 0x100000>;
+      interrupts-extended = <&cpu0intc 7>,
+                            <&cpu1intc 7>,
+                            <&cpu2intc 7>,
+                            <&cpu3intc 7>;
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index b79cdd43fe37..57a4b3789ef8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20952,6 +20952,7 @@ M:	Ben Zong-You Xie <ben717@andestech.com>
 S:	Maintained
 F:	Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
 F:	Documentation/devicetree/bindings/riscv/andes.yaml
+F:	Documentation/devicetree/bindings/timer/andestech,plmt0.yaml

 RISC-V ARCHITECTURE
 M:	Paul Walmsley <paul.walmsley@sifive.com>
--
2.34.1

[PATCH v5 6/8] riscv: dts: andes: add QiLai SoC device tree

[Ben Zong-You Xie]

Introduce the initial device tree support for the Andes QiLai SoC.

For further information, you can refer to [1].

[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
This patch depends on patch 2, patch 4, and patch 5.
Also, the compatible "andestech,qilai-ax45mp-cache" depends on https://git.kernel.org/conor/c/51b081cdb923
---
 MAINTAINERS                          |   2 +
 arch/riscv/boot/dts/andes/qilai.dtsi | 186 +++++++++++++++++++++++++++
 2 files changed, 188 insertions(+)
 create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi

diff --git a/MAINTAINERS b/MAINTAINERS
index 57a4b3789ef8..ceb51e1ecca0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20950,9 +20950,11 @@ F:	include/linux/irqchip/riscv-imsic.h
 RISC-V ANDES SoC Support
 M:	Ben Zong-You Xie <ben717@andestech.com>
 S:	Maintained
+T:	git: https://github.com/ben717-linux/linux
 F:	Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
 F:	Documentation/devicetree/bindings/riscv/andes.yaml
 F:	Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
+F:	arch/riscv/boot/dts/andes/

 RISC-V ARCHITECTURE
 M:	Paul Walmsley <paul.walmsley@sifive.com>
diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi
new file mode 100644
index 000000000000..de3de32f8c39
--- /dev/null
+++ b/arch/riscv/boot/dts/andes/qilai.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <62500000>;
+
+		cpu0: cpu@0 {
+			compatible = "andestech,ax45mp", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "xandespmu";
+			mmu-type = "riscv,sv39";
+			clock-frequency = <100000000>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <256>;
+			i-cache-line-size = <64>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <128>;
+			d-cache-line-size = <64>;
+			next-level-cache = <&l2_cache>;
+
+			cpu0_intc: interrupt-controller {
+				compatible = "andestech,cpu-intc", "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu1: cpu@1 {
+			compatible = "andestech,ax45mp", "riscv";
+			device_type = "cpu";
+			reg = <1>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "xandespmu";
+			mmu-type = "riscv,sv39";
+			clock-frequency = <100000000>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <256>;
+			i-cache-line-size = <64>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <128>;
+			d-cache-line-size = <64>;
+			next-level-cache = <&l2_cache>;
+
+			cpu1_intc: interrupt-controller {
+				compatible = "andestech,cpu-intc",
+					     "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu2: cpu@2 {
+			compatible = "andestech,ax45mp", "riscv";
+			device_type = "cpu";
+			reg = <2>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "xandespmu";
+			mmu-type = "riscv,sv39";
+			clock-frequency = <100000000>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <256>;
+			i-cache-line-size = <64>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <128>;
+			d-cache-line-size = <64>;
+			next-level-cache = <&l2_cache>;
+
+			cpu2_intc: interrupt-controller {
+				compatible = "andestech,cpu-intc",
+					     "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu3: cpu@3 {
+			compatible = "andestech,ax45mp", "riscv";
+			device_type = "cpu";
+			reg = <3>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "xandespmu";
+			mmu-type = "riscv,sv39";
+			clock-frequency = <100000000>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <256>;
+			i-cache-line-size = <64>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <128>;
+			d-cache-line-size = <64>;
+			next-level-cache = <&l2_cache>;
+
+			cpu3_intc: interrupt-controller {
+				compatible = "andestech,cpu-intc",
+					     "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		plmt: timer@100000 {
+			compatible = "andestech,qilai-plmt", "andestech,plmt0";
+			reg = <0x0 0x00100000 0x0 0x100000>;
+			interrupts-extended = <&cpu0_intc 7>,
+					      <&cpu1_intc 7>,
+					      <&cpu2_intc 7>,
+					      <&cpu3_intc 7>;
+		};
+
+		l2_cache: cache-controller@200000 {
+			compatible = "andestech,qilai-ax45mp-cache",
+				     "andestech,ax45mp-cache", "cache";
+			reg = <0x0 0x00200000 0x0 0x100000>;
+			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+			cache-line-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <0x200000>;
+			cache-unified;
+		};
+
+		plic_sw: interrupt-controller@400000 {
+			compatible = "andestech,qilai-plicsw",
+				     "andestech,plicsw";
+			reg = <0x0 0x00400000 0x0 0x400000>;
+			interrupts-extended = <&cpu0_intc 3>,
+					      <&cpu1_intc 3>,
+					      <&cpu2_intc 3>,
+					      <&cpu3_intc 3>;
+		};
+
+		plic: interrupt-controller@2000000 {
+			compatible = "andestech,qilai-plic",
+				     "andestech,nceplic100";
+			reg = <0x0 0x02000000 0x0 0x2000000>;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>;
+			riscv,ndev = <71>;
+		};
+
+		uart0: serial@30300000 {
+			compatible = "andestech,uart16550", "ns16550a";
+			reg = <0x0 0x30300000 0x0 0x100000>;
+			interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <50000000>;
+			reg-offset = <32>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			no-loopback-test;
+		};
+	};
+};
--
2.34.1

[PATCH v5 7/8] riscv: dts: andes: add Voyager board device tree

[Ben Zong-You Xie]

Introduce the device tree support for Voyager development board.

Currently only support booting into console with only uart,
other features will be added later.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
 arch/riscv/boot/dts/Makefile                |  1 +
 arch/riscv/boot/dts/andes/Makefile          |  2 ++
 arch/riscv/boot/dts/andes/qilai-voyager.dts | 28 +++++++++++++++++++++
 3 files changed, 31 insertions(+)
 create mode 100644 arch/riscv/boot/dts/andes/Makefile
 create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 64a898da9aee..3b99e91efa25 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 subdir-y += allwinner
+subdir-y += andes
 subdir-y += canaan
 subdir-y += microchip
 subdir-y += renesas
diff --git a/arch/riscv/boot/dts/andes/Makefile b/arch/riscv/boot/dts/andes/Makefile
new file mode 100644
index 000000000000..c545c668ef70
--- /dev/null
+++ b/arch/riscv/boot/dts/andes/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ANDES) += qilai-voyager.dtb
diff --git a/arch/riscv/boot/dts/andes/qilai-voyager.dts b/arch/riscv/boot/dts/andes/qilai-voyager.dts
new file mode 100644
index 000000000000..fa7d2b32a9b4
--- /dev/null
+++ b/arch/riscv/boot/dts/andes/qilai-voyager.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
+ */
+
+#include "qilai.dtsi"
+
+/ {
+	model = "Voyager";
+	compatible = "andestech,voyager", "andestech,qilai";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@400000000 {
+		device_type = "memory";
+		reg = <0x4 0x00000000 0x4 0x00000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
2.34.1

[PATCH v5 8/8] riscv: defconfig: enable Andes SoC

[Ben Zong-You Xie]

Enable Andes SoC config in defconfig to allow the default
upstream kernel to boot on Voyager board.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 3c8e16d71e17..c9214635fb2f 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 # CONFIG_SYSFS_SYSCALL is not set
 CONFIG_PROFILING=y
+CONFIG_ARCH_ANDES=y
 CONFIG_ARCH_MICROCHIP=y
 CONFIG_ARCH_SIFIVE=y
 CONFIG_ARCH_SOPHGO=y
-- 
2.34.1

Re: [PATCH v5 0/8] add Voyager board support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 4092 bytes --]

On Mon, Jun 02, 2025 at 02:07:39PM +0800, Ben Zong-You Xie wrote:
> The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
> including Andes QiLai SoC. This patch series adds minimal device tree
> files for the QiLai SoC and the Voyager board [1].
> 
> Now only support basic uart drivers to boot up into a basic console. Other
> features will be added later.
> 
> [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/

Ball is in your court now, after rc1 make a tree and get it in
linux-next, and then send a pr to soc@kernel.org with this new content.
Perhaps the defconfig should go separately, I can take that one if you
want.

Cheers,
Conor.

> ---
> Changelog from v4 to v5:
>   - Rebase the series on torvalds/master
>   - Clarify the patch dependencies (2 <- 4 <- 5 <- 6) in the patch description
> 
> v4: https://lore.kernel.org/all/20250514095350.3765716-1-ben717@andestech.com/
> 
> Changelog from v3 to v4:
>   - Restore the modification to cache-sets and cache-size in patch 6
>   - Do not constrain renesas,r9a07g043f-ax45mp-cache since it's independent to
>     this series.
>   - Delete the redundant example added by patch 6
> 
> v3: https://lore.kernel.org/all/20250513094933.1631493-1-ben717@andestech.com/
> 
> Changelog from v2 to v3:
>   - Rebase the series on Conor/riscv-soc-for-next
>   - Reform patch 6 as suggested by Conor
>   - Modify l2_cache's compatible in qilai.dtsi due to patch 6
>   - Add Conor's Acked-by tag to patch 4
>   - Add Conor's Acked-by tag to patch 5
>   - Add Conor's Acked-by tag to patch 9
> 
> v2: https://lore.kernel.org/all/20250503151829.605006-5-ben717@andestech.com/
> 
> Changelog from v1 to v2:
>   - Add detailed descriptions to PLIC_SW and PLMT0
>   - Move the aliases node and memory node from qilai.dtsi to qilai-voyager.dts
>   - Drop "status = okay" in each CPU node since the status property is by
>     default "okay"
>   - Reorder the nodes in qilai.dtsi by unit address in ascending order
>   - Add myself as the maintainer of Andes's SoC tree
>   - Add Rob's Reviewed-by tag to patch 2
>   - Add Rob's Acked-by tag to patch 3
>   - Add Rob's Acked-by tag to patch 6.
> 
> v1: https://lore.kernel.org/all/20250407104937.315783-1-ben717@andestech.com/
> 
> ---
> Ben Zong-You Xie (8):
>   riscv: add Andes SoC family Kconfig support
>   dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
>   dt-bindings: interrupt-controller: add Andes QiLai PLIC
>   dt-bindings: interrupt-controller: add Andes machine-level software
>     interrupt controller
>   dt-bindings: timer: add Andes machine timer
>   riscv: dts: andes: add QiLai SoC device tree
>   riscv: dts: andes: add Voyager board device tree
>   riscv: defconfig: enable Andes SoC
> 
>  .../andestech,plicsw.yaml                     |  54 +++++
>  .../sifive,plic-1.0.0.yaml                    |   1 +
>  .../devicetree/bindings/riscv/andes.yaml      |  25 +++
>  .../bindings/timer/andestech,plmt0.yaml       |  53 +++++
>  MAINTAINERS                                   |   9 +
>  arch/riscv/Kconfig.errata                     |   2 +-
>  arch/riscv/Kconfig.socs                       |   9 +
>  arch/riscv/boot/dts/Makefile                  |   1 +
>  arch/riscv/boot/dts/andes/Makefile            |   2 +
>  arch/riscv/boot/dts/andes/qilai-voyager.dts   |  28 +++
>  arch/riscv/boot/dts/andes/qilai.dtsi          | 186 ++++++++++++++++++
>  arch/riscv/configs/defconfig                  |   1 +
>  12 files changed, 370 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
>  create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml
>  create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
>  create mode 100644 arch/riscv/boot/dts/andes/Makefile
>  create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts
>  create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi
> 
> --
> 2.34.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v5 0/8] add Voyager board support

[Ben Zong-You Xie]

On Fri, Jun 06, 2025 at 05:00:06PM +0100, Conor Dooley wrote:
> [EXTERNAL MAIL]

> Date: Fri, 6 Jun 2025 17:00:06 +0100
> From: Conor Dooley <conor@kernel.org>
> To: Ben Zong-You Xie <ben717@andestech.com>
> Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
>  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
>  tglx@linutronix.de, daniel.lezcano@linaro.org,
>  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
>  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
>  tim609@andestech.com
> Subject: Re: [PATCH v5 0/8] add Voyager board support
> 
> On Mon, Jun 02, 2025 at 02:07:39PM +0800, Ben Zong-You Xie wrote:
> > The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
> > including Andes QiLai SoC. This patch series adds minimal device tree
> > files for the QiLai SoC and the Voyager board [1].
> > 
> > Now only support basic uart drivers to boot up into a basic console. Other
> > features will be added later.
> > 
> > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> 
> Ball is in your court now, after rc1 make a tree and get it in
> linux-next, and then send a pr to soc@kernel.org with this new content.
> Perhaps the defconfig should go separately, I can take that one if you
> want.
> 
> Cheers,
> Conor.

Hi Conor,

Thanks for your guidance on these patches. I will send a PR to
soc@kernel.org as you suggested.

For the defconfig patch, I'm happy for you to handle it. Just let me
know if there's anything specific you'd like me to include.

Thanks,
Ben

Re: [PATCH v5 0/8] add Voyager board support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1861 bytes --]

On Mon, Jun 09, 2025 at 08:06:07PM +0800, Ben Zong-You Xie wrote:
> On Fri, Jun 06, 2025 at 05:00:06PM +0100, Conor Dooley wrote:
> > [EXTERNAL MAIL]
> 
> > Date: Fri, 6 Jun 2025 17:00:06 +0100
> > From: Conor Dooley <conor@kernel.org>
> > To: Ben Zong-You Xie <ben717@andestech.com>
> > Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> >  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
> >  tglx@linutronix.de, daniel.lezcano@linaro.org,
> >  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
> >  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> >  tim609@andestech.com
> > Subject: Re: [PATCH v5 0/8] add Voyager board support
> > 
> > On Mon, Jun 02, 2025 at 02:07:39PM +0800, Ben Zong-You Xie wrote:
> > > The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
> > > including Andes QiLai SoC. This patch series adds minimal device tree
> > > files for the QiLai SoC and the Voyager board [1].
> > > 
> > > Now only support basic uart drivers to boot up into a basic console. Other
> > > features will be added later.
> > > 
> > > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> > 
> > Ball is in your court now, after rc1 make a tree and get it in
> > linux-next, and then send a pr to soc@kernel.org with this new content.
> > Perhaps the defconfig should go separately, I can take that one if you
> > want.
> > 
> > Cheers,
> > Conor.
> 
> Hi Conor,
> 
> Thanks for your guidance on these patches. I will send a PR to
> soc@kernel.org as you suggested.
> 
> For the defconfig patch, I'm happy for you to handle it. Just let me
> know if there's anything specific you'd like me to include.

Okay, I picked it up on the basis that you'll send this all to Arnd for
6.17

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v5 0/8] add Voyager board support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2165 bytes --]

On Mon, Jun 09, 2025 at 05:16:54PM +0100, Conor Dooley wrote:
> On Mon, Jun 09, 2025 at 08:06:07PM +0800, Ben Zong-You Xie wrote:
> > On Fri, Jun 06, 2025 at 05:00:06PM +0100, Conor Dooley wrote:
> > > [EXTERNAL MAIL]
> > 
> > > Date: Fri, 6 Jun 2025 17:00:06 +0100
> > > From: Conor Dooley <conor@kernel.org>
> > > To: Ben Zong-You Xie <ben717@andestech.com>
> > > Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> > >  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
> > >  tglx@linutronix.de, daniel.lezcano@linaro.org,
> > >  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
> > >  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> > >  tim609@andestech.com
> > > Subject: Re: [PATCH v5 0/8] add Voyager board support
> > > 
> > > On Mon, Jun 02, 2025 at 02:07:39PM +0800, Ben Zong-You Xie wrote:
> > > > The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
> > > > including Andes QiLai SoC. This patch series adds minimal device tree
> > > > files for the QiLai SoC and the Voyager board [1].
> > > > 
> > > > Now only support basic uart drivers to boot up into a basic console. Other
> > > > features will be added later.
> > > > 
> > > > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> > > 
> > > Ball is in your court now, after rc1 make a tree and get it in
> > > linux-next, and then send a pr to soc@kernel.org with this new content.
> > > Perhaps the defconfig should go separately, I can take that one if you
> > > want.
> > > 
> > > Cheers,
> > > Conor.
> > 
> > Hi Conor,
> > 
> > Thanks for your guidance on these patches. I will send a PR to
> > soc@kernel.org as you suggested.
> > 
> > For the defconfig patch, I'm happy for you to handle it. Just let me
> > know if there's anything specific you'd like me to include.
> 
> Okay, I picked it up on the basis that you'll send this all to Arnd for
> 6.17

Sorry, I think that was really poorly worded. I picked it up on the
basis that you're going to send the other patches in the series to Arnd
for 6.17.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v5 0/8] add Voyager board support

[Ben Zong-You Xie]

On Mon, Jun 09, 2025 at 05:17:50PM +0100, Conor Dooley wrote:
> [EXTERNAL MAIL]

> Date: Mon, 9 Jun 2025 17:17:50 +0100
> From: Conor Dooley <conor@kernel.org>
> To: Ben Zong-You Xie <ben717@andestech.com>
> Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
>  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
>  tglx@linutronix.de, daniel.lezcano@linaro.org,
>  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
>  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
>  tim609@andestech.com
> Subject: Re: [PATCH v5 0/8] add Voyager board support
> 
> On Mon, Jun 09, 2025 at 05:16:54PM +0100, Conor Dooley wrote:
> > On Mon, Jun 09, 2025 at 08:06:07PM +0800, Ben Zong-You Xie wrote:
> > > On Fri, Jun 06, 2025 at 05:00:06PM +0100, Conor Dooley wrote:
> > > > [EXTERNAL MAIL]
> > > 
> > > > Date: Fri, 6 Jun 2025 17:00:06 +0100
> > > > From: Conor Dooley <conor@kernel.org>
> > > > To: Ben Zong-You Xie <ben717@andestech.com>
> > > > Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> > > >  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
> > > >  tglx@linutronix.de, daniel.lezcano@linaro.org,
> > > >  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
> > > >  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> > > >  tim609@andestech.com
> > > > Subject: Re: [PATCH v5 0/8] add Voyager board support
> > > > 
> > > > On Mon, Jun 02, 2025 at 02:07:39PM +0800, Ben Zong-You Xie wrote:
> > > > > The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
> > > > > including Andes QiLai SoC. This patch series adds minimal device tree
> > > > > files for the QiLai SoC and the Voyager board [1].
> > > > > 
> > > > > Now only support basic uart drivers to boot up into a basic console. Other
> > > > > features will be added later.
> > > > > 
> > > > > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> > > > 
> > > > Ball is in your court now, after rc1 make a tree and get it in
> > > > linux-next, and then send a pr to soc@kernel.org with this new content.
> > > > Perhaps the defconfig should go separately, I can take that one if you
> > > > want.
> > > > 
> > > > Cheers,
> > > > Conor.
> > > 
> > > Hi Conor,
> > > 
> > > Thanks for your guidance on these patches. I will send a PR to
> > > soc@kernel.org as you suggested.
> > > 
> > > For the defconfig patch, I'm happy for you to handle it. Just let me
> > > know if there's anything specific you'd like me to include.
> > 
> > Okay, I picked it up on the basis that you'll send this all to Arnd for
> > 6.17
> 
> Sorry, I think that was really poorly worded. I picked it up on the
> basis that you're going to send the other patches in the series to Arnd
> for 6.17.

Hi Conor,

According to the SoC maintainer documentation [1], I should send a
patchset (not a PR) to soc@kernel.org. Since I'm not a submaintainer yet.
I think I should not sent a PR to the main SoC maintainer. Is that right?

Further, I have two questions about sending a patchset:   
1. Should I send v5 or start a new patchset?
2. Should I continue excluding the defconfig patch, as we discussed
   previously? I think it should be included now.

[1] https://docs.kernel.org/process/maintainer-soc.html#submitting-patches-to-the-main-soc-maintainers

Thanks,
Ben

Re: [PATCH v5 0/8] add Voyager board support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 3702 bytes --]

+CC Arnd,

On Thu, Jun 12, 2025 at 12:13:16AM +0800, Ben Zong-You Xie wrote:
> On Mon, Jun 09, 2025 at 05:17:50PM +0100, Conor Dooley wrote:
> > [EXTERNAL MAIL]
> 
> > Date: Mon, 9 Jun 2025 17:17:50 +0100
> > From: Conor Dooley <conor@kernel.org>
> > To: Ben Zong-You Xie <ben717@andestech.com>
> > Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> >  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
> >  tglx@linutronix.de, daniel.lezcano@linaro.org,
> >  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
> >  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> >  tim609@andestech.com
> > Subject: Re: [PATCH v5 0/8] add Voyager board support
> > 
> > On Mon, Jun 09, 2025 at 05:16:54PM +0100, Conor Dooley wrote:
> > > On Mon, Jun 09, 2025 at 08:06:07PM +0800, Ben Zong-You Xie wrote:
> > > > On Fri, Jun 06, 2025 at 05:00:06PM +0100, Conor Dooley wrote:
> > > > > [EXTERNAL MAIL]
> > > > 
> > > > > Date: Fri, 6 Jun 2025 17:00:06 +0100
> > > > > From: Conor Dooley <conor@kernel.org>
> > > > > To: Ben Zong-You Xie <ben717@andestech.com>
> > > > > Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> > > > >  alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
> > > > >  tglx@linutronix.de, daniel.lezcano@linaro.org,
> > > > >  prabhakar.mahadev-lad.rj@bp.renesas.com, devicetree@vger.kernel.org,
> > > > >  linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> > > > >  tim609@andestech.com
> > > > > Subject: Re: [PATCH v5 0/8] add Voyager board support
> > > > > 
> > > > > On Mon, Jun 02, 2025 at 02:07:39PM +0800, Ben Zong-You Xie wrote:
> > > > > > The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
> > > > > > including Andes QiLai SoC. This patch series adds minimal device tree
> > > > > > files for the QiLai SoC and the Voyager board [1].
> > > > > > 
> > > > > > Now only support basic uart drivers to boot up into a basic console. Other
> > > > > > features will be added later.
> > > > > > 
> > > > > > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> > > > > 
> > > > > Ball is in your court now, after rc1 make a tree and get it in
> > > > > linux-next, and then send a pr to soc@kernel.org with this new content.
> > > > > Perhaps the defconfig should go separately, I can take that one if you
> > > > > want.

> > > > Thanks for your guidance on these patches. I will send a PR to
> > > > soc@kernel.org as you suggested.
> > > > 
> > > > For the defconfig patch, I'm happy for you to handle it. Just let me
> > > > know if there's anything specific you'd like me to include.
> > > 
> > > Okay, I picked it up on the basis that you'll send this all to Arnd for
> > > 6.17
> > 
> > Sorry, I think that was really poorly worded. I picked it up on the
> > basis that you're going to send the other patches in the series to Arnd
> > for 6.17.
> 
> According to the SoC maintainer documentation [1], I should send a
> patchset (not a PR) to soc@kernel.org. Since I'm not a submaintainer yet.
> I think I should not sent a PR to the main SoC maintainer. Is that right?

I think you can send a PR and not worry about it.

> Further, I have two questions about sending a patchset:   
> 1. Should I send v5 or start a new patchset?
> 2. Should I continue excluding the defconfig patch, as we discussed
>    previously? I think it should be included now.

Arnd, you okay with a defconfig in the same branch as the dts/core
bindings for a new platform? I'll happily drop it from by branch if it
can all go as one.


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v5 0/8] add Voyager board support

[Arnd Bergmann]

On Wed, Jun 11, 2025, at 18:21, Conor Dooley wrote:
> On Thu, Jun 12, 2025 at 12:13:16AM +0800, Ben Zong-You Xie wrote:
>> On Mon, Jun 09, 2025 at 05:17:50PM +0100, Conor Dooley wrote:
>> > > > > 
>> > > > > Ball is in your court now, after rc1 make a tree and get it in
>> > > > > linux-next, and then send a pr to soc@kernel.org with this new content.
>> > > > > Perhaps the defconfig should go separately, I can take that one if you
>> > > > > want.
>
>> > > > Thanks for your guidance on these patches. I will send a PR to
>> > > > soc@kernel.org as you suggested.
>> > > > 
>> > > > For the defconfig patch, I'm happy for you to handle it. Just let me
>> > > > know if there's anything specific you'd like me to include.
>> > > 
>> > > Okay, I picked it up on the basis that you'll send this all to Arnd for
>> > > 6.17
>> > 
>> > Sorry, I think that was really poorly worded. I picked it up on the
>> > basis that you're going to send the other patches in the series to Arnd
>> > for 6.17.
>> 
>> According to the SoC maintainer documentation [1], I should send a
>> patchset (not a PR) to soc@kernel.org. Since I'm not a submaintainer yet.
>> I think I should not sent a PR to the main SoC maintainer. Is that right?
>
> I think you can send a PR and not worry about it.
>
>> Further, I have two questions about sending a patchset:   
>> 1. Should I send v5 or start a new patchset?
>> 2. Should I continue excluding the defconfig patch, as we discussed
>>    previously? I think it should be included now.
>
> Arnd, you okay with a defconfig in the same branch as the dts/core
> bindings for a new platform? I'll happily drop it from by branch if it
> can all go as one.

Sorry I missed your question earlier, I finally got to it now as
I am going through the pull requests in patchwork.

Having the defconfig, MAINTAINERS and Kconfig updates in the branch
for a new platform is fine, in this case it makes sense to keep
everything together.

I'm also planning to have multiple new SoC targets in 6.17 and
would put them into a separate branch that does not contain the
dts changes for the existing SoCs.

For the pull request that Ben sent, there were a couple of
mistakes, I'll reply on that separately. It probably would made
more sense to send the patches to soc@lists.linux.dev (note
that the soc@kernel.org address got renamed but they still
both work) than to send a pull request this time.

     Arnd

Re: [PATCH v5 0/8] add Voyager board support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 3036 bytes --]

On Thu, Jul 03, 2025 at 05:32:08PM +0200, Arnd Bergmann wrote:
> On Wed, Jun 11, 2025, at 18:21, Conor Dooley wrote:
> > On Thu, Jun 12, 2025 at 12:13:16AM +0800, Ben Zong-You Xie wrote:
> >> On Mon, Jun 09, 2025 at 05:17:50PM +0100, Conor Dooley wrote:
> >> > > > > 
> >> > > > > Ball is in your court now, after rc1 make a tree and get it in
> >> > > > > linux-next, and then send a pr to soc@kernel.org with this new content.
> >> > > > > Perhaps the defconfig should go separately, I can take that one if you
> >> > > > > want.
> >
> >> > > > Thanks for your guidance on these patches. I will send a PR to
> >> > > > soc@kernel.org as you suggested.
> >> > > > 
> >> > > > For the defconfig patch, I'm happy for you to handle it. Just let me
> >> > > > know if there's anything specific you'd like me to include.
> >> > > 
> >> > > Okay, I picked it up on the basis that you'll send this all to Arnd for
> >> > > 6.17
> >> > 
> >> > Sorry, I think that was really poorly worded. I picked it up on the
> >> > basis that you're going to send the other patches in the series to Arnd
> >> > for 6.17.
> >> 
> >> According to the SoC maintainer documentation [1], I should send a
> >> patchset (not a PR) to soc@kernel.org. Since I'm not a submaintainer yet.
> >> I think I should not sent a PR to the main SoC maintainer. Is that right?
> >
> > I think you can send a PR and not worry about it.
> >
> >> Further, I have two questions about sending a patchset:   
> >> 1. Should I send v5 or start a new patchset?
> >> 2. Should I continue excluding the defconfig patch, as we discussed
> >>    previously? I think it should be included now.
> >
> > Arnd, you okay with a defconfig in the same branch as the dts/core
> > bindings for a new platform? I'll happily drop it from by branch if it
> > can all go as one.
> 
> Sorry I missed your question earlier, I finally got to it now as
> I am going through the pull requests in patchwork.

Yeah, I've been kinda out of it lately. Ordinarily I'd have pinged you
on IRC or something, but instead this thread has just been sitting in my
devicetree mail folder.

> Having the defconfig, MAINTAINERS and Kconfig updates in the branch
> for a new platform is fine, in this case it makes sense to keep
> everything together.

Okay, I have dropped it from my config branch.

> I'm also planning to have multiple new SoC targets in 6.17 and
> would put them into a separate branch that does not contain the
> dts changes for the existing SoCs.
> 
> For the pull request that Ben sent, there were a couple of
> mistakes, I'll reply on that separately. It probably would made
> more sense to send the patches to soc@lists.linux.dev (note
> that the soc@kernel.org address got renamed but they still
> both work) than to send a pull request this time.

Is that a general comment btw? If there are other people coming in with
new platforms should I ask them to send patches to soc@lists.linux.dev
instead of a PR for their first time?


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v5 0/8] add Voyager board support

[Arnd Bergmann]

On Thu, Jul 3, 2025, at 17:53, Conor Dooley wrote:
> On Thu, Jul 03, 2025 at 05:32:08PM +0200, Arnd Bergmann wrote:
>> On Wed, Jun 11, 2025, at 18:21, Conor Dooley wrote:
>>
>> I'm also planning to have multiple new SoC targets in 6.17 and
>> would put them into a separate branch that does not contain the
>> dts changes for the existing SoCs.
>> 
>> For the pull request that Ben sent, there were a couple of
>> mistakes, I'll reply on that separately. It probably would made
>> more sense to send the patches to soc@lists.linux.dev (note
>> that the soc@kernel.org address got renamed but they still
>> both work) than to send a pull request this time.
>
> Is that a general comment btw? If there are other people coming in with
> new platforms should I ask them to send patches to soc@lists.linux.dev
> instead of a PR for their first time?

It's mainly about how comfortable the new maintainers are with
the process, in this case it was clearly a bit too much for
Ben to get right at the first time, but others are more
experienced with sending pull requests to kernel maintainers
already. Since the patches individually are all fine, I could
have just applied them, but the PR ended up having too many
mistakes.

The one thing that is special for a new platform is that the branch
can mix things that would otherwise be separate pull requests.
Sending this as patches means that I have more flexibility to
apply it either into a branch for the new platform or split it
up as normal.

    Arnd