* [PATCH v3 1/6] riscv: dts: microchip: add common board dtsi for icicle kit variants
2025-09-08 11:57 [PATCH v3 0/6] Icicle Kit with prod device and Discovery Kit support Valentina Fernandez
@ 2025-09-08 11:57 ` Valentina Fernandez
2025-09-08 11:57 ` [PATCH v3 2/6] dt-bindings: riscv: microchip: document icicle kit with production device Valentina Fernandez
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Valentina Fernandez @ 2025-09-08 11:57 UTC (permalink / raw)
To: conor.dooley, daire.mcnamara, paul.walmsley, palmer, robh,
krzk+dt, aou, alex, valentina.fernandezalanis
Cc: linux-riscv, linux-kernel, devicetree
In preparation for supporting the Icicle Kit with production silicon,
add a common board dtsi for the icicle kit with hardware shared by both
the engineering sample and production versions.
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
---
.../dts/microchip/mpfs-icicle-kit-common.dtsi | 247 ++++++++++++++++++
.../boot/dts/microchip/mpfs-icicle-kit.dts | 241 +----------------
2 files changed, 248 insertions(+), 240 deletions(-)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
new file mode 100644
index 000000000000..eafea3b69cd7
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2025 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-icicle-kit-fabric.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ ethernet0 = &mac1;
+ serial0 = &mmuart0;
+ serial1 = &mmuart1;
+ serial2 = &mmuart2;
+ serial3 = &mmuart3;
+ serial4 = &mmuart4;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-1 {
+ gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ label = "led1";
+ };
+
+ led-2 {
+ gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ label = "led2";
+ };
+
+ led-3 {
+ gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ label = "led3";
+ };
+
+ led-4 {
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ label = "led4";
+ };
+ };
+
+ ddrc_cache_lo: memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ status = "okay";
+ };
+
+ ddrc_cache_hi: memory@1040000000 {
+ device_type = "memory";
+ reg = <0x10 0x40000000 0x0 0x40000000>;
+ status = "okay";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hss_payload: region@BFC00000 {
+ reg = <0x0 0xBFC00000 0x0 0x400000>;
+ no-map;
+ };
+ };
+};
+
+&core_pwm0 {
+ status = "okay";
+};
+
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ power-monitor@10 {
+ compatible = "microchip,pac1934";
+ reg = <0x10>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@1 {
+ reg = <0x1>;
+ shunt-resistor-micro-ohms = <10000>;
+ label = "VDDREG";
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ shunt-resistor-micro-ohms = <10000>;
+ label = "VDDA25";
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ shunt-resistor-micro-ohms = <10000>;
+ label = "VDD25";
+ };
+
+ channel@4 {
+ reg = <0x4>;
+ shunt-resistor-micro-ohms = <10000>;
+ label = "VDDA_REG";
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&mac0 {
+ phy-mode = "sgmii";
+ phy-handle = <&phy0>;
+ status = "okay";
+};
+
+&mac1 {
+ phy-mode = "sgmii";
+ phy-handle = <&phy1>;
+ status = "okay";
+
+ phy1: ethernet-phy@9 {
+ reg = <9>;
+ };
+
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ };
+};
+
+&mbox {
+ status = "okay";
+};
+
+&mmc {
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&mmuart1 {
+ status = "okay";
+};
+
+&mmuart2 {
+ status = "okay";
+};
+
+&mmuart3 {
+ status = "okay";
+};
+
+&mmuart4 {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+};
+
+&refclk {
+ clock-frequency = <125000000>;
+};
+
+&refclk_ccc {
+ clock-frequency = <50000000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
+
+&syscontroller_qspi {
+ /*
+ * The flash *is* there, but Icicle kits that have engineering sample
+ * silicon (write?) access to this flash to non-functional. The system
+ * controller itself can actually access it, but the MSS cannot write
+ * an image there. Instantiating a coreQSPI in the fabric & connecting
+ * it to the flash instead should work though. Pre-production or later
+ * silicon does not have this issue.
+ */
+ status = "disabled";
+
+ sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <1>;
+ reg = <0>;
+ };
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index f80df225f72b..2cb08ed0946d 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -3,249 +3,10 @@
/dts-v1/;
-#include "mpfs.dtsi"
-#include "mpfs-icicle-kit-fabric.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
+#include "mpfs-icicle-kit-common.dtsi"
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
"microchip,mpfs";
-
- aliases {
- ethernet0 = &mac1;
- serial0 = &mmuart0;
- serial1 = &mmuart1;
- serial2 = &mmuart2;
- serial3 = &mmuart3;
- serial4 = &mmuart4;
- };
-
- chosen {
- stdout-path = "serial1:115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-1 {
- gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_RED>;
- label = "led1";
- };
-
- led-2 {
- gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_RED>;
- label = "led2";
- };
-
- led-3 {
- gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_AMBER>;
- label = "led3";
- };
-
- led-4 {
- gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_AMBER>;
- label = "led4";
- };
- };
-
- ddrc_cache_lo: memory@80000000 {
- device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x40000000>;
- status = "okay";
- };
-
- ddrc_cache_hi: memory@1040000000 {
- device_type = "memory";
- reg = <0x10 0x40000000 0x0 0x40000000>;
- status = "okay";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- hss_payload: region@BFC00000 {
- reg = <0x0 0xBFC00000 0x0 0x400000>;
- no-map;
- };
- };
-};
-
-&core_pwm0 {
- status = "okay";
-};
-
-&gpio2 {
- interrupts = <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-
- power-monitor@10 {
- compatible = "microchip,pac1934";
- reg = <0x10>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- channel@1 {
- reg = <0x1>;
- shunt-resistor-micro-ohms = <10000>;
- label = "VDDREG";
- };
-
- channel@2 {
- reg = <0x2>;
- shunt-resistor-micro-ohms = <10000>;
- label = "VDDA25";
- };
-
- channel@3 {
- reg = <0x3>;
- shunt-resistor-micro-ohms = <10000>;
- label = "VDD25";
- };
-
- channel@4 {
- reg = <0x4>;
- shunt-resistor-micro-ohms = <10000>;
- label = "VDDA_REG";
- };
- };
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&mac0 {
- phy-mode = "sgmii";
- phy-handle = <&phy0>;
- status = "okay";
-};
-
-&mac1 {
- phy-mode = "sgmii";
- phy-handle = <&phy1>;
- status = "okay";
-
- phy1: ethernet-phy@9 {
- reg = <9>;
- };
-
- phy0: ethernet-phy@8 {
- reg = <8>;
- };
-};
-
-&mbox {
- status = "okay";
-};
-
-&mmc {
- bus-width = <4>;
- disable-wp;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- status = "okay";
-};
-
-&mmuart1 {
- status = "okay";
-};
-
-&mmuart2 {
- status = "okay";
-};
-
-&mmuart3 {
- status = "okay";
-};
-
-&mmuart4 {
- status = "okay";
-};
-
-&pcie {
- status = "okay";
-};
-
-&qspi {
- status = "okay";
-};
-
-&refclk {
- clock-frequency = <125000000>;
-};
-
-&refclk_ccc {
- clock-frequency = <50000000>;
-};
-
-&rtc {
- status = "okay";
-};
-
-&spi0 {
- status = "okay";
-};
-
-&spi1 {
- status = "okay";
-};
-
-&syscontroller {
- status = "okay";
-};
-
-&syscontroller_qspi {
- /*
- * The flash *is* there, but Icicle kits that have engineering sample
- * silicon (write?) access to this flash to non-functional. The system
- * controller itself can actually access it, but the MSS cannot write
- * an image there. Instantiating a coreQSPI in the fabric & connecting
- * it to the flash instead should work though. Pre-production or later
- * silicon does not have this issue.
- */
- status = "disabled";
-
- sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <20000000>;
- spi-rx-bus-width = <1>;
- reg = <0>;
- };
-};
-
-&usb {
- status = "okay";
- dr_mode = "host";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v3 2/6] dt-bindings: riscv: microchip: document icicle kit with production device
2025-09-08 11:57 [PATCH v3 0/6] Icicle Kit with prod device and Discovery Kit support Valentina Fernandez
2025-09-08 11:57 ` [PATCH v3 1/6] riscv: dts: microchip: add common board dtsi for icicle kit variants Valentina Fernandez
@ 2025-09-08 11:57 ` Valentina Fernandez
2025-09-09 6:53 ` Krzysztof Kozlowski
2025-09-08 11:57 ` [PATCH v3 3/6] riscv: dts: microchip: add " Valentina Fernandez
` (4 subsequent siblings)
6 siblings, 1 reply; 10+ messages in thread
From: Valentina Fernandez @ 2025-09-08 11:57 UTC (permalink / raw)
To: conor.dooley, daire.mcnamara, paul.walmsley, palmer, robh,
krzk+dt, aou, alex, valentina.fernandezalanis
Cc: linux-riscv, linux-kernel, devicetree
With the introduction of the Icicle Kit using the production MPFS250T
device, it's necessary to distinguish it from the engineering sample
(-es) variant. Engineering samples cannot write to flash from the MSS,
as noted in the PolarFire SoC FPGA ES errata.
Add specific compatibles for the Icicle Kit with Production device
(MPFS250T) and Icicle Kit with Engineering Sample (MPFS250T_ES).
The icicle kit reference designs in the v2025.07 release include the
Mi-V IHC IP v2, used to send/receive data between clusters when
using Asymmetric Multiprocessing (AMP) mode.
In reference design releases prior to v2025.07, the MI-V IHC subsystem
was included as a proof of concept in the design prior to becoming an
IP available in the Libero catalog.
Among other improvements, the new Mi-V IHC IP v2 includes some
changes to the register map. For this reason, make use of a new
reference design compatible to denote that v2025.07 reference design
releases are not backwards compatible.
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 78ce76ae1b6d..8ddc5c02973e 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -18,10 +18,18 @@ properties:
const: '/'
compatible:
oneOf:
+ - items:
+ - const: microchip,mpfs-icicle-prod-reference-rtl-v2507
+ - const: microchip,mpfs-icicle-kit-prod
+ - const: microchip,mpfs-icicle-kit
+ - const: microchip,mpfs-prod
+ - const: microchip,mpfs
+
- items:
- enum:
- microchip,mpfs-icicle-reference-rtlv2203
- microchip,mpfs-icicle-reference-rtlv2210
+ - microchip,mpfs-icicle-es-reference-rtl-v2507
- const: microchip,mpfs-icicle-kit
- const: microchip,mpfs
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v3 2/6] dt-bindings: riscv: microchip: document icicle kit with production device
2025-09-08 11:57 ` [PATCH v3 2/6] dt-bindings: riscv: microchip: document icicle kit with production device Valentina Fernandez
@ 2025-09-09 6:53 ` Krzysztof Kozlowski
2025-09-09 8:35 ` Conor Dooley
0 siblings, 1 reply; 10+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-09 6:53 UTC (permalink / raw)
To: Valentina Fernandez
Cc: conor.dooley, daire.mcnamara, paul.walmsley, palmer, robh,
krzk+dt, aou, alex, linux-riscv, linux-kernel, devicetree
On Mon, Sep 08, 2025 at 12:57:28PM +0100, Valentina Fernandez wrote:
> With the introduction of the Icicle Kit using the production MPFS250T
> device, it's necessary to distinguish it from the engineering sample
> (-es) variant. Engineering samples cannot write to flash from the MSS,
> as noted in the PolarFire SoC FPGA ES errata.
>
> Add specific compatibles for the Icicle Kit with Production device
> (MPFS250T) and Icicle Kit with Engineering Sample (MPFS250T_ES).
>
> The icicle kit reference designs in the v2025.07 release include the
> Mi-V IHC IP v2, used to send/receive data between clusters when
> using Asymmetric Multiprocessing (AMP) mode.
>
> In reference design releases prior to v2025.07, the MI-V IHC subsystem
> was included as a proof of concept in the design prior to becoming an
> IP available in the Libero catalog.
>
> Among other improvements, the new Mi-V IHC IP v2 includes some
> changes to the register map. For this reason, make use of a new
> reference design compatible to denote that v2025.07 reference design
> releases are not backwards compatible.
>
> Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
> ---
> Documentation/devicetree/bindings/riscv/microchip.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
Why are you sending patches which are already applied? For two weeks?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/6] dt-bindings: riscv: microchip: document icicle kit with production device
2025-09-09 6:53 ` Krzysztof Kozlowski
@ 2025-09-09 8:35 ` Conor Dooley
0 siblings, 0 replies; 10+ messages in thread
From: Conor Dooley @ 2025-09-09 8:35 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Valentina Fernandez, conor.dooley, daire.mcnamara, paul.walmsley,
palmer, robh, krzk+dt, aou, alex, linux-riscv, linux-kernel,
devicetree
[-- Attachment #1: Type: text/plain, Size: 1642 bytes --]
On Tue, Sep 09, 2025 at 08:53:05AM +0200, Krzysztof Kozlowski wrote:
> On Mon, Sep 08, 2025 at 12:57:28PM +0100, Valentina Fernandez wrote:
> > With the introduction of the Icicle Kit using the production MPFS250T
> > device, it's necessary to distinguish it from the engineering sample
> > (-es) variant. Engineering samples cannot write to flash from the MSS,
> > as noted in the PolarFire SoC FPGA ES errata.
> >
> > Add specific compatibles for the Icicle Kit with Production device
> > (MPFS250T) and Icicle Kit with Engineering Sample (MPFS250T_ES).
> >
> > The icicle kit reference designs in the v2025.07 release include the
> > Mi-V IHC IP v2, used to send/receive data between clusters when
> > using Asymmetric Multiprocessing (AMP) mode.
> >
> > In reference design releases prior to v2025.07, the MI-V IHC subsystem
> > was included as a proof of concept in the design prior to becoming an
> > IP available in the Libero catalog.
> >
> > Among other improvements, the new Mi-V IHC IP v2 includes some
> > changes to the register map. For this reason, make use of a new
> > reference design compatible to denote that v2025.07 reference design
> > releases are not backwards compatible.
> >
> > Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
> > ---
> > Documentation/devicetree/bindings/riscv/microchip.yaml | 8 ++++++++
> > 1 file changed, 8 insertions(+)
>
> Why are you sending patches which are already applied? For two weeks?
That's probably my bad, I dropped the series when you had complaints
about the version that I applied and forgot to mention it.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 3/6] riscv: dts: microchip: add icicle kit with production device
2025-09-08 11:57 [PATCH v3 0/6] Icicle Kit with prod device and Discovery Kit support Valentina Fernandez
2025-09-08 11:57 ` [PATCH v3 1/6] riscv: dts: microchip: add common board dtsi for icicle kit variants Valentina Fernandez
2025-09-08 11:57 ` [PATCH v3 2/6] dt-bindings: riscv: microchip: document icicle kit with production device Valentina Fernandez
@ 2025-09-08 11:57 ` Valentina Fernandez
2025-09-08 11:57 ` [PATCH v3 4/6] riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes Valentina Fernandez
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Valentina Fernandez @ 2025-09-08 11:57 UTC (permalink / raw)
To: conor.dooley, daire.mcnamara, paul.walmsley, palmer, robh,
krzk+dt, aou, alex, valentina.fernandezalanis
Cc: linux-riscv, linux-kernel, devicetree
With the introduction of the Icicle Kit using the production MPFS250T
device, it's necessary to distinguish it from the engineering sample
(-es) variant. Engineering samples cannot write to flash from the MSS,
as noted in the PolarFire SoC FPGA ES errata.
Add a new device tree (mpfs-icicle-kit-prod.dts) for the production
board which includes the icicle kit common dtsi and enable the system
controller SPI flash, which is only accessible on production silicon.
Remove redundant board compatible from fabric dtsi and update board
compatibles for v2025.07 release, which includes Mi-V IHC v2 for AMP
cluster communication.
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
---
arch/riscv/boot/dts/microchip/Makefile | 1 +
.../dts/microchip/mpfs-icicle-kit-common.dtsi | 4 ++++
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 23 ++++++++++++++++---
.../dts/microchip/mpfs-icicle-kit-prod.dts | 23 +++++++++++++++++++
.../boot/dts/microchip/mpfs-icicle-kit.dts | 3 ++-
5 files changed, 50 insertions(+), 4 deletions(-)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index f51aeeb9fd3b..1e2f4e41bf0d 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit-prod.dtb
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
index eafea3b69cd7..5c7a8ffad85b 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
@@ -134,6 +134,10 @@ &i2c2 {
status = "okay";
};
+&ihc {
+ status = "okay";
+};
+
&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index a6dda55a2d1d..e673b676fd1a 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -2,9 +2,6 @@
/* Copyright (c) 2020-2021 Microchip Technology Inc */
/ {
- compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
- "microchip,mpfs";
-
core_pwm0: pwm@40000000 {
compatible = "microchip,corepwm-rtl-v4";
reg = <0x0 0x40000000 0x0 0xF0>;
@@ -26,6 +23,26 @@ i2c2: i2c@40000200 {
status = "disabled";
};
+ ihc: mailbox {
+ compatible = "microchip,sbi-ipc";
+ interrupt-parent = <&plic>;
+ interrupts = <180>, <179>, <178>, <177>;
+ interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ mailbox@50000000 {
+ compatible = "microchip,miv-ihc-rtl-v2";
+ reg = <0x0 0x50000000 0x0 0x1c000>;
+ interrupt-parent = <&plic>;
+ interrupts = <180>, <179>, <178>, <177>;
+ interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+ #mbox-cells = <1>;
+ microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
+ status = "disabled";
+ };
+
pcie: pcie@3000000000 {
compatible = "microchip,pcie-host-1.0";
#address-cells = <0x3>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
new file mode 100644
index 000000000000..8afedece89d1
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2025 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs-icicle-kit-common.dtsi"
+
+/ {
+ model = "Microchip PolarFire-SoC Icicle Kit (Production Silicon)";
+ compatible = "microchip,mpfs-icicle-prod-reference-rtl-v2507",
+ "microchip,mpfs-icicle-kit-prod",
+ "microchip,mpfs-icicle-kit",
+ "microchip,mpfs-prod",
+ "microchip,mpfs";
+};
+
+&syscontroller {
+ microchip,bitstream-flash = <&sys_ctrl_flash>;
+};
+
+&syscontroller_qspi {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 2cb08ed0946d..556aa9638282 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -7,6 +7,7 @@
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
- compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
+ compatible = "microchip,mpfs-icicle-es-reference-rtl-v2507",
+ "microchip,mpfs-icicle-kit",
"microchip,mpfs";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v3 4/6] riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes
2025-09-08 11:57 [PATCH v3 0/6] Icicle Kit with prod device and Discovery Kit support Valentina Fernandez
` (2 preceding siblings ...)
2025-09-08 11:57 ` [PATCH v3 3/6] riscv: dts: microchip: add " Valentina Fernandez
@ 2025-09-08 11:57 ` Valentina Fernandez
2025-09-08 11:57 ` [PATCH v3 5/6] dt-bindings: riscv: microchip: document Discovery Kit Valentina Fernandez
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Valentina Fernandez @ 2025-09-08 11:57 UTC (permalink / raw)
To: conor.dooley, daire.mcnamara, paul.walmsley, palmer, robh,
krzk+dt, aou, alex, valentina.fernandezalanis
Cc: linux-riscv, linux-kernel, devicetree
Rename the Clock Conditioning Circuit (CCC) reference clock to match
the fixed clock bindings naming recommendation.
Update the reserved memory regions in the Icicle Kit common dtsi to
use lowercase hex and drop the redundant status properties from the
memory regions, as they are not required.
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
---
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi | 6 ++----
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +-
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
index 5c7a8ffad85b..e01a216e6c3a 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
@@ -53,13 +53,11 @@ led-4 {
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
- status = "okay";
};
ddrc_cache_hi: memory@1040000000 {
device_type = "memory";
reg = <0x10 0x40000000 0x0 0x40000000>;
- status = "okay";
};
reserved-memory {
@@ -67,8 +65,8 @@ reserved-memory {
#size-cells = <2>;
ranges;
- hss_payload: region@BFC00000 {
- reg = <0x0 0xBFC00000 0x0 0x400000>;
+ hss_payload: region@bfc00000 {
+ reg = <0x0 0xbfc00000 0x0 0x400000>;
no-map;
};
};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index e673b676fd1a..71f724325578 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -74,7 +74,7 @@ pcie_intc: interrupt-controller {
};
};
- refclk_ccc: cccrefclk {
+ refclk_ccc: clock-cccref {
compatible = "fixed-clock";
#clock-cells = <0>;
};
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v3 5/6] dt-bindings: riscv: microchip: document Discovery Kit
2025-09-08 11:57 [PATCH v3 0/6] Icicle Kit with prod device and Discovery Kit support Valentina Fernandez
` (3 preceding siblings ...)
2025-09-08 11:57 ` [PATCH v3 4/6] riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes Valentina Fernandez
@ 2025-09-08 11:57 ` Valentina Fernandez
2025-09-08 11:57 ` [PATCH v3 6/6] riscv: dts: microchip: add a device tree for " Valentina Fernandez
2025-09-10 17:55 ` [PATCH v3 0/6] Icicle Kit with prod device and Discovery Kit support Conor Dooley
6 siblings, 0 replies; 10+ messages in thread
From: Valentina Fernandez @ 2025-09-08 11:57 UTC (permalink / raw)
To: conor.dooley, daire.mcnamara, paul.walmsley, palmer, robh,
krzk+dt, aou, alex, valentina.fernandezalanis
Cc: linux-riscv, linux-kernel, devicetree
The Discovery Kit (MPFS-DISCO-KIT) is a development board featuring
a Microchip PolarFire SoC MPFS095T.
Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 8ddc5c02973e..381d6eb6672e 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -33,6 +33,11 @@ properties:
- const: microchip,mpfs-icicle-kit
- const: microchip,mpfs
+ - items:
+ - const: microchip,mpfs-disco-kit-reference-rtl-v2507
+ - const: microchip,mpfs-disco-kit
+ - const: microchip,mpfs
+
- items:
- enum:
- aldec,tysom-m-mpfs250t-rev2
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v3 6/6] riscv: dts: microchip: add a device tree for Discovery Kit
2025-09-08 11:57 [PATCH v3 0/6] Icicle Kit with prod device and Discovery Kit support Valentina Fernandez
` (4 preceding siblings ...)
2025-09-08 11:57 ` [PATCH v3 5/6] dt-bindings: riscv: microchip: document Discovery Kit Valentina Fernandez
@ 2025-09-08 11:57 ` Valentina Fernandez
2025-09-10 17:55 ` [PATCH v3 0/6] Icicle Kit with prod device and Discovery Kit support Conor Dooley
6 siblings, 0 replies; 10+ messages in thread
From: Valentina Fernandez @ 2025-09-08 11:57 UTC (permalink / raw)
To: conor.dooley, daire.mcnamara, paul.walmsley, palmer, robh,
krzk+dt, aou, alex, valentina.fernandezalanis
Cc: linux-riscv, linux-kernel, devicetree
Add a minimal device tree for the Microchip PolarFire SoC Discovery Kit.
The Discovery Kit is a cost-optimized board based on PolarFire SoC
MPFS095T and features:
- 1 GB DDR4x16
- 1x Gigabit Ethernet
- 3x UARTs
- Raspberry Pi connector
- mikroBus connector
- microSD card connector
Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
---
arch/riscv/boot/dts/microchip/Makefile | 1 +
.../dts/microchip/mpfs-disco-kit-fabric.dtsi | 58 ++++++
.../boot/dts/microchip/mpfs-disco-kit.dts | 190 ++++++++++++++++++
3 files changed, 249 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index 1e2f4e41bf0d..345ed7a48cc1 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb
+dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-disco-kit.dtb
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit-prod.dtb
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
new file mode 100644
index 000000000000..ae8be7d6f392
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2025 Microchip Technology Inc */
+
+/ {
+ core_pwm0: pwm@40000000 {
+ compatible = "microchip,corepwm-rtl-v4";
+ reg = <0x0 0x40000000 0x0 0xF0>;
+ microchip,sync-update-mask = /bits/ 32 <0>;
+ #pwm-cells = <3>;
+ clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@40000200 {
+ compatible = "microchip,corei2c-rtl-v7";
+ reg = <0x0 0x40000200 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
+ interrupt-parent = <&plic>;
+ interrupts = <122>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ ihc: mailbox {
+ compatible = "microchip,sbi-ipc";
+ interrupt-parent = <&plic>;
+ interrupts = <180>, <179>, <178>, <177>;
+ interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ mailbox@50000000 {
+ compatible = "microchip,miv-ihc-rtl-v2";
+ reg = <0x0 0x50000000 0x0 0x1c000>;
+ interrupt-parent = <&plic>;
+ interrupts = <180>, <179>, <178>, <177>;
+ interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+ #mbox-cells = <1>;
+ microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
+ status = "disabled";
+ };
+
+ refclk_ccc: clock-cccref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+};
+
+&ccc_sw {
+ clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
+ <&refclk_ccc>, <&refclk_ccc>;
+ clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
+ "dll0_ref", "dll1_ref";
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
new file mode 100644
index 000000000000..c068b9bb5bfd
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2025 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-disco-kit-fabric.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Microchip PolarFire-SoC Discovery Kit";
+ compatible = "microchip,mpfs-disco-kit-reference-rtl-v2507",
+ "microchip,mpfs-disco-kit",
+ "microchip,mpfs";
+
+ aliases {
+ ethernet0 = &mac0;
+ serial4 = &mmuart4;
+ };
+
+ chosen {
+ stdout-path = "serial4:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-1 {
+ gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ label = "led1";
+ };
+
+ led-2 {
+ gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ label = "led2";
+ };
+
+ led-3 {
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ label = "led3";
+ };
+
+ led-4 {
+ gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ label = "led4";
+ };
+
+ led-5 {
+ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ label = "led5";
+ };
+
+ led-6 {
+ gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ label = "led6";
+ };
+
+ led-7 {
+ gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ label = "led7";
+ };
+
+ led-8 {
+ gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ label = "led8";
+ };
+ };
+
+ ddrc_cache_lo: memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hss_payload: region@bfc00000 {
+ reg = <0x0 0xbfc00000 0x0 0x400000>;
+ no-map;
+ };
+ };
+};
+
+&core_pwm0 {
+ status = "okay";
+};
+
+&gpio1 {
+ interrupts = <27>, <28>, <29>, <30>,
+ <31>, <32>, <33>, <47>,
+ <35>, <36>, <37>, <38>,
+ <39>, <40>, <41>, <42>,
+ <43>, <44>, <45>, <46>,
+ <47>, <48>, <49>, <50>;
+ status = "okay";
+};
+
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&ihc {
+ status = "okay";
+};
+
+&mac0 {
+ phy-mode = "sgmii";
+ phy-handle = <&phy0>;
+ status = "okay";
+
+ phy0: ethernet-phy@b {
+ reg = <0xb>;
+ };
+};
+
+&mbox {
+ status = "okay";
+};
+
+&mmc {
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ no-1-8-v;
+ status = "okay";
+};
+
+&mmuart1 {
+ status = "okay";
+};
+
+&mmuart4 {
+ status = "okay";
+};
+
+&refclk {
+ clock-frequency = <125000000>;
+};
+
+&refclk_ccc {
+ clock-frequency = <50000000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v3 0/6] Icicle Kit with prod device and Discovery Kit support
2025-09-08 11:57 [PATCH v3 0/6] Icicle Kit with prod device and Discovery Kit support Valentina Fernandez
` (5 preceding siblings ...)
2025-09-08 11:57 ` [PATCH v3 6/6] riscv: dts: microchip: add a device tree for " Valentina Fernandez
@ 2025-09-10 17:55 ` Conor Dooley
6 siblings, 0 replies; 10+ messages in thread
From: Conor Dooley @ 2025-09-10 17:55 UTC (permalink / raw)
To: Valentina Fernandez
Cc: conor.dooley, daire.mcnamara, paul.walmsley, palmer, robh,
krzk+dt, aou, alex, linux-riscv, linux-kernel, devicetree
[-- Attachment #1: Type: text/plain, Size: 997 bytes --]
On Mon, Sep 08, 2025 at 12:57:26PM +0100, Valentina Fernandez wrote:
> Hi all,
>
> With the introduction of the Icicle Kit with the production device
> (MPFS250T) to the market, it's necessary to distinguish it from the
> engineering sample (-es) variant. This is because engineering samples
> cannot write to flash from the MSS, as noted in the PolarFire SoC
> FPGA ES errata.
>
> This series adds a common board DTSI for the Icicle Kit, containing
> hardware shared by both the engineering sample and production
> versions, as well as a DTS for each Icicle Kit variant.
>
> The last two patches add support for the PolarFire SoC Discovery Kit
> board.
>
> Changes since v2:
> - rename ccc clock to clock-cccref to match fixed clock binding
>
> Changes since v1:
> - fix order of properties in mailbox nodes
> - drop redundant status property from ddrc_cache nodes
> - fix lowercase hex in reserved memory regions
I've replaced v1 with this version in my tree.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread