* [PATCH v2 0/4] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards
@ 2026-05-11 10:37 Josua Mayer
2026-05-11 10:37 ` [PATCH v2 1/4] dt-bindings: soc: " Josua Mayer
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Josua Mayer @ 2026-05-11 10:37 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, Josua Mayer
Add support for a variety of SolidRun RZ/G2 based SoMs and the
HummingBoard IIoT Evaluation board.
Bindings are added for all SolidRun RZ/G2 SoMs:
- RZ/G2L SYSTEM ON MODULE
https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2l-som/
- RZ/V2L SYSTEM ON MODULE
https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-v2l-som/
- RZ/G2LC SYSTEM ON MODULE
https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2lc-som/
- RZ/G2UL SYSTEM ON MODULE
https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2ul-som/
And each supported carrier board:
- HUMMINGBOARD RZ/G2L IIOT
https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
- HUMMINGBOARD RZ/G2L PRO
https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-sbc/
- HUMMINGBOARD RZ/G2LC BASE (Ripple)
https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2lc-base/
Device-tree are only added for the first board to reduce initial effort.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Changes in v2:
- Added relevant product page links to each commit description.
- Added product page links to cover letter, thanks Geert.
- Link to v1: https://lore.kernel.org/r/20260503-rzg2-sr-boards-v1-0-8545677f93ca@solid-run.com
---
Josua Mayer (4):
dt-bindings: soc: renesas: Add various SolidRun RZ/G2 based boards
arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb
arm64: dts: renesas: add support for solidrun rzv2l som and hb-iiot evb
arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb
.../devicetree/bindings/soc/renesas/renesas.yaml | 37 ++
arch/arm64/boot/dts/renesas/Makefile | 33 ++
.../dts/renesas/r9a07g044c2-hummingboard-iiot.dts | 20 +
.../dts/renesas/r9a07g044l2-hummingboard-iiot.dts | 16 +
.../dts/renesas/r9a07g054l2-hummingboard-iiot.dts | 16 +
.../renesas/rzg2l-hummingboard-iiot-common.dtsi | 580 +++++++++++++++++++++
.../renesas/rzg2l-hummingboard-iiot-microsd.dtso | 26 +
.../renesas/rzg2l-hummingboard-iiot-rs485-a.dtso | 21 +
.../renesas/rzg2l-hummingboard-iiot-rs485-b.dtso | 21 +
.../boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi | 49 ++
arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso | 44 ++
arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi | 420 +++++++++++++++
arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi | 373 +++++++++++++
13 files changed, 1656 insertions(+)
---
base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
change-id: 20260502-rzg2-sr-boards-37d556668a2d
Best regards,
--
Josua Mayer <josua@solid-run.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 1/4] dt-bindings: soc: renesas: Add various SolidRun RZ/G2 based boards
2026-05-11 10:37 [PATCH v2 0/4] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
@ 2026-05-11 10:37 ` Josua Mayer
2026-05-11 16:28 ` Conor Dooley
2026-05-11 10:37 ` [PATCH v2 2/4] arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb Josua Mayer
` (2 subsequent siblings)
3 siblings, 1 reply; 12+ messages in thread
From: Josua Mayer @ 2026-05-11 10:37 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, Josua Mayer
Add bindings for various SolidRun boards and System on Module built
around Renesas RZ/G2 family of SoCs:
- RZ/G2L SoM [1]
- RZ/V2L SoM [2]
(shares PCB with G2L and has very similar programming model)
- RZ/G2LC SoM [3]
- RZ/G2UL SoM [4]
(shares PCB with G2LC but programming model differs largely)
- HummingBoard IIoT [5] (RZ/G2L, RZ/V2L, RZ/G2LC)
- HummingBoard Pro [6] (RZ/G2L, RZ/V2L)
- HummingBoard Base (Ripple) [7] (RZ/G2L, RZ/V2L, RZ/G2LC, RZ/G2UL)
[1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2l-som/
[2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-v2l-som/
[3] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2lc-som/
[4] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2ul-som/
[5] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
[6] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-sbc/
[7] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2lc-base/
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../devicetree/bindings/soc/renesas/renesas.yaml | 37 ++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index 5c22c51b1533d..889d4c5e8cd1b 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -502,6 +502,14 @@ properties:
- renesas,r9a07g043u12 # RZ/G2UL Type-2
- const: renesas,r9a07g043
+ - description: SolidRun RZ/G2UL based boards
+ items:
+ - enum:
+ - solidrun,rzg2ul-hummingboard-ripple # SolidRun RZ/G2UL HummingBoard Ripple
+ - const: solidrun,rzg2ul-sr-som
+ - const: renesas,r9a07g043u12 # RZ/G2UL Type-2
+ - const: renesas,r9a07g043
+
- description: RZ/G2{L,LC} (R9A07G044)
items:
- enum:
@@ -513,6 +521,25 @@ properties:
- renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L
- const: renesas,r9a07g044
+ - description: SolidRun RZ/G2L based boards
+ items:
+ - enum:
+ - solidrun,rzg2l-hummingboard-iiot # SolidRun RZ/G2L HummingBoard IIoT
+ - solidrun,rzg2l-hummingboard-pro # SolidRun RZ/G2L HummingBoard Pro
+ - solidrun,rzg2l-hummingboard-ripple # SolidRun RZ/G2L HummingBoard Ripple
+ - const: solidrun,rzg2l-sr-som
+ - const: renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L
+ - const: renesas,r9a07g044
+
+ - description: SolidRun RZ/G2LC based boards
+ items:
+ - enum:
+ - solidrun,rzg2lc-hummingboard-iiot # SolidRun RZ/G2LC HummingBoard IIoT
+ - solidrun,rzg2lc-hummingboard-ripple # SolidRun RZ/G2LC HummingBoard Ripple
+ - const: solidrun,rzg2lc-sr-som
+ - const: renesas,r9a07g044c2 # Dual Cortex-A55 RZ/G2LC
+ - const: renesas,r9a07g044
+
- items:
- enum:
# MYIR Remi Pi SBC (MYB-YG2LX-REMI)
@@ -529,6 +556,16 @@ properties:
- renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
- const: renesas,r9a07g054
+ - description: SolidRun RZ/V2L based boards
+ items:
+ - enum:
+ - solidrun,rzv2l-hummingboard-iiot # SolidRun RZ/V2L HummingBoard IIoT
+ - solidrun,rzv2l-hummingboard-pro # SolidRun RZ/V2L HummingBoard Pro
+ - solidrun,rzv2l-hummingboard-ripple # SolidRun RZ/V2L HummingBoard Ripple
+ - const: solidrun,rzv2l-sr-som
+ - const: renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
+ - const: renesas,r9a07g054
+
- description: RZ/G3S (R9A08G045)
items:
- enum:
--
2.51.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 2/4] arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb
2026-05-11 10:37 [PATCH v2 0/4] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
2026-05-11 10:37 ` [PATCH v2 1/4] dt-bindings: soc: " Josua Mayer
@ 2026-05-11 10:37 ` Josua Mayer
2026-05-12 2:28 ` sashiko-bot
2026-05-11 10:37 ` [PATCH v2 3/4] arm64: dts: renesas: add support for solidrun rzv2l " Josua Mayer
2026-05-11 10:37 ` [PATCH v2 4/4] arm64: dts: renesas: add support for solidrun rzg2lc " Josua Mayer
3 siblings, 1 reply; 12+ messages in thread
From: Josua Mayer @ 2026-05-11 10:37 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, Josua Mayer
Add support for the SolidRun RZ/G2L SoM [1] on Hummingboard IIoT [2].
The SoM features:
- 2x 1Gbps Ethernet with PHY
- eMMC
- 1/2GB DDR
- WiFi + Bluetooth
- SDHI Mux switching between eMMC and Carrier Board
The HummingBoard IIoT features:
- 3x USB-2.0 Type A connector
- 2x 1Gbps RJ45 Ethernet
- USB Type-C Console Port
- microSD connector
- RTC with backup battery
- RGB Status LED
- 1x M.2 B-Key connector with USB-2.0 + SIM card holder
- 1x DSI Display Connector
- GPIO header
- 2x RS232/RS485 ports (configurable)
- 2x CAN
Descriptions for eMMC, microSD and RS485 are provided as overlays due to
their dependency on configurable mux states.
[1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2l-som/
[2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/renesas/Makefile | 13 +
.../dts/renesas/r9a07g044l2-hummingboard-iiot.dts | 16 +
.../renesas/rzg2l-hummingboard-iiot-common.dtsi | 580 +++++++++++++++++++++
.../renesas/rzg2l-hummingboard-iiot-microsd.dtso | 26 +
.../renesas/rzg2l-hummingboard-iiot-rs485-a.dtso | 21 +
.../renesas/rzg2l-hummingboard-iiot-rs485-b.dtso | 21 +
.../boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi | 49 ++
arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso | 44 ++
arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi | 420 +++++++++++++++
9 files changed, 1190 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index ca45d2857ea7f..37cfefe66a308 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -169,6 +169,19 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo
r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-sr-som-emmc.dtbo
+r9a07g044l2-hummingboard-iiot-emmc-dtbs += r9a07g044l2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-emmc.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-microsd.dtbo
+r9a07g044l2-hummingboard-iiot-microsd-dtbs += r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-microsd.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-a.dtbo
+r9a07g044l2-hummingboard-iiot-rs485-a-dtbs += r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-rs485-a.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-b.dtbo
+r9a07g044l2-hummingboard-iiot-rs485-b-dtbs += r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-rs485-b.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-remi-pi.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-hummingboard-iiot.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-hummingboard-iiot.dts
new file mode 100644
index 0000000000000..eba4f423c8f05
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-hummingboard-iiot.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include "r9a07g044l2.dtsi"
+#include "rzg2l-sr-som.dtsi"
+#include "rzg2l-hummingboard-iiot.dtsi"
+
+/ {
+ compatible = "solidrun,rzg2l-hummingboard-iiot", "solidrun,rzg2l-sr-som",
+ "renesas,r9a07g044l2", "renesas,r9a07g044";
+ model = "SolidRun RZ/G2L HummingBoard IIoT";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi
new file mode 100644
index 0000000000000..ff2c42bcffe2f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi
@@ -0,0 +1,580 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+/ {
+ /* power for M.2 B-Key connector (J6) */
+ regulator-m2-b {
+ compatible = "regulator-fixed";
+ regulator-name = "m2-b";
+ gpios = <&tca6416_u20 5 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ enable-active-high;
+ };
+
+ /* power for M.2 M-Key connector (J4) */
+ regulator-m2-m {
+ compatible = "regulator-fixed";
+ regulator-name = "m2-m";
+ gpios = <&tca6416_u20 6 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ enable-active-high;
+ };
+
+ /* power for USB-A J27 behind USB Hub Port 3 */
+ regulator-vbus-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus2";
+ regulator-always-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ gpio = <&tca6416_u20 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ /* power for USB-A J27 behind USB Hub Port 4 */
+ regulator-vbus-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus3";
+ regulator-always-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ gpio = <&tca6416_u20 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ aliases {
+ gpio1 = &tca6408_u48;
+ gpio2 = &tca6408_u37;
+ gpio3 = &tca6416_u20;
+ gpio4 = &tca6416_u21;
+ i2c3 = &i2c_exp;
+ i2c4 = &i2c_csi;
+ i2c5 = &i2c_dsi;
+ i2c6 = &i2c_lvds;
+ rtc0 = &carrier_rtc;
+ rtc1 = &pmic;
+ serial3 = &scif3;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ wakeup-event {
+ interrupts-extended = <&tca6416_u21 11 IRQ_TYPE_EDGE_FALLING>;
+ label = "m2-m-wakeup";
+ wakeup-source;
+ linux,code = <KEY_WAKEUP>;
+ };
+ };
+
+ can_mux: mux-controller-1 {
+ compatible = "gpio-mux";
+ /* default J9-55/57/59/61 to on-board transceivers */
+ idle-state = <0>;
+ #mux-control-cells = <0>;
+ /*
+ * Mux routes CAN bus signals between SoM connector pins,
+ * expansion connector (J22) and on-board transceivers using
+ * two GPIO:
+ * - IO3: 0 = on-board transceivers, 1 = expansion connector
+ * - IO4: 0 = J9-55/57/59/61, 1 = J7-12/16 & J9-54/56
+ */
+ mux-gpios = <&tca6416_u20 3 GPIO_ACTIVE_HIGH>,
+ <&tca6416_u20 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ spi_mux: mux-controller-2 {
+ compatible = "gpio-mux";
+ /* default on-board */
+ idle-state = <0>;
+ /*
+ * Mux switches spi bus between on-board tpm
+ * and expansion connector (J22).
+ */
+ mux-gpios = <&tca6416_u21 0 GPIO_ACTIVE_HIGH>;
+ #mux-control-cells = <0>;
+ };
+
+ scif1_scif3_b2b_mux: mux-controller-3 {
+ compatible = "gpio-mux";
+ /* default on-board */
+ idle-state = <0>;
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches both scif1 and scif3 tx/rx between expansion
+ * connector (J22) and on-board rs232/rs485 transceivers
+ * using one GPIO: 0 = on-board, 1 = connector.
+ */
+ mux-gpios = <&tca6416_u20 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ scif1_rs_232_485_mux: mux-controller-4 {
+ compatible = "gpio-mux";
+ /* default rs232 */
+ idle-state = <0>;
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches scif1 tx/rx between rs232 and rs485
+ * transceivers. using one GPIO: 0 = rs232, 1 = rs485.
+ */
+ mux-gpios = <&tca6416_u20 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ scif3_rs_232_485_mux: mux-controller-5 {
+ compatible = "gpio-mux";
+ /* default rs232 */
+ idle-state = <0>;
+ #mux-control-cells = <0>;
+ /*
+ * Mux switches scif3 tx/rx between rs232 and rs485
+ * transceivers. using one GPIO: 0 = rs232, 1 = rs485.
+ */
+ mux-gpios = <&tca6416_u20 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ v_1_2: regulator-1-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v2";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ };
+
+ v_3_3: regulator-3-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ };
+
+ reg_dsi_panel: regulator-dsi-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "dsi-panel";
+ gpios = <&tca6416_u20 15 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <11200000>;
+ regulator-min-microvolt = <11200000>;
+ enable-active-high;
+ };
+
+ vmmc: regulator-mmc {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ startup-delay-us = <250>;
+ vin-supply = <&v_3_3>;
+ gpio = <&pinctrl RZG2L_GPIO(4, 1) GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ };
+
+ /* power for USB-A J5003 */
+ vbus1: regulator-vbus-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus1";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ gpio = <&tca6416_u20 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ rfkill-m2-b-gnss {
+ compatible = "rfkill-gpio";
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&tca6416_u20 10 GPIO_ACTIVE_HIGH>;
+ label = "m2-b gnss";
+ radio-type = "gps";
+ };
+
+ rfkill-m2-b-wwan {
+ compatible = "rfkill-gpio";
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&tca6416_u20 9 GPIO_ACTIVE_HIGH>;
+ label = "m2-b radio";
+ radio-type = "wwan";
+ };
+};
+
+&ehci1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub_2_0: hub@1 {
+ compatible = "usb4b4,6502", "usb4b4,6506";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>;
+ vdd2-supply = <&v_3_3>;
+ vdd-supply = <&v_1_2>;
+ };
+
+ /* this device is not visible because host supports 2.0 only */
+ hub_3_0: hub@2 {
+ compatible = "usb4b4,6500", "usb4b4,6504";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>;
+ vdd2-supply = <&v_3_3>;
+ vdd-supply = <&v_1_2>;
+ };
+};
+
+&i2c0 {
+ /* highest i2c clock supported by all peripherals is 400kHz */
+
+ tca6416_u20: gpio@20 {
+ compatible = "ti,tcal6416";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names = "TCA_INT/EXT_UART", "TCA_UARTA_232/485",
+ "TCA_UARTB_232/485", "TCA_INT/EXT_CAN",
+ "TCA_NXP/REN", "TCA_M.2B_3V3_EN",
+ "TCA_M.2M_3V3_EN", "TCA_M.2M_RESET#",
+ "TCA_M.2B_RESET#", "TCA_M.2B_W_DIS#",
+ "TCA_M.2B_GPS_EN#", "TCA_USB-HUB_RST#",
+ "TCA_USB_HUB3_PWR_EN", "TCA_USB_HUB4_PWR_EN",
+ "TCA_USB1_PWR_EN", "TCA_VIDEO_PWR_EN";
+
+ m2-b-reset-hog {
+ gpios = <8 GPIO_ACTIVE_LOW>;
+ gpio-hog;
+ line-name = "m2-b-reset";
+ output-low;
+ };
+
+ m2-m-reset-hog {
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ gpio-hog;
+ line-name = "m2-m-reset";
+ /*
+ * M.2 Key-M connector only supports PCI,
+ * but RZ/G2L(C) has no pci controller.
+ * Keep any card in reset.
+ */
+ output-high;
+ };
+ };
+
+ tca6416_u21: gpio@21 {
+ compatible = "ti,tcal6416";
+ reg = <0x21>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names = "TCA_SPI_TPM/EXT", "TCA_TPM_RST#",
+ "TCA_I2C_RST", "TCA_RS232_SHTD#",
+ "TCA_LCD_I2C_RST", "TCA_DIG_OUT1",
+ "TCA_bDIG_IN1", "TCA_SENS_INT",
+ "TCA_ALERT#", "TCA_TPM_PIRQ#",
+ "TCA_RTC_INT", "TCA_M.2M_WAKW_ON_LAN",
+ "TCA_M.2M_CLKREQ#", "TCA_LVDS_INT#",
+ "", "TCA_POE_AT";
+ interrupts-extended = <&pinctrl RZG2L_GPIO(4, 0) IRQ_TYPE_EDGE_FALLING>;
+
+ lcd-i2c-reset-hog {
+ gpios = <4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
+ line-name = "lcd-i2c-reset";
+ output-low;
+ /*
+ * reset shared between U37 and U48, to be
+ * supported once gpio-pca953x switches to
+ * reset framework.
+ */
+ gpio-hog;
+ };
+
+ lvds-irq-hog {
+ gpios = <13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP | GPIO_OPEN_DRAIN)>;
+ gpio-hog;
+ input;
+ line-name = "lvds-irq";
+ };
+
+ m2-m-clkreq-hog {
+ gpios = <12 GPIO_ACTIVE_LOW>;
+ gpio-hog;
+ input;
+ line-name = "m2-m-clkreq";
+ };
+
+ rs232_shutdown: rs232-shutdown-hog {
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ gpio-hog;
+ line-name = "rs232-shutdown";
+ output-low;
+ };
+
+ sensor-irq-hog {
+ gpios = <7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP | GPIO_OPEN_DRAIN)>;
+ gpio-hog;
+ input;
+ line-name = "sensor-irq";
+ };
+
+ tpm-irq-hog {
+ gpios = <9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP | GPIO_OPEN_DRAIN)>;
+ gpio-hog;
+ input;
+ line-name = "tpm-irq";
+ };
+ };
+
+ led-controller@30 {
+ compatible = "ti,lp5562";
+ reg = <0x30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* use internal clock, could use external generated by rtc */
+ clock-mode = /bits/ 8 <1>;
+
+ multi-led@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ color = <LED_COLOR_ID_RGB>;
+ label = "D7";
+
+ led@0 {
+ reg = <0x0>;
+ color = <LED_COLOR_ID_RED>;
+ led-cur = /bits/ 8 <0x32>;
+ max-cur = /bits/ 8 <0x64>;
+ };
+
+ led@1 {
+ reg = <0x1>;
+ color = <LED_COLOR_ID_GREEN>;
+ led-cur = /bits/ 8 <0x19>;
+ max-cur = /bits/ 8 <0x32>;
+ };
+
+ led@2 {
+ reg = <0x2>;
+ color = <LED_COLOR_ID_BLUE>;
+ led-cur = /bits/ 8 <0x19>;
+ max-cur = /bits/ 8 <0x32>;
+ };
+ };
+
+ led@3 {
+ reg = <0x3>;
+ chan-name = "D8";
+ color = <LED_COLOR_ID_GREEN>;
+ label = "D8";
+ led-cur = /bits/ 8 <0x19>;
+ max-cur = /bits/ 8 <0x64>;
+ };
+ };
+
+ light-sensor@44 {
+ compatible = "isil,isl29023";
+ reg = <0x44>;
+ /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */
+ interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ accelerometer@53 {
+ compatible = "adi,adxl345";
+ reg = <0x53>;
+ interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>;
+ /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */
+ interrupt-names = "INT1";
+ };
+
+ carrier_eeprom: eeprom@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <8>;
+ };
+
+ carrier_rtc: rtc@69 {
+ compatible = "abracon,ab1805";
+ reg = <0x69>;
+ /*
+ * AM1805 RTC used on this board has only nTIRQ pins wired,
+ * which is for countdown timer irqs only.
+ * Driver does not support this, disable for now.
+ *
+ * interrupts-extended = <&tca6416_u21 10 IRQ_TYPE_EDGE_FALLING>;
+ */
+ abracon,tc-diode = "schottky";
+ abracon,tc-resistor = <3>;
+ };
+};
+
+&i2c1 {
+ /* highest i2c clock supported by all peripherals is 400kHz */
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /*
+ * This reset is open drain,
+ * but reset core does not support GPIO_OPEN_DRAIN flag.
+ */
+ reset-gpios = <&tca6416_u21 2 GPIO_ACTIVE_LOW>;
+
+ /* channel 0 routed to expansion connector (J22) */
+ i2c_exp: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* channel 1 routed to mipi-csi connector (J23) */
+ i2c_csi: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* channel 2 routed to mipi-dsi connector (J25) */
+ i2c_dsi: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6408_u48: gpio@21 {
+ compatible = "ti,tca6408";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-line-names = "CAM_RST#", "DSI_RESET",
+ "DSI_STBYB", "DSI_PWM_BL",
+ "DSI_L/R", "DSI_U/D",
+ "DSI_CTP_/RST", "CAM_TRIG";
+ /*
+ * reset shared between U37 and U48, to be
+ * supported once gpio-pca953x switches to
+ * reset framework.
+ *
+ * reset-gpios = <&tca6416_u21 4
+ * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
+ */
+ gpio-controller;
+ };
+ };
+
+ /* channel 2 routed to lvds connector (J24) */
+ i2c_lvds: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6408_u37: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-line-names = "SELB", "LVDS_RESET",
+ "LVDS_STBYB", "LVDS_PWM_BL",
+ "LVDS_L/R", "LVDS_U/D",
+ "LVDS_CTP_/RST", "";
+ /*
+ * reset shared between U37 and U48, to be
+ * supported once gpio-pca953x switches to
+ * reset framework.
+ *
+ * reset-gpios = <&tca6416_u21 4
+ * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
+ */
+ gpio-controller;
+ };
+ };
+ };
+};
+
+&phy0 {
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* LED_0 pin */
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "keep";
+ function = LED_FUNCTION_LAN;
+ };
+ };
+};
+
+&pinctrl {
+ /* UARTA */
+ scif1_pins: scif1 {
+ pinmux = <RZG2L_PORT_PINMUX(40, 1, 1)>, /* SCIF1_RXD */
+ <RZG2L_PORT_PINMUX(40, 0, 1)>; /* SCIF1_TXD */
+ };
+
+ /* UARTA_RTS */
+ scif1_rts_pins: scif1-rts {
+ pinmux = <RZG2L_PORT_PINMUX(41, 1, 0)>; /* P41_1 */
+ };
+
+ /* UARTB */
+ scif3_pins: scif3 {
+ pinmux = <RZG2L_PORT_PINMUX(0, 1, 5)>, /* SCIF3_RXD */
+ <RZG2L_PORT_PINMUX(0, 0, 5)>; /* SCIF3_TXD */
+ };
+
+ /* UARTB_RTS */
+ scif3_rts_pins: scif3-rts {
+ pinmux = <RZG2L_PORT_PINMUX(41, 0, 0)>; /* P41_0 */
+ };
+};
+
+&scif1 {
+ pinctrl-0 = <&scif1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scif3 {
+ pinctrl-0 = <&scif3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&spi1 {
+ /* native cs does not support cs persistence required for tpm */
+ cs-gpios = <&pinctrl RZG2L_GPIO(44, 3) GPIO_ACTIVE_LOW>;
+ num-cs = <1>;
+ pinctrl-0 = <&spi1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ spi1_muxed: spi@0 {
+ compatible = "spi-mux";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mux-controls = <&spi_mux>;
+ /* mux bandwidth is 2GHz, soc max. spi clock is P0/2 = 50MHz */
+ spi-max-frequency = <50000000>;
+
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ interrupts-extended = <&tca6416_u21 9 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&tca6416_u21 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ spi-max-frequency = <43000000>;
+ };
+ };
+};
+
+&usb2_phy0 {
+ dr_mode = "host";
+ vbus-supply = <&vbus1>;
+};
+
+&usb2_phy1 {
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-microsd.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-microsd.dtso
new file mode 100644
index 0000000000000..aa85054efa0c4
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-microsd.dtso
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+* Device Tree Overlay for the RZ/G2L(C) Solidrun SOM SD
+*
+* Copyright (C) 2024 SolidRun Ltd.
+*/
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+&sdhi0 {
+ bus-width = <4>;
+ full-pwr-cycle;
+ mux-states = <&sdhi0_mux 1>;
+ pinctrl-0 = <&sdhi0_pins>, <&sdhi0_cd_pins>;
+ pinctrl-1 = <&sdhi0_uhs_pins>, <&sdhi0_cd_pins>;
+ pinctrl-names = "default", "state_uhs";
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ vmmc-supply = <&vmmc>;
+ vqmmc-supply = <®_pmic_ldo1>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso
new file mode 100644
index 0000000000000..886f4d4ecd67f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ *
+ * Overlay for enabling HummingBoard IIoT on-board RS485 Port A on connector J5004.
+ *
+ * Because Renesas uart driver does not support rs485,
+ * users must manually toggle P41_1 between RX & TX.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&scif1 {
+ pinctrl-0 = <&scif1_pins>, <&scif1_rts_pins>;
+};
+
+&scif1_rs_232_485_mux {
+ /* select rs485 */
+ idle-state = <1>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-b.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-b.dtso
new file mode 100644
index 0000000000000..9cad7e2834f39
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-b.dtso
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ *
+ * Overlay for enabling HummingBoard IIoT on-board RS485 Port B on connector J5004.
+ *
+ * Because Renesas uart driver does not support rs485,
+ * users must manually toggle P41_0 between RX & TX.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&scif3 {
+ pinctrl-0 = <&scif3_pins>, <&scif3_rts_pins>;
+};
+
+&scif3_rs_232_485_mux {
+ /* select rs485 */
+ idle-state = <1>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi
new file mode 100644
index 0000000000000..22f066079e69a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include "rzg2l-hummingboard-iiot-common.dtsi"
+
+&canfd {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins>, <&can1_pins>;
+ status = "okay";
+
+ channel0 {
+ status = "okay";
+ };
+
+ channel1 {
+ status = "okay";
+ };
+};
+
+&phy1 {
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* LED_0 pin */
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+};
+
+&pinctrl {
+ /* CANA */
+ can0_pins: can0 {
+ pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* CAN0_TX */
+ <RZG2L_PORT_PINMUX(11, 0, 2)>; /* CAN0_RX */
+ };
+
+ /* CANB */
+ can1_pins: can1 {
+ pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* CAN1_TX */
+ <RZG2L_PORT_PINMUX(13, 0, 2)>; /* CAN1_RX */
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso b/arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso
new file mode 100644
index 0000000000000..c59c7e7e70bfa
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+* Device Tree Overlay for the RZ/G2L(C) Solidrun SOM eMMC
+*
+* Copyright (C) 2024 SolidRun Ltd.
+*/
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+®_pmic_ldo1 {
+ /*
+ * This ldo can switch mmc host controller io voltage between
+ * 1.8V and 3.3V. The eMMC IO voltage however is supplied from
+ * reg_pmic_buck3 which is fixed at 1.8V.
+ * Lower this ldo maximum voltage to 1.8V to prevent setting 3.3V.
+ */
+ regulator-max-microvolt = <1800000>;
+};
+
+&sdhi0 {
+ /*
+ * Host controller and eMMC have separate io voltage regulators:
+ * reg_pmic_ldo1 (1.8V/3.3V); reg_pmic_buck3 (1.8V only).
+ * Link to the switchable regulator ensuring that it gets configured.
+ */
+ vqmmc-supply = <®_pmic_ldo1>;
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ mmc-hs200-1_8v;
+ mux-states = <&sdhi0_mux 0>;
+ non-removable;
+ no-sdio;
+ pinctrl-0 = <&sdhi0_uhs_pins>, <&sdhi0_rst_pins>;
+ pinctrl-1 = <&sdhi0_uhs_pins>, <&sdhi0_rst_pins>;
+ pinctrl-names = "default", "state_uhs";
+ vmmc-supply = <®_pmic_buck4>;
+ /* emmc io voltage is hard-wired for 1.8V, disable sd modes */
+ no-sd;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi
new file mode 100644
index 0000000000000..1d52530dcf43c
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi
@@ -0,0 +1,420 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L Solidrun SoM
+ *
+ * Copyright 2023 SolidRun Ltd.
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+/ {
+ aliases {
+ ethernet0 = ð0;
+ ethernet1 = ð1;
+ gpio0 = &pinctrl;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c3;
+ mmc0 = &sdhi0;
+ mmc1 = &sdhi1;
+ rtc0 = &pmic;
+ serial0 = &scif0;
+ serial1 = &scif1;
+ serial2 = &scif2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sdhi0_mux: mux-controller-0 {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ #mux-state-cells = <1>;
+ /*
+ * Mux switches SD0_DATA[0-3], SD0_CMD & SD0_CLK between
+ * on-SoM eMMC and board-to-board connector using one gpio:
+ * 1 = connector, 0 = eMMC.
+ */
+ mux-gpios = <&pinctrl RZG2L_GPIO(22, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ clk_pmic_32k: pmic-32k-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ reg_pmic_buck1: regulator-pmic-buck1 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ };
+
+ reg_pmic_buck3: regulator-pmic-buck3 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ };
+
+ reg_pmic_buck4: regulator-pmic-buck4 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck4";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ };
+
+ reg_pmic_ldo1: regulator-pmic-ldo1 {
+ compatible = "regulator-gpio";
+ regulator-name = "pmic-ldo1";
+ gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ states = <3300000 1>, <1800000 0>;
+ };
+
+ reg_pmic_ldo2: regulator-pmic-ldo2 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-ldo2";
+ /*
+ * This ldo can switch mmc host controller io voltage between
+ * 1.8V and 3.3V by assembly option of pull-up / pull-dow.
+ * Default assembly is 3.3V.
+ */
+ regulator-min-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mmp_reserved: linux,multimedia {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x68000000 0x0 0x8000000>;
+ reusable;
+ };
+
+ global_cma: linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x58000000 0x0 0x10000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ sdhi1_pwrseq: sdhi1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pinctrl RZG2L_GPIO(23, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ /* 32.768kHz crystal */
+ x2: x2-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ memory@40000000 {
+ reg = <0x0 0x40000000 0x0 0x20000000>;
+ device_type = "memory";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+ð0 {
+ phy-handle = <&phy0>;
+ pinctrl-0 = <ð0_pins>;
+ pinctrl-names = "default";
+ /*
+ * ravb driver does not configure mac internal delays for RZ/G2L(C),
+ * instead delays are added by the MxL86110 phy driver.
+ */
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ interrupts-extended = <&pinctrl RZG2L_GPIO(27, 0) IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ð1 {
+ phy-handle = <&phy1>;
+ pinctrl-0 = <ð1_pins>;
+ pinctrl-names = "default";
+ /*
+ * ravb driver does not configure mac internal delays for RZ/G2L(C),
+ * instead delays are added by the MxL86110 phy driver.
+ */
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy1: ethernet-phy@4 {
+ reg = <4>;
+ interrupts-extended = <&pinctrl RZG2L_GPIO(42, 4) IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
+
+&gpu {
+ mali-supply = <®_pmic_buck1>;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pmic: pmic@12 {
+ compatible = "renesas,raa215300";
+ reg = <0x12>, <0x6f>;
+ reg-names = "main", "rtc";
+ clocks = <&x2>;
+ clock-names = "xin";
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ostm1 {
+ status = "okay";
+};
+
+&ostm2 {
+ status = "okay";
+};
+
+&phyrst {
+ status = "okay";
+};
+
+&pinctrl {
+ eth0_pins: eth0 {
+ pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
+ <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
+ <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
+ <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
+ <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
+ <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
+ <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
+ <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
+ <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
+ <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
+ <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
+ <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
+ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
+ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
+ <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+ };
+
+ eth1_pins: eth1 {
+ pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
+ <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
+ <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
+ <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
+ <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
+ <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
+ <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
+ <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
+ <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
+ <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
+ <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
+ <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
+ <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
+ <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
+ <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
+ };
+
+ i2c0_pins: i2c0 {
+ input-enable;
+ pins = "RIIC0_SDA", "RIIC0_SCL";
+ };
+
+ i2c1_pins: i2c1 {
+ input-enable;
+ pins = "RIIC1_SDA", "RIIC1_SCL";
+ };
+
+ i2c3_pins: i2c3 {
+ pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* RIIC3_SDA */
+ <RZG2L_PORT_PINMUX(18, 1, 3)>; /* RIIC3_SCL */
+ };
+
+ qspi0_pins: qspi0 {
+ pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3",
+ "QSPI0_SPCLK", "QSPI0_SSL";
+ power-source = <1800>;
+ };
+
+ scif0_pins: scif0 {
+ pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* SCIF0_TXD */
+ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* SCIF0_RXD */
+ };
+
+ scif2_pins: scif2 {
+ pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* SCIF2_TXD */
+ <RZG2L_PORT_PINMUX(48, 1, 1)>, /* SCIF2_RXD */
+ <RZG2L_PORT_PINMUX(48, 3, 1)>, /* SCIF2_CTS# */
+ <RZG2L_PORT_PINMUX(48, 4, 1)>; /* SCIF2_RTS# */
+ };
+
+ sdhi0_pins: sdhi0 {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <3300>;
+ };
+
+ sdhi0_uhs_pins: sdhi0 {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ sdhi0_cd_pins: sdhi0-cd {
+ pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
+ };
+
+ /* SD0_RST is only routed to eMMC which uses fixed 1.8V IO voltage */
+ sdhi0_rst_pins: sdhi0-rst {
+ pins = "SD0_RST#";
+ power-source = <1800>;
+ };
+
+ sdhi1_pins: sdhi1 {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3",
+ "SD1_CLK", "SD1_CMD";
+ power-source = <3300>;
+ };
+
+ spi1_pins: spi1 {
+ pinmux = <RZG2L_PORT_PINMUX(44, 2, 1)>, /* RSPI1_MISO */
+ <RZG2L_PORT_PINMUX(44, 1, 1)>, /* RSPI1_MOSI# */
+ <RZG2L_PORT_PINMUX(44, 0, 1)>;
+ };
+
+ spi1_cs_pins: spi1-cs {
+ pinmux = <RZG2L_PORT_PINMUX(44, 3, 1)>; /* RSPI1_SSL */
+ };
+
+ usb0_vbus_pins: usb0-vbus {
+ pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>; /* USB0_VBUSEN */
+ };
+
+ usb1_vbus_pins: usb1-vbus {
+ pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>; /* USB1_VBUSEN */
+ };
+};
+
+&sbc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "winbond,w25q80bl", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* WiFi */
+&sdhi1 {
+ /* Murata 1MW max rate is 50MHz */
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ mmc-pwrseq = <&sdhi1_pwrseq>;
+ non-removable;
+ no-1-8-v;
+ no-sd;
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <®_pmic_buck4>;
+ /*
+ * Host controller IO voltage is provided from reg_pmic_ldo2,
+ * WiFi module IO voltage from reg_pmic_buck4.
+ * Neither is configurable at run-time so either can be set here.
+ */
+ vqmmc-supply = <®_pmic_ldo2>;
+ status = "okay";
+};
+
+&usb2_phy0 {
+ vbus-supply = <&usb0_vbus_otg>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ status = "okay";
+};
+
+&wdt0 {
+ status = "okay";
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 3/4] arm64: dts: renesas: add support for solidrun rzv2l som and hb-iiot evb
2026-05-11 10:37 [PATCH v2 0/4] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
2026-05-11 10:37 ` [PATCH v2 1/4] dt-bindings: soc: " Josua Mayer
2026-05-11 10:37 ` [PATCH v2 2/4] arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb Josua Mayer
@ 2026-05-11 10:37 ` Josua Mayer
2026-05-12 2:43 ` sashiko-bot
2026-05-11 10:37 ` [PATCH v2 4/4] arm64: dts: renesas: add support for solidrun rzg2lc " Josua Mayer
3 siblings, 1 reply; 12+ messages in thread
From: Josua Mayer @ 2026-05-11 10:37 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, Josua Mayer
Add support for the SolidRun RZ/V2L [1] SoM on Hummingboard IIoT [2].
The SoM features:
- 2x 1Gbps Ethernet with PHY
- eMMC
- 1/2GB DDR
- WiFi + Bluetooth
- SDHI Mux switching between eMMC and Carrier Board
The HummingBoard IIoT features:
- 3x USB-2.0 Type A connector
- 2x 1Gbps RJ45 Ethernet
- USB Type-C Console Port
- microSD connector
- RTC with backup battery
- RGB Status LED
- 1x M.2 B-Key connector with USB-2.0 + SIM card holder
- 1x DSI Display Connector
- GPIO header
- 2x RS232/RS485 ports (configurable)
- 2x CAN
The RZ-V2L SoM shares PCB with RZ/G2L, differing only in the SoC itself.
V2L is adding a powerful DRP-AI NPU which G2L lacks.
Due to the similarities most code is shared, including DT overlays for
eMMC, microSD, and RS485.
[1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-v2l-som/
[2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/renesas/Makefile | 9 +++++++++
.../boot/dts/renesas/r9a07g054l2-hummingboard-iiot.dts | 16 ++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 37cfefe66a308..cdf59f3240e27 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -188,6 +188,15 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo
r9a07g044l2-smarc-cru-csi-ov5645-dtbs := r9a07g044l2-smarc.dtb r9a07g044l2-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtb
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot.dtb
+r9a07g054l2-hummingboard-emmc-dtbs += r9a07g054l2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-emmc.dtb
+r9a07g054l2-hummingboard-microsd-dtbs += r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-microsd.dtb
+r9a07g054l2-hummingboard-rs485-a-dtbs += r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-rs485-a.dtb
+r9a07g054l2-hummingboard-rs485-b-dtbs += r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-rs485-b.dtb
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtbo
r9a07g054l2-smarc-cru-csi-ov5645-dtbs := r9a07g054l2-smarc.dtb r9a07g054l2-smarc-cru-csi-ov5645.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-hummingboard-iiot.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-hummingboard-iiot.dts
new file mode 100644
index 0000000000000..d77a6ff163bea
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-hummingboard-iiot.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include "r9a07g054l2.dtsi"
+#include "rzg2l-sr-som.dtsi"
+#include "rzg2l-hummingboard-iiot.dtsi"
+
+/ {
+ compatible = "solidrun,rzv2l-hummingboard-iiot", "solidrun,rzv2l-sr-som",
+ "renesas,r9a07g054l2", "renesas,r9a07g054";
+ model = "SolidRun RZ/V2L HummingBoard IIoT";
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 4/4] arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb
2026-05-11 10:37 [PATCH v2 0/4] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
` (2 preceding siblings ...)
2026-05-11 10:37 ` [PATCH v2 3/4] arm64: dts: renesas: add support for solidrun rzv2l " Josua Mayer
@ 2026-05-11 10:37 ` Josua Mayer
2026-05-12 3:18 ` sashiko-bot
3 siblings, 1 reply; 12+ messages in thread
From: Josua Mayer @ 2026-05-11 10:37 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Jon Nettleton, Mikhail Anikin, Yazan Shhady, linux-renesas-soc,
devicetree, linux-kernel, Josua Mayer
Add support for the SolidRun RZ/G2LC SoM [1] on Hummingboard IIoT [2].
The SoM features:
- 1Gbps Ethernet with PHY
- eMMC
- 1/2GB DDR
- WiFi + Bluetooth
- SDHI Mux switching between eMMC and Carrier Board
The HummingBoard IIoT features:
- 3x USB-2.0 Type A connector
- 1x 1Gbps RJ45 Ethernet
- USB Type-C Console Port
- microSD connector
- RTC with backup battery
- RGB Status LED
- 1x M.2 B-Key connector with USB-2.0 + SIM card holder
- 1x DSI Display Connector
- GPIO header
- 2x RS232/RS485 ports (configurable)
The RZ/G2LC SoM was designed to be pin compatible to G2L SoM, with
slightly reduced feature set.
Descriptions for eMMC, microSD, and RS485 are shared with G2L.
[1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2lc-som/
[2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/renesas/Makefile | 11 +
.../dts/renesas/r9a07g044c2-hummingboard-iiot.dts | 20 ++
arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi | 373 +++++++++++++++++++++
3 files changed, 404 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index cdf59f3240e27..adba304a9d767 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -164,6 +164,17 @@ dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtb
r9a07g043u11-smarc-pmod-dtbs := r9a07g043u11-smarc.dtb r9a07g043-smarc-pmod.dtbo
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-pmod.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot.dtb
+r9a07g044c2-hummingboard-iiot-emmc-dtbs += r9a07g044c2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-emmc.dtb
+r9a07g044c2-hummingboard-iiot-microsd-dtbs += r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-microsd.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-a.dtbo
+r9a07g044c2-hummingboard-iiot-rs485-a-dtbs += r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-rs485-a.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-b.dtbo
+r9a07g044c2-hummingboard-iiot-rs485-b-dtbs += r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-rs485-b.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo
r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-hummingboard-iiot.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-hummingboard-iiot.dts
new file mode 100644
index 0000000000000..06d9d031cbe91
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-hummingboard-iiot.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include "r9a07g044c2.dtsi"
+#include "rzg2lc-sr-som.dtsi"
+#include "rzg2l-hummingboard-iiot-common.dtsi"
+
+/ {
+ compatible = "solidrun,rzg2lc-hummingboard-iiot", "solidrun,rzg2lc-sr-som",
+ "renesas,r9a07g044c2", "renesas,r9a07g044";
+ model = "SolidRun RZ/G2LC HummingBoard IIoT";
+};
+
+&vmmc {
+ gpio = <&pinctrl RZG2L_GPIO(18, 1) GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
new file mode 100644
index 0000000000000..e244836f5ec39
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC Solidrun SOM
+ *
+ * Copyright 2023 SolidRun Ltd.
+ * Copyright 2025 Josua Mayer <josua@solid-run.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+/ {
+ aliases {
+ ethernet0 = ð0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ mmc0 = &sdhi0;
+ mmc1 = &sdhi1;
+ rtc0 = &pmic;
+ serial0 = &scif0;
+ serial1 = &scif1;
+ serial2 = &scif2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sdhi0_mux: mux-controller-0 {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ #mux-state-cells = <1>;
+ /*
+ * Mux switches SD0_DATA[0-3], SD0_CMD & SD0_CLK between
+ * on-SoM eMMC and board-to-board connector using one gpio:
+ * 0 = connector, 1 = eMMC.
+ */
+ mux-gpios = <&pinctrl RZG2L_GPIO(22, 1) GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_pmic_buck1: regulator-pmic-buck1 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ };
+
+ reg_pmic_buck3: regulator-pmic-buck3 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ };
+
+ reg_pmic_buck4: regulator-pmic-buck4 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-buck4";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ };
+
+ reg_pmic_ldo1: regulator-pmic-ldo1 {
+ compatible = "regulator-gpio";
+ regulator-name = "pmic-ldo1";
+ gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ states = <3300000 1>, <1800000 0>;
+ };
+
+ reg_pmic_ldo2: regulator-pmic-ldo2 {
+ compatible = "regulator-fixed";
+ regulator-name = "pmic-ldo2";
+ /*
+ * This ldo can switch mmc host controller io voltage between
+ * 1.8V and 3.3V by assembly option of pull-up / pull-dow.
+ * Default assembly is 3.3V.
+ */
+ regulator-min-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mmp_reserved: linux,multimedia {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x68000000 0x0 0x8000000>;
+ reusable;
+ };
+
+ global_cma: linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x58000000 0x0 0x10000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ sdhi1_pwrseq: sdhi1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pinctrl RZG2L_GPIO(23, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ /* 32.768kHz crystal */
+ x2: x2-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ memory@40000000 {
+ reg = <0x0 0x40000000 0x0 0x20000000>;
+ device_type = "memory";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+ð0 {
+ phy-handle = <&phy0>;
+ pinctrl-0 = <ð0_pins>;
+ pinctrl-names = "default";
+ /*
+ * ravb driver does not configure mac internal delays for RZ/G2L(C),
+ * instead delays are added by the ADIN1200 phy driver.
+ */
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ interrupts-extended = <&pinctrl RZG2L_GPIO(27, 0) IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
+
+&gpu {
+ mali-supply = <®_pmic_buck1>;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pmic: pmic@12 {
+ compatible = "renesas,raa215300";
+ reg = <0x12>, <0x6f>;
+ reg-names = "main", "rtc";
+ clocks = <&x2>;
+ clock-names = "xin";
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ostm1 {
+ status = "okay";
+};
+
+&ostm2 {
+ status = "okay";
+};
+
+&phyrst {
+ status = "okay";
+};
+
+&pinctrl {
+ eth0_pins: eth0 {
+ pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
+ <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
+ <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
+ <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
+ <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
+ <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
+ <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
+ <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
+ <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
+ <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
+ <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
+ <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
+ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
+ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
+ <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+ };
+
+ i2c0_pins: i2c0 {
+ input-enable;
+ pins = "RIIC0_SDA", "RIIC0_SCL";
+ };
+
+ i2c1_pins: i2c1 {
+ input-enable;
+ pins = "RIIC1_SDA", "RIIC1_SCL";
+ };
+
+ i2c2_pins: i2c2 {
+ pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* RIIC2_SDA */
+ <RZG2L_PORT_PINMUX(42, 4, 1)>; /* RIIC2_SCL */
+ };
+
+ qspi0_pins: qspi0 {
+ pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3",
+ "QSPI0_SPCLK", "QSPI0_SSL";
+ power-source = <1800>;
+ };
+
+ scif0_pins: scif0 {
+ pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* SCIF0_TXD */
+ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* SCIF0_RXD */
+ };
+
+ scif2_pins: scif2 {
+ pinmux = <RZG2L_PORT_PINMUX(42, 0, 4)>, /* SCIF2_TXD */
+ <RZG2L_PORT_PINMUX(42, 1, 4)>, /* SCIF2_RXD */
+ <RZG2L_PORT_PINMUX(5, 1, 2)>, /* SCIF2_CTS# */
+ <RZG2L_PORT_PINMUX(5, 2, 2)>; /* SCIF2_RTS# */
+ };
+
+ sdhi0_pins: sdhi0 {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <3300>;
+ };
+
+ sdhi0_uhs_pins: sdhi0 {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
+ "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ sdhi0_cd_pins: sdhi0-cd {
+ pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
+ };
+
+ /* SD0_RST is only routed to eMMC which uses fixed 1.8V IO voltage */
+ sdhi0_rst_pins: sdhi0-rst {
+ pins = "SD0_RST#";
+ power-source = <1800>;
+ };
+
+ sdhi1_pins: sdhi1 {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3",
+ "SD1_CLK", "SD1_CMD";
+ power-source = <3300>;
+ };
+
+ spi1_pins: spi1 {
+ pinmux = <RZG2L_PORT_PINMUX(44, 2, 1)>, /* RSPI1_MISO */
+ <RZG2L_PORT_PINMUX(44, 1, 1)>, /* RSPI1_MOSI# */
+ <RZG2L_PORT_PINMUX(44, 0, 1)>; /* RSPI1_CK# */
+ };
+
+ spi1_cs_pins: spi1-cs {
+ pinmux = <RZG2L_PORT_PINMUX(44, 3, 1)>; /* RSPI1_SSL */
+ };
+
+ usb0_vbus_pins: usb0-vbus {
+ pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>; /* USB0_VBUSEN */
+ };
+};
+
+&sbc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "winbond,w25q80bl", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* WiFi */
+&sdhi1 {
+ /* Murata 1YN max rate is 50MHz */
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ mmc-pwrseq = <&sdhi1_pwrseq>;
+ non-removable;
+ no-1-8-v;
+ no-sd;
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <®_pmic_buck4>;
+ /*
+ * Host controller IO voltage is provided from reg_pmic_ldo2,
+ * WiFi module IO voltage from reg_pmic_buck4.
+ * Neither is configurable at run-time so either can be set here.
+ */
+ vqmmc-supply = <®_pmic_ldo2>;
+ status = "okay";
+};
+
+&usb2_phy0 {
+ vbus-supply = <&usb0_vbus_otg>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ status = "okay";
+};
+
+&wdt0 {
+ status = "okay";
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: soc: renesas: Add various SolidRun RZ/G2 based boards
2026-05-11 10:37 ` [PATCH v2 1/4] dt-bindings: soc: " Josua Mayer
@ 2026-05-11 16:28 ` Conor Dooley
0 siblings, 0 replies; 12+ messages in thread
From: Conor Dooley @ 2026-05-11 16:28 UTC (permalink / raw)
To: Josua Mayer
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jon Nettleton, Mikhail Anikin, Yazan Shhady,
linux-renesas-soc, devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1437 bytes --]
On Mon, May 11, 2026 at 12:37:47PM +0200, Josua Mayer wrote:
> Add bindings for various SolidRun boards and System on Module built
> around Renesas RZ/G2 family of SoCs:
>
> - RZ/G2L SoM [1]
> - RZ/V2L SoM [2]
> (shares PCB with G2L and has very similar programming model)
> - RZ/G2LC SoM [3]
> - RZ/G2UL SoM [4]
> (shares PCB with G2LC but programming model differs largely)
> - HummingBoard IIoT [5] (RZ/G2L, RZ/V2L, RZ/G2LC)
> - HummingBoard Pro [6] (RZ/G2L, RZ/V2L)
> - HummingBoard Base (Ripple) [7] (RZ/G2L, RZ/V2L, RZ/G2LC, RZ/G2UL)
>
> [1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2l-som/
> [2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-v2l-som/
> [3] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2lc-som/
> [4] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2ul-som/
> [5] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
> [6] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-sbc/
> [7] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2lc-base/
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb
2026-05-11 10:37 ` [PATCH v2 2/4] arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb Josua Mayer
@ 2026-05-12 2:28 ` sashiko-bot
2026-05-12 12:50 ` Josua Mayer
0 siblings, 1 reply; 12+ messages in thread
From: sashiko-bot @ 2026-05-12 2:28 UTC (permalink / raw)
To: Josua Mayer; +Cc: devicetree, wsa+renesas, krzk+dt, conor+dt, robh
Thank you for your contribution! Sashiko AI review found 9 potential issue(s) to consider:
- [High] USB VBUS pinmux nodes are defined but never referenced, breaking USB host power.
- [High] Edge-triggered interrupt for TCAL6416 GPIO expander leads to lost interrupts.
- [High] Inverse polarity on `rfkill-m2-b-gnss` disable GPIO will disable the GPS when it should be enabled.
- [High] Omitted `GPIO_OPEN_DRAIN` flag on I2C mux reset line forces dangerous push-pull drive.
- [Medium] Missing SDIO interrupt capabilities on WiFi MMC interface degrades performance.
- [Medium] Pinctrl strict locking prevents documented manual RS485 toggling.
- [Medium] Contradictory regulator polarity flags in `vmmc` create ambiguous regulator state.
- [Medium] Unimplemented internal pull-ups on GPIO hogs lead to floating open-drain lines.
- [Low] Improper append operator `+=` used for multi-blob DTB definitions in Makefile.
--
commit 264a692a0b295dedac1ff5214c5f24eb1c644647
Author: Josua Mayer <josua@solid-run.com>
arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb
This commit adds support for the SolidRun RZ/G2L SoM on Hummingboard IIoT,
including definitions for Ethernet, eMMC, DDR, and WiFi/Bluetooth.
Descriptions for eMMC, microSD, and RS485 are provided as overlays due to
their dependency on configurable mux states.
[1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2l-som/
[2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
> diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
> index ca45d2857ea7f..37cfefe66a308 100644
> --- a/arch/arm64/boot/dts/renesas/Makefile
> +++ b/arch/arm64/boot/dts/renesas/Makefile
> @@ -169,6 +169,19 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo
> r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo
> dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtb
>
> +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot.dtb
> +dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-sr-som-emmc.dtbo
> +r9a07g044l2-hummingboard-iiot-emmc-dtbs += r9a07g044l2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
Is it safer to use the exact assignment operator := instead of the append
operator += for composite device tree blobs? Standard Kbuild convention
dictates using := for <target>-dtbs to ensure immediate evaluation and avoid
any risk of build pollution from inherited environment variables.
[ ... ]
> diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi
> new file mode 100644
> index 0000000000000..ff2c42bcffe2f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi
[ ... ]
> + vmmc: regulator-mmc {
> + compatible = "regulator-fixed";
> + regulator-name = "vmmc";
> + regulator-max-microvolt = <3300000>;
> + regulator-min-microvolt = <3300000>;
> + startup-delay-us = <250>;
> + vin-supply = <&v_3_3>;
> + gpio = <&pinctrl RZG2L_GPIO(4, 1) GPIO_ACTIVE_LOW>;
> + enable-active-high;
> + };
Mixing enable-active-high and GPIO_ACTIVE_LOW creates an ambiguous
configuration. The fixed regulator driver interprets enable-active-high as a
physical active-high requirement, but modern gpiolib automatically handles
the GPIO_ACTIVE_LOW inversion at the descriptor level.
Could this conflicting double-inversion cause the regulator to be driven to
the wrong physical state and fail to power the eMMC module?
[ ... ]
> + rfkill-m2-b-gnss {
> + compatible = "rfkill-gpio";
> + /* rfkill-gpio inverts internally */
> + shutdown-gpios = <&tca6416_u20 10 GPIO_ACTIVE_HIGH>;
> + label = "m2-b gnss";
> + radio-type = "gps";
> + };
The rfkill-gpio driver asserts shutdown_gpios (drives a logical 1) when the
radio is turned on. With GPIO_ACTIVE_HIGH, a logical 1 maps to a physical
HIGH signal.
Since the pin is an active-low enable (GPS_EN#), driving it physically HIGH
will disable the GPS. Does this cause the kernel to disable the GPS radio
when it attempts to enable it? Should the polarity be GPIO_ACTIVE_LOW?
[ ... ]
> + tca6416_u21: gpio@21 {
> + compatible = "ti,tcal6416";
> + reg = <0x21>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + #gpio-cells = <2>;
> + gpio-controller;
> + gpio-line-names = "TCA_SPI_TPM/EXT", "TCA_TPM_RST#",
> + "TCA_I2C_RST", "TCA_RS232_SHTD#",
> + "TCA_LCD_I2C_RST", "TCA_DIG_OUT1",
> + "TCA_bDIG_IN1", "TCA_SENS_INT",
> + "TCA_ALERT#", "TCA_TPM_PIRQ#",
> + "TCA_RTC_INT", "TCA_M.2M_WAKW_ON_LAN",
> + "TCA_M.2M_CLKREQ#", "TCA_LVDS_INT#",
> + "", "TCA_POE_AT";
> + interrupts-extended = <&pinctrl RZG2L_GPIO(4, 0) IRQ_TYPE_EDGE_FALLING>;
The hardware INT pin for the TCAL6416 GPIO expander is an active-low
level-sensitive output that remains low as long as unread state changes
exist.
If this is configured as IRQ_TYPE_EDGE_FALLING, could the kernel miss
subsequent interrupts if a second GPIO state change occurs before the first
is cleared, since the line will remain low without generating a new falling
edge? Should this be IRQ_TYPE_LEVEL_LOW instead?
> +
> + lcd-i2c-reset-hog {
> + gpios = <4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
The ti,tcal6416 chip is driven by gpio-pca953x, which does not implement the
.set_config callback for this specific IC because it lacks the PCA_PCAL
hardware flag.
Will gpiolib silently ignore the GPIO_PULL_UP flag? For open-drain lines
like the lcd reset and the TPM interrupt below, could this leave the lines
floating and lead to spurious interrupts or unstable hardware states if
there are no external board-level pull-ups?
[ ... ]
> + i2c-mux@70 {
> + compatible = "nxp,pca9546";
> + reg = <0x70>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + /*
> + * This reset is open drain,
> + * but reset core does not support GPIO_OPEN_DRAIN flag.
> + */
> + reset-gpios = <&tca6416_u21 2 GPIO_ACTIVE_LOW>;
The comment mentions that the reset core does not support the
GPIO_OPEN_DRAIN flag, but the i2c-mux-pca954x driver requests the GPIO using
devm_gpiod_get_optional(), which fully supports device tree flags.
By omitting the flag, does the GPIO controller get forced to drive the pin
in push-pull mode? Could actively driving a hard-wired open-drain line high
cause short circuits or component damage?
[ ... ]
> diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso
> new file mode 100644
> index 0000000000000..886f4d4ecd67f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
> + *
> + * Overlay for enabling HummingBoard IIoT on-board RS485 Port A on connector J5004.
> + *
> + * Because Renesas uart driver does not support rs485,
> + * users must manually toggle P41_1 between RX & TX.
The overlay below adds <&scif1_rts_pins> to the pinctrl-0 property of the
UART controllers. Since the Renesas RZ/G2L pinctrl driver operates in strict
mode, it will exclusively claim these RTS pins.
Will this prevent userspace from subsequently requesting these pins as GPIOs
for the documented manual toggling, causing requests to be rejected with
-EBUSY?
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +&scif1 {
> + pinctrl-0 = <&scif1_pins>, <&scif1_rts_pins>;
> +};
[ ... ]
> diff --git a/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi
> new file mode 100644
> index 0000000000000..1d52530dcf43c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi
[ ... ]
> +&sdhi1 {
> + /* Murata 1MW max rate is 50MHz */
> + max-frequency = <50000000>;
> + bus-width = <4>;
> + mmc-pwrseq = <&sdhi1_pwrseq>;
> + non-removable;
> + no-1-8-v;
> + no-sd;
> + pinctrl-0 = <&sdhi1_pins>;
> + pinctrl-names = "default";
> + vmmc-supply = <®_pmic_buck4>;
> + /*
> + * Host controller IO voltage is provided from reg_pmic_ldo2,
> + * WiFi module IO voltage from reg_pmic_buck4.
> + * Neither is configurable at run-time so either can be set here.
> + */
> + vqmmc-supply = <®_pmic_ldo2>;
> + status = "okay";
> +};
The sdhi1 node is designated for an on-board WiFi module but omits the
cap-sdio-irq property and lacks a child node defining an out-of-band
interrupt.
Will the MMC core fall back to SDIO polling without this capability
declared, and could this degrade I/O performance and inflate CPU utilization?
> +
> +&usb2_phy0 {
> + vbus-supply = <&usb0_vbus_otg>;
> + status = "okay";
> +};
> +
> +&usb2_phy1 {
> + status = "okay";
> +};
The usb0_vbus_pins and usb1_vbus_pins nodes are defined in the pinctrl
section earlier in this file to configure the USB VBUS enable pins, but
neither &usb2_phy0 nor &usb2_phy1 appears to reference them via a pinctrl-0
property.
Without being multiplexed, will the USB host controllers be able to drive
VBUS power to connected devices?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260511-rzg2-sr-boards-v2-0-82aebbd27891@solid-run.com?part=2
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: renesas: add support for solidrun rzv2l som and hb-iiot evb
2026-05-11 10:37 ` [PATCH v2 3/4] arm64: dts: renesas: add support for solidrun rzv2l " Josua Mayer
@ 2026-05-12 2:43 ` sashiko-bot
2026-05-12 10:40 ` Josua Mayer
0 siblings, 1 reply; 12+ messages in thread
From: sashiko-bot @ 2026-05-12 2:43 UTC (permalink / raw)
To: Josua Mayer; +Cc: krzk+dt, devicetree, robh, conor+dt, wsa+renesas
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] The composite DTB targets for the RZ/V2L board are missing the '-iiot' identifier, leading to inconsistent naming.
- [Medium] The shared device tree overlays are not added to the install targets for the R9A07G054 architecture.
- [Low] The `-dtbs` composite variables are populated using `+=` instead of `:=`.
--
commit 1346fdf98939d24bedd9085cb7ddffee29247fcf
Author: Josua Mayer <josua@solid-run.com>
arm64: dts: renesas: add support for solidrun rzv2l som and hb-iiot evb
This commit adds device tree support for the SolidRun RZ/V2L SoM on the
HummingBoard IIoT platform. It utilizes shared code and device tree overlays
from the existing RZ/G2L series.
> diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
> index 37cfefe66a308..cdf59f3240e27 100644
> --- a/arch/arm64/boot/dts/renesas/Makefile
> +++ b/arch/arm64/boot/dts/renesas/Makefile
> @@ -188,6 +188,15 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo
> r9a07g044l2-smarc-cru-csi-ov5645-dtbs := r9a07g044l2-smarc.dtb r9a07g044l2-smarc-cru-csi-ov5645.dtbo
> dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtb
>
> +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot.dtb
Should the shared device tree overlays be explicitly added to the install
targets for CONFIG_ARCH_R9A07G054?
Currently, overlays like rzg2l-sr-som-emmc.dtbo and
rzg2l-hummingboard-iiot-microsd.dtbo are built as intermediate dependencies,
but Kbuild's make dtbs_install only installs artifacts present in dtb-y.
Without being added to dtb-$(CONFIG_ARCH_R9A07G054), will these standalone
.dtbo files be missing from the installation directory?
> +r9a07g054l2-hummingboard-emmc-dtbs += r9a07g054l2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
> +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-emmc.dtb
Are these composite DTB targets missing the -iiot identifier?
The base board is named r9a07g054l2-hummingboard-iiot.dts, but the targets
omit -iiot (for example, r9a07g054l2-hummingboard-emmc.dtb). The equivalent
RZ/G2L targets correctly include it, such as
r9a07g044l2-hummingboard-iiot-emmc.dtb.
Could this naming discrepancy cause issues for deployment scripts
expecting the -iiot substring to locate the RZ/V2L DTBs?
Also, this isn't a bug, but is it intentional to use += instead of := for
these composite variables?
In Kbuild, := is generally the standard convention for defining multi-DTB
targets, as seen in the surrounding Makefile entries.
> +r9a07g054l2-hummingboard-microsd-dtbs += r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
> +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-microsd.dtb
> +r9a07g054l2-hummingboard-rs485-a-dtbs += r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
> +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-rs485-a.dtb
> +r9a07g054l2-hummingboard-rs485-b-dtbs += r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
> +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-rs485-b.dtb
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260511-rzg2-sr-boards-v2-0-82aebbd27891@solid-run.com?part=3
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 4/4] arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb
2026-05-11 10:37 ` [PATCH v2 4/4] arm64: dts: renesas: add support for solidrun rzg2lc " Josua Mayer
@ 2026-05-12 3:18 ` sashiko-bot
2026-05-12 10:56 ` Josua Mayer
0 siblings, 1 reply; 12+ messages in thread
From: sashiko-bot @ 2026-05-12 3:18 UTC (permalink / raw)
To: Josua Mayer; +Cc: conor+dt, krzk+dt, wsa+renesas, robh, devicetree
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Low] Missing unit address for reserved-memory node with a `reg` property.
- [Low] Inconsistent use of `+=` instead of `:=` for Kbuild composite DTB definitions.
- [Low] Redundant addition of shared `.dtbo` overlay targets to the Makefile variable.
--
commit 8d9d2cbc7a77754ee19950ca31a17d0916b4b627
Author: Josua Mayer <josua@solid-run.com>
arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb
Add support for the SolidRun RZ/G2LC SoM on Hummingboard IIoT, which
features various peripherals including Ethernet, eMMC, and WiFi.
The RZ/G2LC SoM is pin-compatible with the G2L SoM with a slightly
reduced feature set.
Link: https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2lc-som/
Link: https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
> diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
> --- a/arch/arm64/boot/dts/renesas/Makefile
> +++ b/arch/arm64/boot/dts/renesas/Makefile
> @@ -164,6 +164,17 @@ dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtb
> r9a07g043u11-smarc-pmod-dtbs := r9a07g043u11-smarc.dtb r9a07g043-smarc-pmod.dtbo
> dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-pmod.dtb
>
> +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot.dtb
> +r9a07g044c2-hummingboard-iiot-emmc-dtbs += r9a07g044c2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
This isn't a bug, but should this use := instead of += for consistency with
standard Kbuild practice and other composite DTB definitions in this Makefile?
> +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-emmc.dtb
> +r9a07g044c2-hummingboard-iiot-microsd-dtbs += r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
> +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-microsd.dtb
> +dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-a.dtbo
This isn't a bug, but since rzg2l-hummingboard-iiot-rs485-a.dtbo and
rzg2l-hummingboard-iiot-rs485-b.dtbo are already appended to
dtb-$(CONFIG_ARCH_R9A07G044) for the shared r9a07g044l2 SoC variant, is it
redundant to include them here?
> +r9a07g044c2-hummingboard-iiot-rs485-a-dtbs += r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
> +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-rs485-a.dtb
> +dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-b.dtbo
[ ... ]
> diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
> @@ -0,0 +1,373 @@
[ ... ]
> + reserved-memory {
> + ranges;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mmp_reserved: linux,multimedia {
> + compatible = "shared-dma-pool";
> + reg = <0x0 0x68000000 0x0 0x8000000>;
> + reusable;
> + };
Does this node need a unit address matching the first address of the reg block
(e.g., linux,multimedia@68000000) to prevent a unit_address_vs_reg DTC
compiler warning?
> +
> + global_cma: linux,cma@58000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x0 0x58000000 0x0 0x10000000>;
> + reusable;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260511-rzg2-sr-boards-v2-0-82aebbd27891@solid-run.com?part=4
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/4] arm64: dts: renesas: add support for solidrun rzv2l som and hb-iiot evb
2026-05-12 2:43 ` sashiko-bot
@ 2026-05-12 10:40 ` Josua Mayer
0 siblings, 0 replies; 12+ messages in thread
From: Josua Mayer @ 2026-05-12 10:40 UTC (permalink / raw)
To: sashiko@lists.linux.dev
Cc: krzk+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org,
conor+dt@kernel.org, wsa+renesas@sang-engineering.com
Am 12.05.26 um 04:43 schrieb sashiko-bot@kernel.org:
> Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
> - [Medium] The composite DTB targets for the RZ/V2L board are missing the '-iiot' identifier, leading to inconsistent naming.
> - [Medium] The shared device tree overlays are not added to the install targets for the R9A07G054 architecture.
> - [Low] The `-dtbs` composite variables are populated using `+=` instead of `:=`.
> --
>
> commit 1346fdf98939d24bedd9085cb7ddffee29247fcf
> Author: Josua Mayer <josua@solid-run.com>
>
> arm64: dts: renesas: add support for solidrun rzv2l som and hb-iiot evb
>
> This commit adds device tree support for the SolidRun RZ/V2L SoM on the
> HummingBoard IIoT platform. It utilizes shared code and device tree overlays
> from the existing RZ/G2L series.
>
>> diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
>> index 37cfefe66a308..cdf59f3240e27 100644
>> --- a/arch/arm64/boot/dts/renesas/Makefile
>> +++ b/arch/arm64/boot/dts/renesas/Makefile
>> @@ -188,6 +188,15 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo
>> r9a07g044l2-smarc-cru-csi-ov5645-dtbs := r9a07g044l2-smarc.dtb r9a07g044l2-smarc-cru-csi-ov5645.dtbo
>> dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtb
>>
>> +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot.dtb
> Should the shared device tree overlays be explicitly added to the install
> targets for CONFIG_ARCH_R9A07G054?
They should, though building for one platform without the other is unlikely.
Queued for v3.
>
> Currently, overlays like rzg2l-sr-som-emmc.dtbo and
> rzg2l-hummingboard-iiot-microsd.dtbo are built as intermediate dependencies,
> but Kbuild's make dtbs_install only installs artifacts present in dtb-y.
> Without being added to dtb-$(CONFIG_ARCH_R9A07G054), will these standalone
> .dtbo files be missing from the installation directory?
>
>> +r9a07g054l2-hummingboard-emmc-dtbs += r9a07g054l2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
>> +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-emmc.dtb
> Are these composite DTB targets missing the -iiot identifier?
Correct.
Queued for v3
>
> The base board is named r9a07g054l2-hummingboard-iiot.dts, but the targets
> omit -iiot (for example, r9a07g054l2-hummingboard-emmc.dtb). The equivalent
> RZ/G2L targets correctly include it, such as
> r9a07g044l2-hummingboard-iiot-emmc.dtb.
>
> Could this naming discrepancy cause issues for deployment scripts
> expecting the -iiot substring to locate the RZ/V2L DTBs?
>
> Also, this isn't a bug, but is it intentional to use += instead of := for
> these composite variables?
Unintentional copy from other examples.
>
> In Kbuild, := is generally the standard convention for defining multi-DTB
> targets, as seen in the surrounding Makefile entries.
Queued for v3.
>
>> +r9a07g054l2-hummingboard-microsd-dtbs += r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
>> +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-microsd.dtb
>> +r9a07g054l2-hummingboard-rs485-a-dtbs += r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
>> +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-rs485-a.dtb
>> +r9a07g054l2-hummingboard-rs485-b-dtbs += r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
>> +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-rs485-b.dtb
> [ ... ]
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 4/4] arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb
2026-05-12 3:18 ` sashiko-bot
@ 2026-05-12 10:56 ` Josua Mayer
0 siblings, 0 replies; 12+ messages in thread
From: Josua Mayer @ 2026-05-12 10:56 UTC (permalink / raw)
To: sashiko@lists.linux.dev
Cc: conor+dt@kernel.org, krzk+dt@kernel.org,
wsa+renesas@sang-engineering.com, robh@kernel.org,
devicetree@vger.kernel.org
Am 12.05.26 um 05:18 schrieb sashiko-bot@kernel.org:
> Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
> - [Low] Missing unit address for reserved-memory node with a `reg` property.
> - [Low] Inconsistent use of `+=` instead of `:=` for Kbuild composite DTB definitions.
> - [Low] Redundant addition of shared `.dtbo` overlay targets to the Makefile variable.
> --
>
> commit 8d9d2cbc7a77754ee19950ca31a17d0916b4b627
> Author: Josua Mayer <josua@solid-run.com>
> arm64: dts: renesas: add support for solidrun rzg2lc som and hb-iiot evb
>
> Add support for the SolidRun RZ/G2LC SoM on Hummingboard IIoT, which
> features various peripherals including Ethernet, eMMC, and WiFi.
> The RZ/G2LC SoM is pin-compatible with the G2L SoM with a slightly
> reduced feature set.
>
> Link: https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2lc-som/
> Link: https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
>
>> diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
>> --- a/arch/arm64/boot/dts/renesas/Makefile
>> +++ b/arch/arm64/boot/dts/renesas/Makefile
>> @@ -164,6 +164,17 @@ dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtb
>> r9a07g043u11-smarc-pmod-dtbs := r9a07g043u11-smarc.dtb r9a07g043-smarc-pmod.dtbo
>> dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-pmod.dtb
>>
>> +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot.dtb
>> +r9a07g044c2-hummingboard-iiot-emmc-dtbs += r9a07g044c2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
> This isn't a bug, but should this use := instead of += for consistency with
> standard Kbuild practice and other composite DTB definitions in this Makefile?
Queued vor v3.
>
>> +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-emmc.dtb
>> +r9a07g044c2-hummingboard-iiot-microsd-dtbs += r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
>> +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-microsd.dtb
>> +dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-a.dtbo
> This isn't a bug, but since rzg2l-hummingboard-iiot-rs485-a.dtbo and
> rzg2l-hummingboard-iiot-rs485-b.dtbo are already appended to
> dtb-$(CONFIG_ARCH_R9A07G044) for the shared r9a07g044l2 SoC variant, is it
> redundant to include them here?
Yes, redundant as both G2L and G2LC are CONFIG_ARCH_R9A07G044.
Queued vor v3.
>
>> +r9a07g044c2-hummingboard-iiot-rs485-a-dtbs += r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
>> +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-rs485-a.dtb
>> +dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-b.dtbo
> [ ... ]
>
>> diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
>> @@ -0,0 +1,373 @@
> [ ... ]
>
>> + reserved-memory {
>> + ranges;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + mmp_reserved: linux,multimedia {
>> + compatible = "shared-dma-pool";
>> + reg = <0x0 0x68000000 0x0 0x8000000>;
>> + reusable;
>> + };
> Does this node need a unit address matching the first address of the reg block
> (e.g., linux,multimedia@68000000) to prevent a unit_address_vs_reg DTC
> compiler warning?
Probably, but the usage of pattern "linux,.+@" (i.e. with address suffix) is extremely rare
in existing device-tree, on v7.1-rc1:
❯ grep -r -E "linux,.+@" arch/arm64/boot/dts/
❯ grep -r -E "linux,.+@" arch/arm/boot/dts/
arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts: linux,cma@80000000 {
arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts: linux,cma@30000000 {
arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi: linux,cma@80000000 {
arch/arm/boot/dts/nvidia/tegra30-asus-p1801-t.dts: linux,cma@80000000 {
arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi: linux,cma@80000000 {
arch/arm/boot/dts/nvidia/tegra30-ouya.dts: linux,cma@80000000 {
arch/arm/boot/dts/nvidia/tegra30-pegatron-chagall.dts: linux,cma@80000000 {
arch/arm/boot/dts/nvidia/tegra20-asus-transformer-common.dtsi: linux,cma@30000000 {
arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts: linux,cma@80000000 {
arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi: linux,cma@80000000 {
No objection to adding the address suffix to linux,multimedia node though.
>
>> +
>> + global_cma: linux,cma@58000000 {
>> + compatible = "shared-dma-pool";
>> + reg = <0x0 0x58000000 0x0 0x10000000>;
>> + reusable;
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb
2026-05-12 2:28 ` sashiko-bot
@ 2026-05-12 12:50 ` Josua Mayer
0 siblings, 0 replies; 12+ messages in thread
From: Josua Mayer @ 2026-05-12 12:50 UTC (permalink / raw)
To: sashiko@lists.linux.dev
Cc: devicetree@vger.kernel.org, wsa+renesas@sang-engineering.com,
krzk+dt@kernel.org, conor+dt@kernel.org, robh@kernel.org
Am 12.05.26 um 04:28 schrieb sashiko-bot@kernel.org:
> Thank you for your contribution! Sashiko AI review found 9 potential issue(s) to consider:
> - [High] USB VBUS pinmux nodes are defined but never referenced, breaking USB host power.
> - [High] Edge-triggered interrupt for TCAL6416 GPIO expander leads to lost interrupts.
> - [High] Inverse polarity on `rfkill-m2-b-gnss` disable GPIO will disable the GPS when it should be enabled.
> - [High] Omitted `GPIO_OPEN_DRAIN` flag on I2C mux reset line forces dangerous push-pull drive.
> - [Medium] Missing SDIO interrupt capabilities on WiFi MMC interface degrades performance.
> - [Medium] Pinctrl strict locking prevents documented manual RS485 toggling.
> - [Medium] Contradictory regulator polarity flags in `vmmc` create ambiguous regulator state.
> - [Medium] Unimplemented internal pull-ups on GPIO hogs lead to floating open-drain lines.
> - [Low] Improper append operator `+=` used for multi-blob DTB definitions in Makefile.
> --
>
> commit 264a692a0b295dedac1ff5214c5f24eb1c644647
> Author: Josua Mayer <josua@solid-run.com>
>
> arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb
>
> This commit adds support for the SolidRun RZ/G2L SoM on Hummingboard IIoT,
> including definitions for Ethernet, eMMC, DDR, and WiFi/Bluetooth.
> Descriptions for eMMC, microSD, and RS485 are provided as overlays due to
> their dependency on configurable mux states.
>
> [1] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/rz-g2l-som/
> [2] https://www.solid-run.com/embedded-industrial-iot/renesas-rz-family/hummingboard-rz-series-sbcs/hummingboard-rz-g2l-iot-sbc/
>
>> diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
>> index ca45d2857ea7f..37cfefe66a308 100644
>> --- a/arch/arm64/boot/dts/renesas/Makefile
>> +++ b/arch/arm64/boot/dts/renesas/Makefile
>> @@ -169,6 +169,19 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo
>> r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo
>> dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtb
>>
>> +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot.dtb
>> +dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-sr-som-emmc.dtbo
>> +r9a07g044l2-hummingboard-iiot-emmc-dtbs += r9a07g044l2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
> Is it safer to use the exact assignment operator := instead of the append
> operator += for composite device tree blobs? Standard Kbuild convention
> dictates using := for <target>-dtbs to ensure immediate evaluation and avoid
> any risk of build pollution from inherited environment variables.
Queued for v3.
>
> [ ... ]
>> diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi
>> new file mode 100644
>> index 0000000000000..ff2c42bcffe2f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi
> [ ... ]
>> + vmmc: regulator-mmc {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vmmc";
>> + regulator-max-microvolt = <3300000>;
>> + regulator-min-microvolt = <3300000>;
>> + startup-delay-us = <250>;
>> + vin-supply = <&v_3_3>;
>> + gpio = <&pinctrl RZG2L_GPIO(4, 1) GPIO_ACTIVE_LOW>;
>> + enable-active-high;
>> + };
> Mixing enable-active-high and GPIO_ACTIVE_LOW creates an ambiguous
> configuration. The fixed regulator driver interprets enable-active-high as a
> physical active-high requirement, but modern gpiolib automatically handles
> the GPIO_ACTIVE_LOW inversion at the descriptor level.
>
> Could this conflicting double-inversion cause the regulator to be driven to
> the wrong physical state and fail to power the eMMC module?
No double inversion because regulator driver ignores gpio flags.
Will align flags for v3, enable-active-high is intentional.
>
> [ ... ]
>> + rfkill-m2-b-gnss {
>> + compatible = "rfkill-gpio";
>> + /* rfkill-gpio inverts internally */
>> + shutdown-gpios = <&tca6416_u20 10 GPIO_ACTIVE_HIGH>;
>> + label = "m2-b gnss";
>> + radio-type = "gps";
>> + };
> The rfkill-gpio driver asserts shutdown_gpios (drives a logical 1) when the
> radio is turned on. With GPIO_ACTIVE_HIGH, a logical 1 maps to a physical
> HIGH signal.
>
> Since the pin is an active-low enable (GPS_EN#), driving it physically HIGH
> will disable the GPS. Does this cause the kernel to disable the GPS radio
> when it attempts to enable it? Should the polarity be GPIO_ACTIVE_LOW?
From rfkill-gpio driver:
gpiod_set_value_cansleep(rfkill->shutdown_gpio, !blocked);
this means deassert when blocked, assert when unblocked.
I have not seen an actual M.2 cecllular modem with builtin gps pinout,
so I am not sure what is correct.
Going strictly by board schematics, this is m.2 b-key pin 26, labelled M.2B_GPS_EN#,
indicating it enables gps when low.
So I shall change gpio flag accordingly for v3.
>
> [ ... ]
>> + tca6416_u21: gpio@21 {
>> + compatible = "ti,tcal6416";
>> + reg = <0x21>;
>> + #interrupt-cells = <2>;
>> + interrupt-controller;
>> + #gpio-cells = <2>;
>> + gpio-controller;
>> + gpio-line-names = "TCA_SPI_TPM/EXT", "TCA_TPM_RST#",
>> + "TCA_I2C_RST", "TCA_RS232_SHTD#",
>> + "TCA_LCD_I2C_RST", "TCA_DIG_OUT1",
>> + "TCA_bDIG_IN1", "TCA_SENS_INT",
>> + "TCA_ALERT#", "TCA_TPM_PIRQ#",
>> + "TCA_RTC_INT", "TCA_M.2M_WAKW_ON_LAN",
>> + "TCA_M.2M_CLKREQ#", "TCA_LVDS_INT#",
>> + "", "TCA_POE_AT";
>> + interrupts-extended = <&pinctrl RZG2L_GPIO(4, 0) IRQ_TYPE_EDGE_FALLING>;
> The hardware INT pin for the TCAL6416 GPIO expander is an active-low
> level-sensitive output that remains low as long as unread state changes
> exist.
>
> If this is configured as IRQ_TYPE_EDGE_FALLING, could the kernel miss
> subsequent interrupts if a second GPIO state change occurs before the first
> is cleared, since the line will remain low without generating a new falling
> edge? Should this be IRQ_TYPE_LEVEL_LOW instead?
Level interrupts did not work well in Renesas vendor fork,
and don't work at all in v6.1-rc1.
Interrupts may be lost but this is the best setting for now.
Adding comment for v3.
>
>> +
>> + lcd-i2c-reset-hog {
>> + gpios = <4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
> The ti,tcal6416 chip is driven by gpio-pca953x, which does not implement the
> .set_config callback for this specific IC because it lacks the PCA_PCAL
> hardware flag.
>
> Will gpiolib silently ignore the GPIO_PULL_UP flag? For open-drain lines
> like the lcd reset and the TPM interrupt below, could this leave the lines
> floating and lead to spurious interrupts or unstable hardware states if
> there are no external board-level pull-ups?
>
> [ ... ]
>> + i2c-mux@70 {
>> + compatible = "nxp,pca9546";
>> + reg = <0x70>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + /*
>> + * This reset is open drain,
>> + * but reset core does not support GPIO_OPEN_DRAIN flag.
>> + */
>> + reset-gpios = <&tca6416_u21 2 GPIO_ACTIVE_LOW>;
> The comment mentions that the reset core does not support the
> GPIO_OPEN_DRAIN flag, but the i2c-mux-pca954x driver requests the GPIO using
> devm_gpiod_get_optional(), which fully supports device tree flags.
The driver first tries reset core, and only falls back to direct gpio control.
The reset-core registers with reset-gpios properties by default,
so we must satisfy that and not the i2c device driver.
static int pca954x_get_reset(struct device *dev, struct pca954x *data)
{
data->reset_cont = devm_reset_control_get_optional_shared(dev, NULL);
if (IS_ERR(data->reset_cont))
return dev_err_probe(dev, PTR_ERR(data->reset_cont),
"Failed to get reset\n");
else if (data->reset_cont)
return 0;
/*
* fallback to legacy reset-gpios
*/
data->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(data->reset_gpio)) {
return dev_err_probe(dev, PTR_ERR(data->reset_gpio),
"Failed to get reset gpio");
}
return 0;
}
>
> By omitting the flag, does the GPIO controller get forced to drive the pin
> in push-pull mode? Could actively driving a hard-wired open-drain line high
> cause short circuits or component damage?
Nothing bad happens, the line has a 10k pull-up to same IO voltage as the
tca6416_u21.
>
> [ ... ]
>> diff --git a/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso
>> new file mode 100644
>> index 0000000000000..886f4d4ecd67f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-rs485-a.dtso
>> @@ -0,0 +1,21 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +/*
>> + * Copyright 2025 Josua Mayer <josua@solid-run.com>
>> + *
>> + * Overlay for enabling HummingBoard IIoT on-board RS485 Port A on connector J5004.
>> + *
>> + * Because Renesas uart driver does not support rs485,
>> + * users must manually toggle P41_1 between RX & TX.
> The overlay below adds <&scif1_rts_pins> to the pinctrl-0 property of the
> UART controllers. Since the Renesas RZ/G2L pinctrl driver operates in strict
> mode, it will exclusively claim these RTS pins.
>
> Will this prevent userspace from subsequently requesting these pins as GPIOs
> for the documented manual toggling, causing requests to be rejected with
> -EBUSY?
# gpioinfo
gpiochip0 - 392 lines:
line 329: "P41_1" kernel input active-high [used]
# gpioset 0 329=1
[ 342.868990] pinctrl-rzg2l 11030000.pinctrl: pin P41_1 already requested by 1004bc00.serial; cannot claim for 11030000.pinctrl:841
[ 342.880756] pinctrl-rzg2l 11030000.pinctrl: error -EINVAL: pin-329 (11030000.pinctrl:841)
gpioset: error setting the GPIO line values: Invalid argument
>> + */
>> +
>> +/dts-v1/;
>> +/plugin/;
>> +
>> +&scif1 {
>> + pinctrl-0 = <&scif1_pins>, <&scif1_rts_pins>;
>> +};
I'll drop the scif1_rts_pins reference vor v3.
> [ ... ]
>> diff --git a/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi
>> new file mode 100644
>> index 0000000000000..1d52530dcf43c
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi
> [ ... ]
>> +&sdhi1 {
>> + /* Murata 1MW max rate is 50MHz */
>> + max-frequency = <50000000>;
>> + bus-width = <4>;
>> + mmc-pwrseq = <&sdhi1_pwrseq>;
>> + non-removable;
>> + no-1-8-v;
>> + no-sd;
>> + pinctrl-0 = <&sdhi1_pins>;
>> + pinctrl-names = "default";
>> + vmmc-supply = <®_pmic_buck4>;
>> + /*
>> + * Host controller IO voltage is provided from reg_pmic_ldo2,
>> + * WiFi module IO voltage from reg_pmic_buck4.
>> + * Neither is configurable at run-time so either can be set here.
>> + */
>> + vqmmc-supply = <®_pmic_ldo2>;
>> + status = "okay";
>> +};
> The sdhi1 node is designated for an on-board WiFi module but omits the
> cap-sdio-irq property and lacks a child node defining an out-of-band
> interrupt.
>
> Will the MMC core fall back to SDIO polling without this capability
> declared,
Yes, this is expected.
> and could this degrade I/O performance and inflate CPU utilization?
We have not previously tested cap-sdio-irq on any SolidRun board,
however it appears to work okay on G2L SoM, v7.1-rc1.
Confirmed interrupt counters going up rapidly during iperf.
Queued for v3.
>
>> +
>> +&usb2_phy0 {
>> + vbus-supply = <&usb0_vbus_otg>;
>> + status = "okay";
>> +};
>> +
>> +&usb2_phy1 {
>> + status = "okay";
>> +};
> The usb0_vbus_pins and usb1_vbus_pins nodes are defined in the pinctrl
> section earlier in this file to configure the USB VBUS enable pins,
They are described in the SoM dtsi:
usb0_vbus_pins: usb0-vbus {
pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>; /* USB0_VBUSEN */
};
usb1_vbus_pins: usb1-vbus {
pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>; /* USB1_VBUSEN */
};
They are used as vbus-enable by HummigBoad Ripple,
which was not included in this patch-set for brevity.
The IIOT carrier board uses these pins for different functions:
tca6416_u21: gpio@21 {
interrupts-extended = <&pinctrl RZG2L_GPIO(4, 0) IRQ_TYPE_EDGE_FALLING>;
}
P42_0 is routed to a board-to-board expansion connector for future use.
> but
> neither &usb2_phy0 nor &usb2_phy1 appears to reference them via a pinctrl-0
> property.
>
> Without being multiplexed, will the USB host controllers be able to drive
> VBUS power to connected devices?
There is no issue here, usb power is controlled by other GPIOs.
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2026-05-12 12:50 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-11 10:37 [PATCH v2 0/4] arm64: dts: renesas: Add various SolidRun RZ/G2 based boards Josua Mayer
2026-05-11 10:37 ` [PATCH v2 1/4] dt-bindings: soc: " Josua Mayer
2026-05-11 16:28 ` Conor Dooley
2026-05-11 10:37 ` [PATCH v2 2/4] arm64: dts: renesas: add support for solidrun rzg2l som and hb-iiot evb Josua Mayer
2026-05-12 2:28 ` sashiko-bot
2026-05-12 12:50 ` Josua Mayer
2026-05-11 10:37 ` [PATCH v2 3/4] arm64: dts: renesas: add support for solidrun rzv2l " Josua Mayer
2026-05-12 2:43 ` sashiko-bot
2026-05-12 10:40 ` Josua Mayer
2026-05-11 10:37 ` [PATCH v2 4/4] arm64: dts: renesas: add support for solidrun rzg2lc " Josua Mayer
2026-05-12 3:18 ` sashiko-bot
2026-05-12 10:56 ` Josua Mayer
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