[PATCH v2 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC

[PATCH v2 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

This series enables the SMMU and adds DMA coherency support for the
XGMAC nodes across the affected board device trees.

Patch 1 enables the SMMU for the SoCFPGA board device trees where it
was missing. The SoC uses a different memory-mapped base address for
its peripherals, which requires the SMMU to be active so that the
Secure Device Manager (SDM) can correctly access those regions through
address translation.

Patch 2 adds the dma-coherent property to the XGMAC nodes. The SMMU
is enabled and transactions going through it are cache coherent.
Adding dma-coherent prevents redundant cache flush/invalidate
operations and potential stale data issues.

Changes in v2:
- Move SMMU enable into the base DTSI file instead of individual DTS files
- Move dma-coherent property into the base DTSI file instead of individual DTS files
- Improve commit messages and cover letter descriptions with more context on why the changes are needed

Nazim Amirul (2):
  arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees
  arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

-- 
2.43.7

[PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

Enable the SMMU on the SoCFPGA board device trees where it was
missing. The SoC uses a different memory-mapped base address for
its peripherals, which requires the System Memory Management Unit
(SMMU) to be active so that the Secure Device Manager (SDM) can
correctly access those regions through address translation.

Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
Changes in v2:
- Move SMMU enable into the base DTSI file instead of individual DTS files

 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index b06c6d5d60ee..64f3739a0c33 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -385,7 +385,7 @@ smmu: iommu@16000000 {
 			interrupt-names = "eventq", "gerror", "priq";
 			dma-coherent;
 			#iommu-cells = <1>;
-			status = "disabled";
+			status = "okay";
 		};
 
 		spi0: spi@10da4000 {
-- 
2.43.7

[PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

The SMMU is enabled and transactions going through it are cache
coherent. Add the dma-coherent property to the XGMAC nodes to prevent
redundant cache flush/invalidate operations and potential stale data
issues.

Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
Changes in v2:
- Move dma-coherent property into the base DTSI file instead of individual DTS files

 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 64f3739a0c33..bef386cb2fcc 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -577,6 +577,7 @@ gmac0: ethernet@10810000 {
 			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
 			snps,clk-csr = <0>;
 			iommus = <&smmu 1>;
+			dma-coherent;
 			status = "disabled";
 
 			stmmac_axi_emac0_setup: stmmac-axi-config {
@@ -690,6 +691,7 @@ gmac1: ethernet@10820000 {
 			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
 			snps,clk-csr = <0>;
 			iommus = <&smmu 2>;
+			dma-coherent;
 			status = "disabled";
 
 			stmmac_axi_emac1_setup: stmmac-axi-config {
@@ -803,6 +805,7 @@ gmac2: ethernet@10830000 {
 			altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
 			snps,clk-csr = <0>;
 			iommus = <&smmu 3>;
+			dma-coherent;
 			status = "disabled";
 
 			stmmac_axi_emac2_setup: stmmac-axi-config {
-- 
2.43.7

Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Incomplete Refactoring (Redundant Overrides)
--

commit 1b8d9495374546485f67ed52546157ae1e006ba8
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

This commit enables the SMMU on the SoCFPGA board device trees by setting its
status to okay in the base dtsi file. This is needed so the Secure Device
Manager can correctly access memory-mapped peripheral regions.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 352c96d144a84..527a5ef54c837 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -385,7 +385,7 @@ smmu: iommu@16000000 {
>  			interrupt-names = "eventq", "gerror", "priq";
>  			dma-coherent;
>  			#iommu-cells = <1>;
> -			status = "disabled";
> +			status = "okay";

This isn't a bug, but since the status is now set to okay in the base dtsi,
does this make the existing overrides in the board specific device trees
redundant?

For example, socfpga_agilex5_socdk_modular.dts,
socfpga_agilex5_socdk_013b.dts, and socfpga_agilex3_socdk.dts already
contain:

&smmu {
	status = "okay";
};

Could these board-level overrides be removed in this patch to maintain
device tree cleanliness?

>  		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260515080014.6260-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=1

Re: [PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing dma-coherent property on other SMMU clients causes data corruption
--

commit be9ce7db4922ed7d48488efa182130301cfa9435
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

The commit asserts that SMMU transactions are cache coherent and adds
dma-coherent to the XGMAC nodes. This prevents redundant cache flush and
invalidate operations and potential stale data issues.

> The SMMU is enabled and transactions going through it are cache
> coherent. Add the dma-coherent property to the XGMAC nodes to prevent
> redundant cache flush/invalidate operations and potential stale data
> issues.

This problem wasn't introduced by this patch, but the patch provides an
incomplete fix.

The commit message asserts that "transactions going through it are cache
coherent" and correctly notes that missing the dma-coherent property causes
"potential stale data issues".

On ARM64, if a hardware-coherent device is treated as non-coherent, the kernel
will execute cache invalidation (dcache_inval_poc -> dc ivac via
arch_sync_dma_for_cpu) for DMA_FROM_DEVICE transfers.

If the device wrote data directly into the CPU caches, the dc ivac instruction
will discard those dirty cache lines without writing them back to RAM. This
destroys the DMA writes and causes the CPU to read stale data from memory,
resulting in reproducible data corruption.

If the SMMU provides coherency for all transactions, do other major DMA
masters that also route through the SMMU need the dma-coherent property?

For example, usb0, dmac0, and dmac1 use the SMMU but lack the property:

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi:
    usb0: usb@10b00000 {
        ...
        iommus = <&smmu 6>;
        ...
    };

    dmac0: dma-controller@0 {
        ...
        iommus = <&smmu 8>;
        ...
    };

    dmac1: dma-controller@10000 {
        ...
        iommus = <&smmu 9>;
        ...
    };

If coherency is specific only to XGMAC, could the commit message be clarified
to avoid a blanket statement about the SMMU?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260515080014.6260-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=2