[PATCH v3 0/4] arm64: qcom: add Ayaneo Pocket DS gaming console

[PATCH v3 0/4] arm64: qcom: add Ayaneo Pocket DS gaming console

[Alexandre Hamamdjian via B4 Relay]

This series adds initial support for the Ayaneo Pocket DS, a handheld
gaming console built around the Qualcomm QCS8550 SoC. It has UFS
storage, WiFi/Bluetooth, gaming buttons, microSD, dual displays, and
USB-C with DisplayPort. Game controls are exposed through a Renesas
uPD720201 PCIe USB 3.0 host controller hung off PCIe1, while a
dedicated gamepad MCU is reached over UART11.

The series is structured as:

  1. dt-bindings entry for the new qcom,qcs8550-ayaneo-pocketds
     compatible.
  2. sm8550.dtsi: add labels for the cpuss/cpu/gpuss thermal zones so
     the board can extend them with trip points and cooling maps via
     &label overrides instead of redeclaring zones by path.
  3. The Pocket DS board device tree itself, with the root-level
     nodes alphabetised and the fixed regulators named per the
     "<name>-regulator" convention.
  4. sm8550.dtsi: add the QUP2 SE3 (UART11) controller node and its
     default pinctrl, so the board can enable it as &uart11 instead
     of open-coding the controller in the board dts.

Only the basics are wired up at this stage (boot to console, core
peripherals, USB-C and DP); the display panel will follow in a later
submission.

Signed-off-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
---
Changes in v3:
- New prerequisite patch adding the QUP2 SE3 (UART11) controller node
  and the qup_uart11_default pinctrl state to sm8550.dtsi, so the
  board can enable the gamepad MCU UART via &uart11 instead of
  duplicating the controller node in the board dts.
- Alphabetised the root-level nodes in the board dts and renamed the
  fixed regulators to the "<name>-regulator" node-name convention.
- Link to v2: https://patch.msgid.link/20260511-pocketds-v2-0-299dd4247f2f@gmail.com

Changes in v2:
- Inlined the board into a single qcs8550-ayaneo-pocketds.dts, matching
  the sm8650-ayaneo-pocket-s2 layout
- Added qcom,qcs8550 to the compatible chain
- Prerequisite patch labelling the sm8550 thermal zones so the board
  can extend them via &label overrides (and refactored the board's
  thermal-zones to use them)
- Added the Renesas uPD720201 USB 3.0 controller as a child of pcie1
  with proper avdd33 / vdd10 / vdd33 regulators
- Moved gamepad_pwr_en off &pcie1's pinctrl-0 and onto the
  usb-controller node
- Split the lumped upd720201_active pinctrl into per-regulator states
- Fixed mdss_dp0_out data-lanes to <0 1 2 3> (all four wired)
- Fixed gpio-reserved-ranges to <32 4> (gpio 38-39 drive the Goodix
  touchscreen)
- Renamed nodes with underscores (llcc-lpi-region, splash-region,
  gpio@20) per DT conventions
- Reordered pinctrl-names after pinctrl-N file-wide
- Dropped the unused cont_splash_region label
- Link to v1: https://patch.msgid.link/20260510-pocketds-v1-0-cf05acec06af@gmail.com

To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

---
Alexandre Hamamdjian (3):
      dt-bindings: arm: qcom: document the Ayaneo Pocket DS
      arm64: dts: qcom: sm8550: add labels for thermal zones
      arm64: dts: qcom: sm8550: add UART11 node

Teguh Sobirin (1):
      arm64: dts: qcom: add basic devicetree for Ayaneo Pocket DS gaming console

 Documentation/devicetree/bindings/arm/qcom.yaml    |    6 +
 arch/arm64/boot/dts/qcom/Makefile                  |    1 +
 .../boot/dts/qcom/qcs8550-ayaneo-pocketds.dts      | 1883 ++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sm8550.dtsi               |   52 +-
 4 files changed, 1929 insertions(+), 13 deletions(-)
---
base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83
change-id: 20260510-pocketds-e0e7b99cf369

Best regards,
--  
Alexandre Hamamdjian <azkali.limited@gmail.com>

[PATCH v3 1/4] dt-bindings: arm: qcom: document the Ayaneo Pocket DS

[Alexandre Hamamdjian via B4 Relay]

From: Alexandre Hamamdjian <azkali.limited@gmail.com>

Document the Qualcomm QCS8550 based Ayaneo Pocket DS gaming console.

Signed-off-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 2741c07e9f41..f130a6b092b9 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -1107,6 +1107,12 @@ properties:
           - const: qcom,qcs8550
           - const: qcom,sm8550
 
+      - items:
+          - enum:
+              - ayaneo,pocketds
+          - const: qcom,qcs8550
+          - const: qcom,sm8550
+
       - items:
           - enum:
               - ayaneo,pocket-s2

-- 
2.54.0

[PATCH v3 2/4] arm64: dts: qcom: sm8550: add labels for thermal zones

[Alexandre Hamamdjian via B4 Relay]

From: Alexandre Hamamdjian <azkali.limited@gmail.com>

Add labels for the cpuss, cpu and gpuss thermal zones so board files
can extend them with trip points and cooling maps through the &label
override syntax, instead of redeclaring the zones by path.

Signed-off-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 912525e9bca6..a9c678fc9cb2 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -5764,7 +5764,7 @@ reset-mon-config {
 			};
 		};
 
-		cpuss0-thermal {
+		cpuss0_thermal: cpuss0-thermal {
 			thermal-sensors = <&tsens0 1>;
 
 			trips {
@@ -5782,7 +5782,7 @@ reset-mon-config {
 			};
 		};
 
-		cpuss1-thermal {
+		cpuss1_thermal: cpuss1-thermal {
 			thermal-sensors = <&tsens0 2>;
 
 			trips {
@@ -5800,7 +5800,7 @@ reset-mon-config {
 			};
 		};
 
-		cpuss2-thermal {
+		cpuss2_thermal: cpuss2-thermal {
 			thermal-sensors = <&tsens0 3>;
 
 			trips {
@@ -5818,7 +5818,7 @@ reset-mon-config {
 			};
 		};
 
-		cpuss3-thermal {
+		cpuss3_thermal: cpuss3-thermal {
 			thermal-sensors = <&tsens0 4>;
 
 			trips {
@@ -6028,7 +6028,7 @@ cpu6_bottom_crit: cpu-critical {
 			};
 		};
 
-		cpu7-top-thermal {
+		cpu7_top_thermal: cpu7-top-thermal {
 			thermal-sensors = <&tsens0 13>;
 
 			trips {
@@ -6536,7 +6536,7 @@ reset-mon-config {
 			};
 		};
 
-		gpuss-0-thermal {
+		gpuss0_thermal: gpuss-0-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 1>;
@@ -6569,7 +6569,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-1-thermal {
+		gpuss1_thermal: gpuss-1-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 2>;
@@ -6602,7 +6602,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-2-thermal {
+		gpuss2_thermal: gpuss-2-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 3>;
@@ -6635,7 +6635,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-3-thermal {
+		gpuss3_thermal: gpuss-3-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 4>;
@@ -6668,7 +6668,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-4-thermal {
+		gpuss4_thermal: gpuss-4-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 5>;
@@ -6701,7 +6701,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-5-thermal {
+		gpuss5_thermal: gpuss-5-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 6>;
@@ -6734,7 +6734,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-6-thermal {
+		gpuss6_thermal: gpuss-6-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 7>;
@@ -6767,7 +6767,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-7-thermal {
+		gpuss7_thermal: gpuss-7-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 8>;

-- 
2.54.0

[PATCH v3 3/4] arm64: dts: qcom: add basic devicetree for Ayaneo Pocket DS gaming console

[Alexandre Hamamdjian via B4 Relay]

From: Teguh Sobirin <teguh@sobir.in>

Add initial Device Tree for the Ayaneo Pocket DS gaming console based
on the Qualcomm QCS8550 platform.

The design is similar to a phone without the modem, the game control
is handled via a standalone controller connected to a Renesas uPD720201
PCIe USB 3.0 host controller. DisplayPort is muxed over the USB-C
connector with all four lanes wired.

Display panel support will be added in a second time.

Co-developed-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
Signed-off-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
Signed-off-by: Teguh Sobirin <teguh@sobir.in>
---
 arch/arm64/boot/dts/qcom/Makefile                  |    1 +
 .../boot/dts/qcom/qcs8550-ayaneo-pocketds.dts      | 1883 ++++++++++++++++++++
 2 files changed, 1884 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index cc42829f92eb..45859e977bc9 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -185,6 +185,7 @@ qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo
 
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs8300-ride-el2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-aim300-aiot.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-ayaneo-pocketds.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride-r3.dtb
 
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts
new file mode 100644
index 000000000000..416399a4179b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts
@@ -0,0 +1,1883 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Teguh Sobirin.
+ * Copyright (c) 2025, ROCKNIX (https://github.com/ROCKNIX)
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qcs8550.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+/delete-node/ &aop_image_mem;
+/delete-node/ &aop_config_mem;
+/delete-node/ &camera_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &ipa_gsi_mem;
+/delete-node/ &mpss_dsm_mem;
+/delete-node/ &mpss_mem;
+/delete-node/ &q6_mpss_dtb_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &q6_cdsp_dtb_mem;
+
+/delete-node/ &remoteproc_mpss;
+/delete-node/ &remoteproc_cdsp;
+
+/ {
+	model = "AYANEO Pocket DS";
+	compatible = "ayaneo,pocketds", "qcom,qcs8550", "qcom,sm8550";
+	rocknix-u-boot-dt-id = "u-boot-pocket-ds";
+
+	aliases {
+		serial0 = &uart7;
+		serial1 = &uart14;
+		hsuart0 = &uart11;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	pmic-glink {
+		compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+
+		connector@0 {
+			compatible = "usb-c-connector";
+
+			reg = <0>;
+
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_hs_in: endpoint {
+						remote-endpoint = <&usb_1_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss_in: endpoint {
+						remote-endpoint = <&redriver_ss_out>;
+					};
+				};
+			};
+		};
+	};
+
+	pwm_fan: pwm-fan {
+		compatible = "pwm-fan";
+
+		pinctrl-0 = <&fan_pwm_active>, <&fan_int>;
+		pinctrl-names = "default", "sleep";
+
+		fan-supply = <&vdd_fan_5v0>;
+		pwms = <&pm8550_pwm 3 40000>;
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <64 IRQ_TYPE_EDGE_FALLING>;
+
+		#cooling-cells = <2>;
+		cooling-levels = <0 30 45 60 70 90 120 150>;
+	};
+
+	reserved-memory {
+		hyp_mem: hyp-region@80000000 {
+			reg = <0 0x80000000 0 0xa00000>;
+			no-map;
+		};
+
+		cpusys_vm_mem: cpusys-vm-region@80a00000 {
+			reg = <0 0x80a00000 0 0x400000>;
+			no-map;
+		};
+
+		hyp_tags_mem: hyp-tags-region@80e00000 {
+			reg = <0 0x80e00000 0 0x3d0000>;
+			no-map;
+		};
+
+		xbl_sc_mem: xbl-sc-region@d8100000 {
+			reg = <0 0xd8100000 0 0x40000>;
+			no-map;
+		};
+
+		hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
+			reg = <0 0x811d0000 0 0x30000>;
+			no-map;
+		};
+
+		xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
+			reg = <0 0x81a00000 0 0x260000>;
+			no-map;
+		};
+
+		aop_config_merged_mem: aop-config-merged-region@81c80000 {
+			reg = <0 0x81c80000 0 0x74000>;
+			no-map;
+		};
+
+		chipinfo_mem: chipinfo-region@81cf4000 {
+			reg = <0 0x81cf4000 0 0x1000>;
+			no-map;
+		};
+
+		global_sync_mem: global-sync-region@82600000 {
+			reg = <0 0x82600000 0 0x100000>;
+			no-map;
+		};
+
+		tz_stat_mem: tz-stat-region@82700000 {
+			reg = <0 0x82700000 0 0x100000>;
+			no-map;
+		};
+
+		cpucp_fw_mem: cpucp-fw-region@d8140000 {
+			reg = <0 0xd8140000 0 0x1c0000>;
+			no-map;
+		};
+
+		qtee_mem: qtee-region@d8300000 {
+			reg = <0 0xd8300000 0 0x500000>;
+			no-map;
+		};
+
+		hwfence_shbuf: hwfence-shbuf-region@e6440000 {
+			reg = <0 0xe6440000 0 0x2dd000>;
+			no-map;
+		};
+
+		hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
+			reg = <0 0xff700000 0 0x100000>;
+			no-map;
+		};
+
+		llcc_lpi_mem: llcc-lpi-region@ff800000 {
+			reg = <0 0xff800000 0 0x600000>;
+			no-map;
+		};
+
+		hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
+			reg = <0 0xfce00000 0 0x2900000>;
+			no-map;
+		};
+
+		splash_region: splash-region@b8000000 {
+			reg = <0x0 0xb8000000 0x0 0x2b00000>;
+			no-map;
+		};
+	};
+
+	sound {
+		compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
+		model = "SM8550-APS";
+
+		audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+				"SpkrRight IN", "WSA_SPK2 OUT",
+				"VA DMIC0", "vdd-micb",
+				"VA DMIC1", "vdd-micb";
+
+		wsa-dai-link {
+			link-name = "WSA Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&spk_amp_l>,
+					    <&spk_amp_r>,
+					    <&swr0 0>,
+					    <&lpass_wsamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		va-dai-link {
+			link-name = "VA Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+			};
+
+			codec {
+				sound-dai = <&lpass_vamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
+
+	tca6424_vcc: tca6424-vcc-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "tca6424_vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 168 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	upd720201_avdd33_reg: upd720201-avdd33-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "upd720201_avdd33";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		vin-supply = <&vph_pwr>;
+
+		pinctrl-0 = <&upd720201_avdd33>;
+		pinctrl-names = "default";
+	};
+
+	upd720201_vdd10_reg: upd720201-vdd10-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "upd720201_vdd10";
+		regulator-min-microvolt = <1050000>;
+		regulator-max-microvolt = <1050000>;
+
+		gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		vin-supply = <&vph_pwr>;
+
+		pinctrl-0 = <&upd720201_vdd10>;
+		pinctrl-names = "default";
+	};
+
+	upd720201_vdd33_reg: upd720201-vdd33-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "upd720201_vdd33";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		vin-supply = <&vph_pwr>;
+
+		pinctrl-0 = <&upd720201_vdd33>;
+		pinctrl-names = "default";
+	};
+
+	vdd_fan_5v0: vdd-fan-5v0-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vdd_fan_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+
+		gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&fan_pwr_active>;
+		pinctrl-names = "default";
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_ts: vdd-ts-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vdd_ts_en";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tca6408 1 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	wcn7850-pmu {
+		compatible = "qcom,wcn7850-pmu";
+
+		pinctrl-0 = <&wlan_en>, <&bt_default>, <&pmk8550_sleep_clk>;
+		pinctrl-names = "default";
+
+		wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+
+		vdd-supply = <&vreg_s5g_0p85>;
+		vddio-supply = <&vreg_l15b_1p8>;
+		vddaon-supply = <&vreg_s2g_0p85>;
+		vdddig-supply = <&vreg_s4e_0p95>;
+		vddrfa1p2-supply = <&vreg_s4g_1p25>;
+		vddrfa1p8-supply = <&vreg_s6g_1p86>;
+
+		regulators {
+			vreg_pmu_rfa_cmn: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn";
+			};
+
+			vreg_pmu_aon_0p59: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p59";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p85: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p85";
+			};
+
+			vreg_pmu_btcmx_0p85: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p85";
+			};
+
+			vreg_pmu_rfa_0p8: ldo5 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo6 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p8: ldo7 {
+				regulator-name = "vreg_pmu_rfa_1p8";
+			};
+
+			vreg_pmu_pcie_0p9: ldo8 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_pcie_1p8: ldo9 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+		};
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-bob1-supply = <&vph_pwr>;
+		vdd-bob2-supply = <&vph_pwr>;
+		vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l3-supply = <&vreg_s4g_1p25>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob1>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l11-supply = <&vreg_s4g_1p25>;
+		vdd-l12-supply = <&vreg_s6g_1p86>;
+		vdd-l15-supply = <&vreg_s6g_1p86>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3296000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2720000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p1: ldo5 {
+			regulator-name = "vreg_l5b_3p1";
+			regulator-min-microvolt = <3104000>;
+			regulator-max-microvolt = <3104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_1p8: ldo7 {
+			regulator-name = "vreg_l7b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8b_1p8: ldo8 {
+			regulator-name = "vreg_l8b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_2p9: ldo9 {
+			regulator-name = "vreg_l9b_2p9";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10b_1p8: ldo10 {
+			regulator-name = "vreg_l10b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l11b_1p2: ldo11 {
+			regulator-name = "vreg_l11b_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p8: ldo12 {
+			regulator-name = "vreg_l12b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p2: ldo14 {
+			regulator-name = "vreg_l14b_3p2";
+			regulator-min-microvolt = <3200000>;
+			regulator-max-microvolt = <3200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16b_2p8: ldo16 {
+			regulator-name = "vreg_l16b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-l1-supply = <&vreg_s4g_1p25>;
+		vdd-l2-supply = <&vreg_s4e_0p95>;
+		vdd-l3-supply = <&vreg_s4e_0p95>;
+
+		vreg_l3c_0p9: ldo3 {
+			regulator-name = "vreg_l3c_0p9";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+		qcom,pmic-id = "d";
+
+		vdd-l1-supply = <&vreg_s4e_0p95>;
+		vdd-l2-supply = <&vreg_s4e_0p95>;
+		vdd-l3-supply = <&vreg_s4e_0p95>;
+
+		vreg_l1d_0p88: ldo1 {
+			regulator-name = "vreg_l1d_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-3 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+		qcom,pmic-id = "e";
+
+		vdd-l1-supply = <&vreg_s4e_0p95>;
+		vdd-l2-supply = <&vreg_s4e_0p95>;
+		vdd-l3-supply = <&vreg_s4g_1p25>;
+		vdd-s4-supply = <&vph_pwr>;
+		vdd-s5-supply = <&vph_pwr>;
+
+		vreg_s4e_0p95: smps4 {
+			regulator-name = "vreg_s4e_0p95";
+			regulator-min-microvolt = <904000>;
+			regulator-max-microvolt = <984000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5e_1p08: smps5 {
+			regulator-name = "vreg_s5e_1p08";
+			regulator-min-microvolt = <1010000>;
+			regulator-max-microvolt = <1120000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1e_0p88: ldo1 {
+			regulator-name = "vreg_l1e_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2e_0p9: ldo2 {
+			regulator-name = "vreg_l2e_0p9";
+			regulator-min-microvolt = <904000>;
+			regulator-max-microvolt = <970000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3e_1p2: ldo3 {
+			regulator-name = "vreg_l3e_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "f";
+
+		vdd-l1-supply = <&vreg_s4e_0p95>;
+		vdd-l2-supply = <&vreg_s4e_0p95>;
+		vdd-l3-supply = <&vreg_s4e_0p95>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		vreg_s4f_0p5: smps4 {
+			regulator-name = "vreg_s4f_0p5";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <700000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1f_0p9: ldo1 {
+			regulator-name = "vreg_l1f_0p9";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_0p88: ldo2 {
+			regulator-name = "vreg_l2f_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_0p88: ldo3 {
+			regulator-name = "vreg_l3f_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-5 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+		qcom,pmic-id = "g";
+
+		vdd-l1-supply = <&vreg_s4g_1p25>;
+		vdd-l2-supply = <&vreg_s4g_1p25>;
+		vdd-l3-supply = <&vreg_s4g_1p25>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+		vdd-s5-supply = <&vph_pwr>;
+		vdd-s6-supply = <&vph_pwr>;
+
+		vreg_s1g_1p25: smps1 {
+			regulator-name = "vreg_s1g_1p25";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s2g_0p85: smps2 {
+			regulator-name = "vreg_s2g_0p85";
+			regulator-min-microvolt = <800000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3g_0p8: smps3 {
+			regulator-name = "vreg_s3g_0p8";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <1004000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4g_1p25: smps4 {
+			regulator-name = "vreg_s4g_1p25";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1352000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5g_0p85: smps5 {
+			regulator-name = "vreg_s5g_0p85";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <1004000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s6g_1p86: smps6 {
+			regulator-name = "vreg_s6g_1p86";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1g_1p2: ldo1 {
+			regulator-name = "vreg_l1g_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3g_1p2: ldo3 {
+			regulator-name = "vreg_l3g_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&cpu7_top_thermal {
+	polling-delay = <200>;
+
+	trips {
+		cpu7_top_fan0: trip-point2 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpu7_top_fan1: trip-point3 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpu7_top_fan2: trip-point4 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&cpuss0_thermal {
+	polling-delay = <200>;
+
+	trips {
+		cpuss0_fan0: trip-point2 {
+			temperature = <40000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss0_fan1: trip-point3 {
+			temperature = <50000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss0_fan2: trip-point4 {
+			temperature = <60000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss0_fan3: trip-point5 {
+			temperature = <65000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss0_fan4: trip-point6 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss0_fan5: trip-point7 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss0_fan6: trip-point8 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&cpuss1_thermal {
+	polling-delay = <200>;
+
+	trips {
+		cpuss1_fan0: trip-point2 {
+			temperature = <40000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss1_fan1: trip-point3 {
+			temperature = <50000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss1_fan2: trip-point4 {
+			temperature = <60000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss1_fan3: trip-point5 {
+			temperature = <65000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss1_fan4: trip-point6 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss1_fan5: trip-point7 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss1_fan6: trip-point8 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&cpuss2_thermal {
+	polling-delay = <200>;
+
+	trips {
+		cpuss2_fan0: trip-point2 {
+			temperature = <40000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss2_fan1: trip-point3 {
+			temperature = <50000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss2_fan2: trip-point4 {
+			temperature = <60000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss2_fan3: trip-point5 {
+			temperature = <65000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss2_fan4: trip-point6 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss2_fan5: trip-point7 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss2_fan6: trip-point8 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&cpuss3_thermal {
+	polling-delay = <200>;
+
+	trips {
+		cpuss3_fan0: trip-point2 {
+			temperature = <40000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss3_fan1: trip-point3 {
+			temperature = <50000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss3_fan2: trip-point4 {
+			temperature = <60000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss3_fan3: trip-point5 {
+			temperature = <65000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss3_fan4: trip-point6 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss3_fan5: trip-point7 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss3_fan6: trip-point8 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpi_dma1 {
+	status = "okay";
+};
+
+&gpi_dma2 {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&gpu_opp_table {
+	opp-719000000 {
+		opp-hz = /bits/ 64 <719000000>;
+		opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+		opp-peak-kBps = <10687500>;
+		qcom,opp-acd-level = <0x882e5ffd>;
+	};
+
+	opp-746000000 {
+		opp-hz = /bits/ 64 <746000000>;
+		opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+		opp-peak-kBps = <10687500>;
+		qcom,opp-acd-level = <0x882e5ffd>;
+	};
+
+	opp-794000000 {
+		opp-hz = /bits/ 64 <794000000>;
+		opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+		opp-peak-kBps = <14398438>;
+		qcom,opp-acd-level = <0xa82d5ffd>;
+	};
+
+	opp-827000000 {
+		opp-hz = /bits/ 64 <827000000>;
+		opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+		opp-peak-kBps = <16500000>;
+		qcom,opp-acd-level = <0xa82d5ffd>;
+	};
+
+	opp-860000000 {
+		opp-hz = /bits/ 64 <860000000>;
+		opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+		opp-peak-kBps = <16500000>;
+		qcom,opp-acd-level = <0x882d5ffd>;
+	};
+
+	opp-1000000000 {
+		opp-hz = /bits/ 64 <1000000000>;
+		opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+		opp-peak-kBps = <16500000>;
+		qcom,opp-acd-level = <0x882d5ffd>;
+	};
+};
+
+&gpu_zap_shader {
+	firmware-name = "qcom/sm8550/a740_zap.mbn";
+};
+
+&gpuss0_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss0_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss0_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss0_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss1_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss1_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss1_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss1_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss2_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss2_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss2_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss2_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss3_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss3_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss3_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss3_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss4_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss4_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss4_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss4_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss5_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss5_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss5_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss5_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss6_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss6_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss6_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss6_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss7_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss7_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss7_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss7_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	tca6408: gpio@20 {
+		compatible = "ti,tca6408";
+		reg = <0x20>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		vcc-supply = <&tca6424_vcc>;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	touchscreen@5d {
+		compatible = "goodix,gt911";
+		reg = <0x5d>;
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
+
+		reset-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>;
+		irq-gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
+
+		VDDIO-supply = <&vdd_ts>;
+
+		pinctrl-0 = <&ts2_reset>, <&ts2_irq>;
+		pinctrl-names = "default";
+
+		touchscreen-size-x = <768>;
+		touchscreen-size-y = <1024>;
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	touchscreen: touchscreen@38 {
+		compatible = "focaltech,ft5426";
+		reg = <0x38>;
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+
+		reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
+
+		vcc-supply = <&vreg_l14b_3p2>;
+		iovcc-supply = <&vreg_l12b_1p8>;
+
+		pinctrl-0 = <&ts_int_default &ts_rst_default>;
+		pinctrl-1 = <&ts_int_sleep &ts_rst_sleep>;
+		pinctrl-names = "default", "sleep";
+
+		touchscreen-size-x = <1080>;
+		touchscreen-size-y = <1920>;
+	};
+};
+
+&i2c_hub_2 {
+	status = "okay";
+
+	typec-retimer@1c {
+		compatible = "onnn,nb7vpq904m";
+		reg = <0x1c>;
+
+		vcc-supply = <&vreg_l15b_1p8>;
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				redriver_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				redriver_ss_in: endpoint {
+					data-lanes = <3 2 1 0>;
+					remote-endpoint = <&usb_dp_qmpphy_out>;
+				};
+			};
+		};
+	};
+};
+
+&i2c_master_hub_0 {
+	status = "okay";
+};
+
+&iris {
+	status = "okay";
+};
+
+/* DMIC 01 23 */
+&lpass_vamacro {
+	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+	pinctrl-names = "default";
+
+	vdd-micb-supply = <&vreg_l10b_1p8>;
+
+	qcom,dmic-sample-rate = <4800000>;
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dp0 {
+	status = "okay";
+};
+
+&mdss_dp0_out {
+	remote-endpoint = <&panel0_in>;
+
+	data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0 {
+	vdda-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+
+	display_panel: panel@0 {
+		reg = <0>;
+
+		pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>;
+		pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>;
+		pinctrl-names = "default", "sleep";
+	};
+};
+
+&mdss_dsi0_phy {
+	vdds-supply = <&vreg_l1e_0p88>;
+
+	status = "okay";
+};
+
+&mdss_dsi1 {
+	vdda-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+
+	panel@0 {
+		reg = <0>;
+
+		pinctrl-0 = <&sde_dsi1_active>;
+		pinctrl-1 = <&sde_dsi1_suspend>;
+		pinctrl-names = "default", "sleep";
+	};
+};
+
+&mdss_dsi1_out {
+	remote-endpoint = <&panel1_in>;
+	data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi1_phy {
+	vdds-supply = <&vreg_l1e_0p88>;
+	status = "okay";
+};
+
+&pcie0 {
+	wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+	perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+	max-link-speed = <3>;
+
+	pinctrl-0 = <&pcie0_default_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie1 {
+	wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+	perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+
+	pinctrl-0 = <&pcie1_default_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	pcie@0 {
+		/* Renesas μPD720201 PCIe USB3.0 HOST CONTROLLER */
+		usb-controller@0 {
+			compatible = "pci1912,0014";
+			reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+			avdd33-supply = <&upd720201_avdd33_reg>;
+			vdd10-supply = <&upd720201_vdd10_reg>;
+			vdd33-supply = <&upd720201_vdd33_reg>;
+
+			pinctrl-0 = <&gamepad_pwr_en>;
+			pinctrl-names = "default";
+		};
+	};
+};
+
+&pcie1_phy {
+	vdda-phy-supply = <&vreg_l3c_0p9>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+	vdda-qref-supply = <&vreg_l1e_0p88>;
+
+	status = "okay";
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&pm8550_gpios {
+	sdc2_card_det_n: sdc2-card-det-n-state {
+		pins = "gpio12";
+		function = "normal";
+		input-enable;
+		output-disable;
+		bias-pull-up;
+		power-source = <1>;
+	};
+
+	volume_up_n: volume-up-n-state {
+		pins = "gpio6";
+		function = "normal";
+		power-source = <1>;
+		bias-pull-up;
+		input-enable;
+	};
+
+	fan_pwm_active: fan-pwm-active-state {
+		pins = "gpio9";
+		function = "func1";
+		output-low;
+		bias-disable;
+		power-source = <0>;
+		qcom,drive-strength = <3>; /* PMIC_GPIO_STRENGTH_LOW */
+	};
+};
+
+&pm8550_pwm {
+	status = "okay";
+};
+
+&pm8550b_eusb2_repeater {
+	vdd18-supply = <&vreg_l15b_1p8>;
+	vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pmk8550_gpios {
+	pmk8550_sleep_clk: sleep-clk-state {
+		pins = "gpio3";
+		function = "func1";
+		input-disable;
+		output-enable;
+		bias-disable;
+		power-source = <0>;
+	};
+};
+
+&pmk8550_rtc {
+	nvmem-cells = <&rtc_offset>;
+	nvmem-cell-names = "offset";
+};
+
+&pmk8550_sdam_2 {
+	rtc_offset: rtc-offset@bc {
+		reg = <0xbc 0x4>;
+	};
+};
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&qupv3_id_1 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/sm8550/ayaneo/adsp.mdt",
+			"qcom/sm8550/ayaneo/adsp_dtb.mdt";
+
+	status = "okay";
+};
+
+&sdhc_2 {
+	cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
+
+	pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+	pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+	pinctrl-names = "default", "sleep";
+
+	vmmc-supply = <&vreg_l9b_2p9>;
+	vqmmc-supply = <&vreg_l8b_1p8>;
+
+	no-sdio;
+	no-mmc;
+
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+
+	qcom,dll-config = <0x0007442c>;
+	sdhci-caps-mask = <0x3 0x0>;
+
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32764>;
+};
+
+&swr0 {
+	status = "okay";
+
+	spk_amp_l: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+
+		pinctrl-0 = <&spkr_1_sd_n_active>;
+		pinctrl-names = "default";
+
+		powerdown-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>;
+
+		vdd-1p8-supply = <&vreg_l10b_1p8>;
+		vdd-io-supply = <&vreg_l10b_1p8>;
+
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrLeft";
+		qcom,port-mapping = <1 2 3 7 10 13>;
+	};
+
+	spk_amp_r: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+
+		pinctrl-0 = <&spkr_2_sd_n_active>;
+		pinctrl-names = "default";
+
+		powerdown-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
+
+		vdd-1p8-supply = <&vreg_l10b_1p8>;
+		vdd-io-supply = <&vreg_l10b_1p8>;
+
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrRight";
+		qcom,port-mapping = <4 5 6 7 11 13>;
+	};
+};
+
+&tlmm {
+	gpio-reserved-ranges = <32 4>;
+
+	bt_default: bt-default-state {
+		bt-en-pins {
+			pins = "gpio81";
+			function = "gpio";
+			drive-strength = <16>;
+			bias-disable;
+		};
+
+		sw-ctrl-pins {
+			pins = "gpio82";
+			function = "gpio";
+			bias-pull-down;
+		};
+	};
+
+	fan_pwr_active: fan-pwr-active-state {
+		pins = "gpio31";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	fan_int: fan-int-state {
+		pins = "gpio64";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	upd720201_avdd33: upd720201-avdd33-state {
+		pins = "gpio10";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	upd720201_vdd10: upd720201-vdd10-state {
+		pins = "gpio13";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	upd720201_vdd33: upd720201-vdd33-state {
+		pins = "gpio18";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	gamepad_pwr_en: gamepad-pwr-en-active-state {
+		pins = "gpio52";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-high;
+	};
+
+	sde_dsi_active: sde-dsi-active-state {
+		pins = "gpio133";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+		output-high;
+	};
+
+	sde_dsi_suspend: sde-dsi-suspend-state {
+		pins = "gpio133";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	sde_te_active: sde-te-active-state {
+		pins = "gpio86";
+		function = "mdp_vsync";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	sde_te_suspend: sde-te-suspend-state {
+		pins = "gpio86";
+		function = "mdp_vsync";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	wlan_en: wlan-en-state {
+		pins = "gpio80";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-down;
+	};
+
+	spkr_1_sd_n_active: spkr-1-sd-n-active-state {
+		pins = "gpio7";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-high;
+	};
+
+	spkr_2_sd_n_active: spkr-2-sd-n-active-state {
+		pins = "gpio12";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-high;
+	};
+
+	panel_pwr_active: panel-pwr-active-state {
+		pins = "gpio152", "gpio153";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+		output-high;
+	};
+
+	sde_dsi1_active: sde-dsi1-active-state {
+		pins = "gpio137";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+		output-high;
+	};
+
+	sde_dsi1_suspend: sde-dsi1-suspend-state {
+		pins = "gpio137";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	ts_rst_default: ts-rst-default-state {
+		pins = "gpio24";
+		function = "gpio";
+		bias-pull-up;
+		drive-strength = <8>;
+	};
+
+	ts_rst_sleep: ts-rst-sleep-state {
+		pins = "gpio24";
+		function = "gpio";
+		bias-pull-down;
+		drive-strength = <2>;
+	};
+
+	ts_int_default: ts-int-default-state {
+		pins = "gpio25";
+		function = "gpio";
+		bias-pull-up;
+		drive-strength = <8>;
+	};
+
+	ts_int_sleep: ts-int-sleep-state {
+		pins = "gpio25";
+		function = "gpio";
+		bias-pull-down;
+		drive-strength = <2>;
+	};
+
+	ts2_irq: ts2-irq-state {
+		pins = "gpio39";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+	};
+
+	ts2_reset: ts2-reset-state {
+		pins = "gpio38";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-down;
+	};
+};
+
+&uart7 {
+	status = "okay";
+};
+
+/* AYANEO Controller serial interface */
+&uart11 {
+	status = "okay";
+};
+
+&uart14 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn7850-bt";
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+
+		max-speed = <3200000>;
+	};
+};
+
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+	vcc-supply = <&vreg_l17b_2p5>;
+	vcc-max-microamp = <1300000>;
+	vccq-supply = <&vreg_l1g_1p2>;
+	vccq-max-microamp = <1200000>;
+	vdd-hba-supply = <&vreg_l3g_1p2>;
+
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l1d_0p88>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3_hs {
+	remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+	vdd-supply = <&vreg_l1e_0p88>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&pm8550b_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_dp_qmpphy {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3f_0p88>;
+
+	status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+	remote-endpoint = <&redriver_ss_in>;
+};
+
+&xo_board {
+	clock-frequency = <76800000>;
+};

-- 
2.54.0

[PATCH v3 4/4] arm64: dts: qcom: sm8550: add UART11 node

[Alexandre Hamamdjian via B4 Relay]

From: Alexandre Hamamdjian <azkali.limited@gmail.com>

Add the QUPv3_2 SE3 High Speed UART (UART11) controller node and its
default pinctrl state to sm8550.dtsi, so boards can enable it through
&uart11 instead of open-coding the controller in their own dts.

Signed-off-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index a9c678fc9cb2..3e71701b18ff 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1084,6 +1084,24 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
 				status = "disabled";
 			};
 
+			uart11: serial@88c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x0088c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart11_default>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+				interconnect-names = "qup-core", "qup-config";
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				status = "disabled";
+			};
+
 			i2c12: i2c@890000 {
 				compatible = "qcom,geni-i2c";
 				reg = <0 0x00890000 0 0x4000>;
@@ -5102,6 +5120,14 @@ qup_uart7_default: qup-uart7-default-state {
 				bias-disable;
 			};
 
+			qup_uart11_default: qup-uart11-default-state {
+				/* TX, RX */
+				pins = "gpio70", "gpio71";
+				function = "qup2_se3";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
 			qup_uart14_default: qup-uart14-default-state {
 				/* TX, RX */
 				pins = "gpio78", "gpio79";

-- 
2.54.0

Re: [PATCH v3 1/4] dt-bindings: arm: qcom: document the Ayaneo Pocket DS

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The compatible string 'ayaneo,pocketds' violates Devicetree naming conventions by omitting a hyphen between words.
--

commit afa187f3006436f1b9cb60821ba5f70e1c3ff499
Author: Alexandre Hamamdjian <azkali.limited@gmail.com>

dt-bindings: arm: qcom: document the Ayaneo Pocket DS

This commit adds device tree binding documentation for the Ayaneo Pocket DS
gaming console, based on the Qualcomm QCS8550 platform.

> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 2741c07e9f416..f130a6b092b95 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
[ ... ]
> @@ -1107,6 +1107,12 @@ properties:
>            - const: qcom,qcs8550
>            - const: qcom,sm8550
>  
> +      - items:
> +          - enum:
> +              - ayaneo,pocketds

This isn't a bug, but there is a missing hyphen in the compatible string.

Should this be ayaneo,pocket-ds instead? The commit message refers to the
device as the Ayaneo Pocket DS, and the sibling entry for the Ayaneo Pocket S2
uses the hyphenated form ayaneo,pocket-s2.

A check of subsequent patches in the series confirms the string remains
uncorrected.

> +          - const: qcom,qcs8550
> +          - const: qcom,sm8550
> +

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260517-pocketds-v3-0-d5910c801756@gmail.com?part=1

Re: [PATCH v3 2/4] arm64: dts: qcom: sm8550: add labels for thermal zones

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incomplete implementation: missing labels for almost all CPU thermal zones despite commit message claims.
--

commit 32e1020122d8ab932064f6929e94b9d9f74c8a75
Author: Alexandre Hamamdjian <azkali.limited@gmail.com>

arm64: dts: qcom: sm8550: add labels for thermal zones

This commit adds labels to the cpuss, cpu, and gpuss thermal zones in
the sm8550 device tree. This is intended to allow board files to override
trip points and cooling maps using labels instead of full node paths.

> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 912525e9bca6f..a9c678fc9cb2e 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
[ ... ]
> @@ -6028,7 +6028,7 @@ cpu6_bottom_crit: cpu-critical {
>  			};
>  		};
>  
> -		cpu7-top-thermal {
> +		cpu7_top_thermal: cpu7-top-thermal {
>  			thermal-sensors = <&tsens0 13>;
>  
>  			trips {

The commit message states that labels are added for the cpu thermal zones,
but it looks like only cpu7-top-thermal was updated here.

Were the other CPU thermal zones in this file, such as cpu0-thermal,
cpu1-thermal, cpu3-bottom-thermal, and cpu7-bottom-thermal intentionally
left without labels, or did they get missed during the update?

If they are left out, it seems board files will not be able to extend those
remaining zones using the label override syntax.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260517-pocketds-v3-0-d5910c801756@gmail.com?part=2

Re: [PATCH v3 3/4] arm64: dts: qcom: add basic devicetree for Ayaneo Pocket DS gaming console

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 7 potential issue(s) to consider:
- [Critical] Unresolved references to non-existent nodes `&panel0_in` and `&panel1_in`.
- [High] DisplayPort is not correctly routed to the USB-C connector.
- [High] Missing PCI bridge properties in `pcie@0` root port node.
- [High] Missing `pinctrl-1` sleep state for the `pwm-fan`.
- [High] Thermal zones omit `cooling-maps` to bind the PWM fan and use incorrect trip types.
- [Medium] Empty `panel@0` node lacks a `compatible` string.
- [Low] Undocumented custom DT property `rocknix-u-boot-dt-id`.
--

commit d78e5e056b91e897429aec4c3dcd17b82685dc92
Author: Teguh Sobirin <teguh@sobir.in>

arm64: dts: qcom: add basic devicetree for Ayaneo Pocket DS gaming console

Add initial Device Tree for the Ayaneo Pocket DS gaming console based
on the Qualcomm QCS8550 platform.

> diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts
> new file mode 100644
> index 0000000000000..416399a4179b4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts
> @@ -0,0 +1,1883 @@
> +// SPDX-License-Identifier: BSD-3-Clause

[ ... ]

> +/ {
> +	model = "AYANEO Pocket DS";
> +	compatible = "ayaneo,pocketds", "qcom,qcs8550", "qcom,sm8550";
> +	rocknix-u-boot-dt-id = "u-boot-pocket-ds";

This isn't a bug, but is this a documented standard property?
Using custom properties may trigger dtbs_check warnings.

> +
> +	aliases {

[ ... ]

> +	pmic-glink {
> +		compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
> +
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
> +
> +		connector@0 {
> +			compatible = "usb-c-connector";
> +
> +			reg = <0>;
> +
> +			power-role = "dual";
> +			data-role = "dual";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +
> +					pmic_glink_hs_in: endpoint {
> +						remote-endpoint = <&usb_1_dwc3_hs>;
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +
> +					pmic_glink_ss_in: endpoint {
> +						remote-endpoint = <&redriver_ss_out>;
> +					};
> +				};
> +			};

The commit message mentions "DisplayPort is muxed over the USB-C connector".
Is the graph topology missing the DP Alt Mode port (port@2) for the
usb-c-connector?

> +		};
> +	};
> +
> +	pwm_fan: pwm-fan {
> +		compatible = "pwm-fan";
> +
> +		pinctrl-0 = <&fan_pwm_active>, <&fan_int>;
> +		pinctrl-names = "default", "sleep";

Does this missing pinctrl-1 property cause the pinctrl core to fail when
transitioning to sleep state?

> +
> +		fan-supply = <&vdd_fan_5v0>;

[ ... ]

> +&cpu7_top_thermal {
> +	polling-delay = <200>;
> +
> +	trips {
> +		cpu7_top_fan0: trip-point2 {
> +			temperature = <70000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};

Should active cooling devices like fans use type = "active" instead of
"passive"?

Also, are cooling-maps subnodes needed to bind these trip points to the
pwm_fan cooling device? Without them, the thermal framework might not
automatically engage the fan.

> +
> +		cpu7_top_fan1: trip-point3 {

[ ... ]

> +&mdss_dp0_out {
> +	remote-endpoint = <&panel0_in>;
> +
> +	data-lanes = <0 1 2 3>;
> +};

Are these endpoints defined anywhere? The commit message mentions display
panel support is deferred, but compiling this might result in a reference
to a non-existent node.

Also, should DisplayPort be routed to the USB QMP PHY's DisplayPort input
instead of a standalone panel, given it is muxed over the USB-C connector?

> +
> +&mdss_dsi0 {
> +	vdda-supply = <&vreg_l3e_1p2>;
> +
> +	status = "okay";
> +
> +	display_panel: panel@0 {
> +		reg = <0>;
> +
> +		pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>;
> +		pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>;
> +		pinctrl-names = "default", "sleep";
> +	};

Since display panel support is deferred, should this node be removed for now,
or at least include a compatible string to prevent dtbs_check errors?

> +};
> +
> +&mdss_dsi0_phy {

[ ... ]

> +&mdss_dsi1_out {
> +	remote-endpoint = <&panel1_in>;
> +	data-lanes = <0 1 2 3>;
> +};

Will this also cause a compilation failure due to referencing a non-existent
node, as panel support is deferred?

> +
> +&mdss_dsi1_phy {

[ ... ]

> +&pcie1 {
> +	wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
> +	perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
> +
> +	pinctrl-0 = <&pcie1_default_state>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +
> +	pcie@0 {
> +		/* Renesas μPD720201 PCIe USB3.0 HOST CONTROLLER */
> +		usb-controller@0 {
> +			compatible = "pci1912,0014";
> +			reg = <0x10000 0x0 0x0 0x0 0x0>;

Does the pcie@0 bridge node need #address-cells = <3>, #size-cells = <2>, and
a reg property so the child's reg can be properly parsed by the PCI subsystem?

> +
> +			avdd33-supply = <&upd720201_avdd33_reg>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260517-pocketds-v3-0-d5910c801756@gmail.com?part=3

Re: [PATCH v3 4/4] arm64: dts: qcom: sm8550: add UART11 node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Hardware/Device Tree inconsistency: The uart11 node references the wrong operating-points-v2 table.
- [Medium] Missing Pinctrl State: The `qup_uart11_cts_rts` state is omitted, forcing boards to open-code it.
- [Medium] Incorrect Pin Bias: The `qup_uart11_default` pinctrl state configures pins with `bias-disable` instead of `bias-pull-up`.
--

commit 3269a824736c1b0b41ba9f1674a29c444d6c2b01
Author: Alexandre Hamamdjian <azkali.limited@gmail.com>

arm64: dts: qcom: sm8550: add UART11 node

This commit adds the QUPv3_2 SE3 High Speed UART (UART11) controller node
and its default pinctrl state to the sm8550 device tree.

> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index a9c678fc9cb2e..3e71701b18ff0 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1084,6 +1084,24 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
>  				status = "disabled";
>  			};
>  
> +			uart11: serial@88c000 {
> +				compatible = "qcom,geni-uart";
> +				reg = <0 0x0088c000 0 0x4000>;
> +				clock-names = "se";
> +				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
> +				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&qup_uart11_default>;
> +				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
> +						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
> +						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> +						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
> +				interconnect-names = "qup-core", "qup-config";
> +				operating-points-v2 = <&qup_opp_table_100mhz>;

Is this the correct OPP table for this Serial Engine block?

The sibling spi11 and i2c11 nodes, which represent the same physical SE block
at the same address, use operating-points-v2 = <&qup_opp_table_120mhz>;.

A mismatch could lead to the UART mode voting for incorrect voltages or
failing to reach required frequencies.

> +				power-domains = <&rpmhpd RPMHPD_CX>;
> +				status = "disabled";
> +			};
> +

[ ... ]

> @@ -5102,6 +5120,14 @@ qup_uart7_default: qup-uart7-default-state {
>  				bias-disable;
>  			};
>  
> +			qup_uart11_default: qup-uart11-default-state {
> +				/* TX, RX */
> +				pins = "gpio70", "gpio71";
> +				function = "qup2_se3";
> +				drive-strength = <2>;
> +				bias-disable;

Should these pins be configured with a pull-up?

Other high-speed UARTs on this SoC (like qup_uart14_default) typically use
bias-pull-up for TX/RX lines. Using bias-disable deviates from the
established pattern for high-speed UARTs and could cause signal integrity
issues on boards lacking external pull-up resistors.

> +			};
> +

Could a qup_uart11_cts_rts state be added here as well?

The commit message states the goal is to prevent boards from open-coding the
controller configuration. Since high-speed UARTs often require hardware flow
control, boards that need it will still have to open-code the CTS/RTS pins
(gpio68 and gpio69) if the state is omitted from this file.

>  			qup_uart14_default: qup-uart14-default-state {
>  				/* TX, RX */
>  				pins = "gpio78", "gpio79";

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260517-pocketds-v3-0-d5910c801756@gmail.com?part=4

Re: [PATCH v3 3/4] arm64: dts: qcom: add basic devicetree for Ayaneo Pocket DS gaming console

[Dmitry Baryshkov]

On Sun, May 17, 2026 at 08:14:22PM +0700, Alexandre Hamamdjian via B4 Relay wrote:
> From: Teguh Sobirin <teguh@sobir.in>
> 
> Add initial Device Tree for the Ayaneo Pocket DS gaming console based
> on the Qualcomm QCS8550 platform.
> 
> The design is similar to a phone without the modem, the game control
> is handled via a standalone controller connected to a Renesas uPD720201
> PCIe USB 3.0 host controller. DisplayPort is muxed over the USB-C
> connector with all four lanes wired.
> 
> Display panel support will be added in a second time.
> 
> Co-developed-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
> Signed-off-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
> Signed-off-by: Teguh Sobirin <teguh@sobir.in>
> ---
>  arch/arm64/boot/dts/qcom/Makefile                  |    1 +
>  .../boot/dts/qcom/qcs8550-ayaneo-pocketds.dts      | 1883 ++++++++++++++++++++
>  2 files changed, 1884 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index cc42829f92eb..45859e977bc9 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -185,6 +185,7 @@ qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo
>  
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs8300-ride-el2.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-aim300-aiot.dtb
> +dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-ayaneo-pocketds.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride-r3.dtb
>  
> diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts
> new file mode 100644
> index 000000000000..416399a4179b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts
> @@ -0,0 +1,1883 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2025, Teguh Sobirin.
> + * Copyright (c) 2025, ROCKNIX (https://github.com/ROCKNIX)
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include "qcs8550.dtsi"
> +#include "pm8550.dtsi"
> +#include "pm8550b.dtsi"
> +#define PMK8550VE_SID 5
> +#include "pm8550ve.dtsi"
> +#include "pm8550vs.dtsi"
> +#include "pmk8550.dtsi"
> +
> +/delete-node/ &aop_image_mem;
> +/delete-node/ &aop_config_mem;
> +/delete-node/ &camera_mem;
> +/delete-node/ &ipa_fw_mem;
> +/delete-node/ &ipa_gsi_mem;
> +/delete-node/ &mpss_dsm_mem;
> +/delete-node/ &mpss_mem;
> +/delete-node/ &q6_mpss_dtb_mem;
> +/delete-node/ &cdsp_mem;
> +/delete-node/ &q6_cdsp_dtb_mem;
> +
> +/delete-node/ &remoteproc_mpss;
> +/delete-node/ &remoteproc_cdsp;

Why are you deleting them? Isn't status="disabled" enough? If it's about
the memory-region properties, it might be better to delete the
properties instead of deleting the nodes.

> +
> +&cpu7_top_thermal {
> +	polling-delay = <200>;
> +
> +	trips {
> +		cpu7_top_fan0: trip-point2 {
> +			temperature = <70000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};

How are these trip-points being used? If you want to control the fan, is
there a cooling device for them?

> +
> +		cpu7_top_fan1: trip-point3 {
> +			temperature = <75000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpu7_top_fan2: trip-point4 {
> +			temperature = <80000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +	};
> +};
> +
> +&cpuss0_thermal {
> +	polling-delay = <200>;
> +
> +	trips {
> +		cpuss0_fan0: trip-point2 {
> +			temperature = <40000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss0_fan1: trip-point3 {
> +			temperature = <50000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss0_fan2: trip-point4 {
> +			temperature = <60000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss0_fan3: trip-point5 {
> +			temperature = <65000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss0_fan4: trip-point6 {
> +			temperature = <70000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss0_fan5: trip-point7 {
> +			temperature = <75000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss0_fan6: trip-point8 {
> +			temperature = <80000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +	};
> +};
> +
> +&cpuss1_thermal {
> +	polling-delay = <200>;
> +
> +	trips {
> +		cpuss1_fan0: trip-point2 {
> +			temperature = <40000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss1_fan1: trip-point3 {
> +			temperature = <50000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss1_fan2: trip-point4 {
> +			temperature = <60000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss1_fan3: trip-point5 {
> +			temperature = <65000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss1_fan4: trip-point6 {
> +			temperature = <70000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss1_fan5: trip-point7 {
> +			temperature = <75000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss1_fan6: trip-point8 {
> +			temperature = <80000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +	};
> +};
> +
> +&cpuss2_thermal {
> +	polling-delay = <200>;
> +
> +	trips {
> +		cpuss2_fan0: trip-point2 {
> +			temperature = <40000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss2_fan1: trip-point3 {
> +			temperature = <50000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss2_fan2: trip-point4 {
> +			temperature = <60000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss2_fan3: trip-point5 {
> +			temperature = <65000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss2_fan4: trip-point6 {
> +			temperature = <70000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss2_fan5: trip-point7 {
> +			temperature = <75000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss2_fan6: trip-point8 {
> +			temperature = <80000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +	};
> +};
> +
> +&cpuss3_thermal {
> +	polling-delay = <200>;
> +
> +	trips {
> +		cpuss3_fan0: trip-point2 {
> +			temperature = <40000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss3_fan1: trip-point3 {
> +			temperature = <50000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss3_fan2: trip-point4 {
> +			temperature = <60000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss3_fan3: trip-point5 {
> +			temperature = <65000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss3_fan4: trip-point6 {
> +			temperature = <70000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss3_fan5: trip-point7 {
> +			temperature = <75000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +
> +		cpuss3_fan6: trip-point8 {
> +			temperature = <80000>;
> +			hysteresis = <3000>;
> +			type = "passive";
> +		};
> +	};
> +};
> +
> +&gpi_dma1 {
> +	status = "okay";
> +};
> +
> +&gpi_dma2 {
> +	status = "okay";
> +};
> +
> +&gpu {
> +	status = "okay";
> +};
> +
> +&gpu_opp_table {
> +	opp-719000000 {
> +		opp-hz = /bits/ 64 <719000000>;
> +		opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> +		opp-peak-kBps = <10687500>;
> +		qcom,opp-acd-level = <0x882e5ffd>;
> +	};

We probably need to get speed bins done...

> +
> +	opp-746000000 {
> +		opp-hz = /bits/ 64 <746000000>;
> +		opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +		opp-peak-kBps = <10687500>;
> +		qcom,opp-acd-level = <0x882e5ffd>;
> +	};
> +
> +	opp-794000000 {
> +		opp-hz = /bits/ 64 <794000000>;
> +		opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +		opp-peak-kBps = <14398438>;
> +		qcom,opp-acd-level = <0xa82d5ffd>;
> +	};
> +
> +	opp-827000000 {
> +		opp-hz = /bits/ 64 <827000000>;
> +		opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +		opp-peak-kBps = <16500000>;
> +		qcom,opp-acd-level = <0xa82d5ffd>;
> +	};
> +
> +	opp-860000000 {
> +		opp-hz = /bits/ 64 <860000000>;
> +		opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +		opp-peak-kBps = <16500000>;
> +		qcom,opp-acd-level = <0x882d5ffd>;
> +	};
> +
> +	opp-1000000000 {
> +		opp-hz = /bits/ 64 <1000000000>;
> +		opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
> +		opp-peak-kBps = <16500000>;
> +		qcom,opp-acd-level = <0x882d5ffd>;
> +	};
> +};
> +

[...]

> +
> +&remoteproc_adsp {
> +	firmware-name = "qcom/sm8550/ayaneo/adsp.mdt",
> +			"qcom/sm8550/ayaneo/adsp_dtb.mdt";

.mbn, please. Even if the downstream uses .mdt. Either pil-squash them
or just symlink, the code will handle it anyway.


> +
> +	status = "okay";
> +};
> +

-- 
With best wishes
Dmitry

Re: [PATCH v3 2/4] arm64: dts: qcom: sm8550: add labels for thermal zones

[Dmitry Baryshkov]

On Sun, May 17, 2026 at 08:14:21PM +0700, Alexandre Hamamdjian via B4 Relay wrote:
> From: Alexandre Hamamdjian <azkali.limited@gmail.com>
> 
> Add labels for the cpuss, cpu and gpuss thermal zones so board files
> can extend them with trip points and cooling maps through the &label
> override syntax, instead of redeclaring the zones by path.
> 
> Signed-off-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 +++++++++++++-------------
>  1 file changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 912525e9bca6..a9c678fc9cb2 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -5764,7 +5764,7 @@ reset-mon-config {
>  			};
>  		};
>  
> -		cpuss0-thermal {
> +		cpuss0_thermal: cpuss0-thermal {

thermal_cpuss0, so that all thermal nodes are grouped in .dts file.

>  			thermal-sensors = <&tsens0 1>;
>  
>  			trips {

-- 
With best wishes
Dmitry

Re: [PATCH v3 4/4] arm64: dts: qcom: sm8550: add UART11 node

[Dmitry Baryshkov]

On Sun, May 17, 2026 at 08:14:23PM +0700, Alexandre Hamamdjian via B4 Relay wrote:
> From: Alexandre Hamamdjian <azkali.limited@gmail.com>
> 
> Add the QUPv3_2 SE3 High Speed UART (UART11) controller node and its
> default pinctrl state to sm8550.dtsi, so boards can enable it through
> &uart11 instead of open-coding the controller in their own dts.
> 
> Signed-off-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 

This should come before the previous patch, otherwise building of the
kernel will be broken between those two.

-- 
With best wishes
Dmitry