[PATCH] arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate

[PATCH] arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz.

The CMN PLL driver did not account for the ref clock divider which is 2
for IPQ5018. Therefore, the computed rate was twice the actual output.

With the driver now accounting for the CMN PLL reference clock
divider (commit: 88c543fff756), set the correct reference clock rate.

Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node")

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 6f8004a22a1f..f6cf2cca44eb 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -256,7 +256,7 @@ cmn_pll: clock-controller@9b000 {
 				      "sys";
 			#clock-cells = <1>;
 			assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;
-			assigned-clock-rates-u64 = /bits/ 64 <9600000000>;
+			assigned-clock-rates-u64 = /bits/ 64 <4800000000>;
 		};
 
 		qfprom: qfprom@a0000 {

---
base-commit: 80dd246accce631c328ea43294e53b2b2dd2aa32
change-id: 20260519-ipq5018-cmn-pll-rate-fix-388a379bfe10

Best regards,
--  
George Moussalem <george.moussalem@outlook.com>

Re: [PATCH] arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The commit message incorrectly refers to 4.8 GHz as the 'CMN PLL reference clock rate'.
--

commit 4cb93e818beccfa0a5e9ea288ba3c76a08ea178c
Author: George Moussalem <george.moussalem@outlook.com>

arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate

This commit corrects the CMN PLL clock rate configuration for the IPQ5018
in the device tree to 4.8 GHz, aligning it with the driver's updated clock
divider math.

> arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate
>
> The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz.
>
> The CMN PLL driver did not account for the ref clock divider which is 2
> for IPQ5018. Therefore, the computed rate was twice the actual output.

This isn't a bug in the device tree changes, but does the commit message
conflate the output rate with the input reference clock rate?

In PLL terminology, the input reference clock for the IPQ5018 CMN PLL is
96 MHz. The 4.8 GHz value being configured via assigned-clock-rates-u64
is the output (or VCO) rate of the CMN PLL, rather than the reference
clock rate.

Could the subject and commit message be updated to clarify that 4.8 GHz
is the output rate?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260519-ipq5018-cmn-pll-rate-fix-v1-1-3c83a173c27f@outlook.com?part=1