Re: [PATCH v3 RESEND 2/5] arm64: dts: qcom: Add device tree for Nord SoC series

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The UFS host controller node is missing the required `reg` property.
- [Medium] PSCI CPU power domains incorrectly reference an `arm,idle-state` as a `domain-idle-state`.
--

commit 5cfe2bd3985bb2e72ebd4055f3c4ed028cffb283
Author: Shawn Guo <shengchao.guo@oss.qualcomm.com>
arm64: dts: qcom: Add device tree for Nord SoC series

This commit introduces the base device tree include for the Nord SoC series,
defining core hardware components like CPUs, GIC, GPIO, thermal sensors, 
SMMUs, UFS, and power management domains.

> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> new file mode 100644
> index 0000000000000..954a2b23a4fa3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> @@ -0,0 +1,4513 @@

[ ... ]

> +		idle-states {
> +			entry-method = "psci";
> +
> +			core_off_c4: cluster-c4 {
> +				compatible = "arm,idle-state";
> +				idle-state-name = "retention";
> +				entry-latency-us = <93>;
> +				exit-latency-us = <129>;
> +				min-residency-us = <560>;
> +				arm,psci-suspend-param = <0x00000003>;
> +			};
> +		};

[ ... ]

> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +
> +		cpu0_pd: power-domain-cpu0 {
> +			#power-domain-cells = <0>;
> +			power-domains = <&cluster0_pd>;
> +			domain-idle-states = <&core_off_c4>;
> +		};

[Severity: Medium]
Will this successfully parse the domain idle state? 

The generic power domain framework (genpd_parse_state_node) expects nodes
referenced by domain-idle-states to have compatible = "domain-idle-state". 

Since core_off_c4 uses "arm,idle-state", this might get rejected during
genpd initialization and prevent CPU retention/power-down states from
working in OSI mode.

[ ... ]

> +		ufs_mem_hc: ufshc@1d44000 {
> +			compatible = "qcom,nord-ufshc",
> +				     "qcom,ufshc",
> +				     "jedec,ufs-2.0";
> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> +			lanes-per-direction = <2>;
> +			iommus = <&apps_smmu_0 0x14c0 0x0>;
> +			dma-coherent;
> +			msi-parent = <&gic_its 0x14c0>;
> +		};

[Severity: High]
Is this node missing a reg property to map its MMIO base address and size? 

Without it, schema validation may fail, and the UFS driver won't be able
to map its hardware registers. This will cause the probe to fail, which could
prevent the system from mounting the root filesystem.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260526051300.1669201-1-shengchao.guo@oss.qualcomm.com?part=2