Re: [PATCH v3 RESEND 5/5] arm64: dts: qcom: Add device tree for SA8797P Ride board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Thermal zones lack a critical trip point and use passive trips without cooling maps.
- [Medium] UART nodes are enabled without pinctrl configurations.
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commit 2a7d549a569e32271efac6bc43150f202ba201ce
Author: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>

arm64: dts: qcom: Add device tree for SA8797P Ride board

This commit adds the initial device tree for the Qualcomm SA8797P Ride
reference board. It configures the primary and secondary serial consoles,
enables UFS storage support, and defines multiple thermal zones.

> diff --git a/arch/arm64/boot/dts/qcom/sa8797p-ride.dts b/arch/arm64/boot/dts/qcom/sa8797p-ride.dts
> new file mode 100644
> index 0000000000000..d429de313f248
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sa8797p-ride.dts

[ ... ]

> +&thermal_zones {
> +	pm_kobra_thermal: pm-a-die-thermal {
> +		polling-delay-passive = <100>;
> +		polling-delay = <0>;
> +		thermal-sensors = <&scmi23_sensor 3>;
> +
> +		trips {
> +			trip0 {
> +				temperature = <115000>;
> +				hysteresis = <5000>;
> +				type = "passive";
> +			};
> +
> +			trip1 {
> +				temperature = <135000>;
> +				hysteresis = <5000>;
> +				type = "passive";
> +			};
> +		};
> +	};

[Severity: High]
Are we missing cooling maps and critical trip points in these thermal zones?

These passive trips set high temperature limits (up to 135C for PMIC and 125C
for UFS) but lack a cooling-maps section, meaning the thermal core cannot
take action to throttle a cooling device.

Furthermore, by omitting a type = "critical" trip point, the kernel is
prevented from performing an emergency orderly shutdown when excessive
temperatures are reached. Does this leave the hardware unprotected against
thermal runaway?

[ ... ]

> +&uart4 {
> +	status = "okay";
> +};
> +
> +&uart15 {
> +	status = "okay";
> +};

[Severity: Medium]
Do these UART nodes need pinctrl configurations?

They are enabled without defining or assigning any pinctrl properties
(such as pinctrl-0 and pinctrl-names). On Qualcomm platforms, explicit pin
multiplexing configurations are usually required to map UART TX and RX
lines to physical pins.

Without these properties, will the UARTs fail to route data and remain
non-functional unless they rely purely on implicit bootloader configurations?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260526051300.1669201-1-shengchao.guo@oss.qualcomm.com?part=5