[PATCH 1/3] arm64: dts: renesas: r9a09g077: Add xSPI nodes

[PATCH 1/3] arm64: dts: renesas: r9a09g077: Add xSPI nodes

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add xSPI (Expanded SPI) device nodes to the RZ/T2H (R9A09G077) SoC DTSI.
The RZ/T2H integrates two xSPI interfaces.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 38 ++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 3761551c9647..a5b570ae82c0 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -1006,6 +1006,44 @@ mii_conv3: mii-conv@3 {
 			};
 		};
 
+		xspi0: spi@801c0000 {
+			compatible = "renesas,r9a09g077-xspi", "renesas,r9a09g047-xspi";
+			reg = <0 0x801c0000 0 0x1000>,
+			      <0 0x40000000 0 0x10000000>;
+			reg-names = "regs", "dirmap";
+			interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pulse", "err_pulse";
+			clocks = <&cpg CPG_MOD 4>,
+				 <&cpg CPG_CORE R9A09G077_XSPI_CLK0>;
+			clock-names = "ahb", "spi";
+			resets = <&cpg 0x4>;
+			reset-names = "hresetn";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		xspi1: spi@801c1000 {
+			compatible = "renesas,r9a09g077-xspi", "renesas,r9a09g047-xspi";
+			reg = <0 0x801c1000 0 0x1000>,
+			      <0 0x50000000 0 0x10000000>;
+			reg-names = "regs", "dirmap";
+			interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pulse", "err_pulse";
+			clocks = <&cpg CPG_MOD 5>,
+				 <&cpg CPG_CORE R9A09G077_XSPI_CLK1>;
+			clock-names = "ahb", "spi";
+			resets = <&cpg 5>;
+			reset-names = "hresetn";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		cpg: clock-controller@80280000 {
 			compatible = "renesas,r9a09g077-cpg-mssr";
 			reg = <0 0x80280000 0 0x10000>,
-- 
2.54.0

[PATCH 0/3] Add xSPI support for RZT2H, RZN2H SoCs

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi all,

This patch series adds support for the xSPI controller on the RZT2H
and RZN2H SoCs and enables it on the RZT2H-N2H-EVK board.

Cheers,
Prabhakar

Lad Prabhakar (3):
  arm64: dts: renesas: r9a09g077: Add xSPI nodes
  arm64: dts: renesas: r9a09g087: Add xSPI nodes
  arm64: dts: renesas: rzt2h-n2h-evk: Enable xSPI nodes

 arch/arm64/boot/dts/renesas/r9a09g077.dtsi    |  38 +++++
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi    |  38 +++++
 .../dts/renesas/rzt2h-n2h-evk-common.dtsi     | 139 ++++++++++++++++++
 3 files changed, 215 insertions(+)

-- 
2.54.0

[PATCH 1/3] arm64: dts: renesas: r9a09g077: Add xSPI nodes

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add device tree nodes for the two xSPI (Expanded SPI) controllers
integrated into the RZ/T2H (R9A09G077) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 38 ++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index fe5d206d4def..1b194361fef8 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -1006,6 +1006,44 @@ mii_conv3: mii-conv@3 {
 			};
 		};
 
+		xspi0: spi@801c0000 {
+			compatible = "renesas,r9a09g077-xspi", "renesas,r9a09g047-xspi";
+			reg = <0 0x801c0000 0 0x1000>,
+			      <0 0x40000000 0 0x10000000>;
+			reg-names = "regs", "dirmap";
+			interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pulse", "err_pulse";
+			clocks = <&cpg CPG_MOD 4>,
+				 <&cpg CPG_CORE R9A09G077_XSPI_CLK0>;
+			clock-names = "ahb", "spi";
+			resets = <&cpg 0x4>;
+			reset-names = "hresetn";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		xspi1: spi@801c1000 {
+			compatible = "renesas,r9a09g077-xspi", "renesas,r9a09g047-xspi";
+			reg = <0 0x801c1000 0 0x1000>,
+			      <0 0x50000000 0 0x10000000>;
+			reg-names = "regs", "dirmap";
+			interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pulse", "err_pulse";
+			clocks = <&cpg CPG_MOD 5>,
+				 <&cpg CPG_CORE R9A09G077_XSPI_CLK1>;
+			clock-names = "ahb", "spi";
+			resets = <&cpg 5>;
+			reset-names = "hresetn";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		cpg: clock-controller@80280000 {
 			compatible = "renesas,r9a09g077-cpg-mssr";
 			reg = <0 0x80280000 0 0x10000>,
-- 
2.54.0

[PATCH 2/3] arm64: dts: renesas: r9a09g087: Add xSPI nodes

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add device tree nodes for the two xSPI (Expanded SPI) controllers
integrated into the RZ/N2H (R9A09G087) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 38 ++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index c64b532f3d23..7a23112ed696 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -1009,6 +1009,44 @@ mii_conv3: mii-conv@3 {
 			};
 		};
 
+		xspi0: spi@801c0000 {
+			compatible = "renesas,r9a09g087-xspi", "renesas,r9a09g047-xspi";
+			reg = <0 0x801c0000 0 0x1000>,
+			      <0 0x40000000 0 0x10000000>;
+			reg-names = "regs", "dirmap";
+			interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pulse", "err_pulse";
+			clocks = <&cpg CPG_MOD 4>,
+				 <&cpg CPG_CORE R9A09G087_XSPI_CLK0>;
+			clock-names = "ahb", "spi";
+			resets = <&cpg 0x4>;
+			reset-names = "hresetn";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		xspi1: spi@801c1000 {
+			compatible = "renesas,r9a09g087-xspi", "renesas,r9a09g047-xspi";
+			reg = <0 0x801c1000 0 0x1000>,
+			      <0 0x50000000 0 0x10000000>;
+			reg-names = "regs", "dirmap";
+			interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pulse", "err_pulse";
+			clocks = <&cpg CPG_MOD 5>,
+				 <&cpg CPG_CORE R9A09G087_XSPI_CLK1>;
+			clock-names = "ahb", "spi";
+			resets = <&cpg 5>;
+			reset-names = "hresetn";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		cpg: clock-controller@80280000 {
 			compatible = "renesas,r9a09g087-cpg-mssr";
 			reg = <0 0x80280000 0 0x10000>,
-- 
2.54.0

[PATCH 3/3] arm64: dts: renesas: rzt2h-n2h-evk: Enable xSPI nodes

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable the xSPI0 and xSPI1 controllers on the RZ/T2H N2H EVK board.

Configure the xSPI0 controller interface to 1-bit (x1) mode, even though
the connected MX25LW51245 octal flash device supports octal mode. Add a
corresponding inline hardware comment detailing this restriction;
operating in octal mode causes the BootROM to fail loading the first-stage
bootloader following a Watchdog Timer (WDT) reset.

Configure the xSPI1 controller interface connected to the AT25SF128A
flash device for 4-bit (x4) mode to utilize all available data lines.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../dts/renesas/rzt2h-n2h-evk-common.dtsi     | 139 ++++++++++++++++++
 1 file changed, 139 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index f87c2492f414..fff63d08e3a3 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -5,6 +5,7 @@
  * Copyright (C) 2025 Renesas Electronics Corp.
  */
 
+#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/net/mscc-phy-vsc8531.h>
@@ -20,6 +21,8 @@ aliases {
 		mmc0 = &sdhi0;
 		mmc1 = &sdhi1;
 		serial0 = &sci0;
+		spi0 = &xspi0;
+		spi1 = &xspi1;
 	};
 
 	chosen {
@@ -331,6 +334,59 @@ ctrl-pins {
 				 <RZT2H_PORT_PINMUX(17, 4, 0x29)>; /* SD1_CD */
 		};
 	};
+
+	xspi0_pins: xspi0-group {
+		clk-pins {
+			pinmux = <RZT2H_PORT_PINMUX(5, 1, 0x1c)>, /* XSPI0_CKP */
+				 <RZT2H_PORT_PINMUX(5, 2, 0x1c)>; /* XSPI0_CKN */
+			input-schmitt-disable;
+			slew-rate = <1>;
+			drive-strength-microamp = <9000>;
+		};
+
+		data-pins {
+			pinmux = <RZT2H_PORT_PINMUX(5, 6, 0x1c)>, /* XSPI0_IO0 */
+				 <RZT2H_PORT_PINMUX(5, 7, 0x1c)>, /* XSPI0_IO1 */
+				 <RZT2H_PORT_PINMUX(6, 0, 0x1c)>, /* XSPI0_IO2 */
+				 <RZT2H_PORT_PINMUX(6, 1, 0x1c)>, /* XSPI0_IO3 */
+				 <RZT2H_PORT_PINMUX(6, 2, 0x1c)>, /* XSPI0_IO4 */
+				 <RZT2H_PORT_PINMUX(6, 3, 0x1c)>, /* XSPI0_IO5 */
+				 <RZT2H_PORT_PINMUX(6, 4, 0x1c)>, /* XSPI0_IO6 */
+				 <RZT2H_PORT_PINMUX(6, 5, 0x1c)>; /* XSPI0_IO7 */
+			input-schmitt-disable;
+			slew-rate = <1>;
+			drive-strength-microamp = <9000>;
+		};
+
+		ctrl-pins {
+			pinmux = <RZT2H_PORT_PINMUX(5, 3, 0x1c)>, /* XSPI0_CS0 */
+				 <RZT2H_PORT_PINMUX(6, 6, 0x1c)>, /* XSPI0_RESET0 */
+				 <RZT2H_PORT_PINMUX(5, 5, 0x1c)>; /* XSPI0_DS */
+			input-schmitt-disable;
+			slew-rate = <1>;
+			drive-strength-microamp = <9000>;
+		};
+	};
+
+	xspi1_pins: xspi1-group {
+		ctrl-pins {
+			pinmux = <RZT2H_PORT_PINMUX(1, 0, 0x1c)>, /* XSPI1_CKP */
+				 <RZT2H_PORT_PINMUX(1, 1, 0x1c)>; /* XSPI1_CS0 */
+			input-schmitt-enable;
+			slew-rate = <1>;
+			drive-strength-microamp = <9000>;
+		};
+
+		data-pins {
+			pinmux = <RZT2H_PORT_PINMUX(1, 4, 0x1c)>, /* XSPI1_IO0 */
+				 <RZT2H_PORT_PINMUX(1, 5, 0x1c)>, /* XSPI1_IO1 */
+				 <RZT2H_PORT_PINMUX(1, 6, 0x1c)>, /* XSPI1_IO2 */
+				 <RZT2H_PORT_PINMUX(1, 7, 0x1c)>; /* XSPI1_IO3 */
+			input-schmitt-enable;
+			slew-rate = <1>;
+			drive-strength-microamp = <9000>;
+		};
+	};
 };
 
 &sci0 {
@@ -395,3 +451,86 @@ &wdt2 {
 	timeout-sec = <60>;
 };
 
+&xspi0 {
+	pinctrl-0 = <&xspi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	assigned-clocks = <&cpg CPG_CORE R9A09G077_XSPI_CLK0>;
+	assigned-clock-rates = <50000000>;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		m25p,fast-read;
+		/*
+		 * Configure for 1-bit mode to prevent the BootROM from failing
+		 * to load the first-stage bootloader following a watchdog reset.
+		 */
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		vcc-supply = <&reg_3p3v>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2-0";
+				reg = <0x00000000 0x00060000>;
+				read-only;
+			};
+
+			partition@1fb000 {
+				label = "fip-0";
+				reg = <0x00060000 0x007a0000>;
+				read-only;
+			};
+
+			partition@300000 {
+				label = "user-0";
+				reg = <0x800000 0x003800000>;
+			};
+		};
+	};
+};
+
+&xspi1 {
+	pinctrl-0 = <&xspi1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	assigned-clocks = <&cpg CPG_CORE R9A09G077_XSPI_CLK1>;
+	assigned-clock-rates = <50000000>;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		m25p,fast-read;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		vcc-supply = <&reg_3p3v>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2-1";
+				reg = <0x00000000 0x00060000>;
+			};
+
+			partition@60000 {
+				label = "fip-1";
+				reg = <0x00060000 0x007a0000>;
+			};
+
+			partition@800000 {
+				label = "user-1";
+				reg = <0x800000 0x800000>;
+			};
+		};
+	};
+};
-- 
2.54.0

Re: [PATCH 1/3] arm64: dts: renesas: r9a09g077: Add xSPI nodes

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The xSPI nodes provide fewer clocks and resets than strictly required by the fallback compatible string 'renesas,r9a09g047-xspi', causing dtbs_check validation failures and breaking the hardware compatibility contract.
- [Low] Inconsistent numeric formatting in the 'resets' property between xspi0 and xspi1.
--

commit 5e178072e3e48c6e7ba03bbaf8ea699cb37031c4
Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

arm64: dts: renesas: r9a09g077: Add xSPI nodes

This commit adds device tree nodes for the two xSPI (Expanded SPI)
controllers integrated into the RZ/T2H (R9A09G077) SoC.

> diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
[ ... ]
> +		xspi0: spi@801c0000 {
> +			compatible = "renesas,r9a09g077-xspi", "renesas,r9a09g047-xspi";
> +			reg = <0 0x801c0000 0 0x1000>,
> +			      <0 0x40000000 0 0x10000000>;
> +			reg-names = "regs", "dirmap";
> +			interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "pulse", "err_pulse";
> +			clocks = <&cpg CPG_MOD 4>,
> +				 <&cpg CPG_CORE R9A09G077_XSPI_CLK0>;
> +			clock-names = "ahb", "spi";
> +			resets = <&cpg 0x4>;

[Severity: Medium]
Will this trigger validation errors during make dtbs_check?

The fallback compatible string renesas,r9a09g047-xspi typically requires
exactly 4 clocks (ahb, axi, spi, spix2) and 2 resets (hresetn, aresetn) in
its bindings schema. Since these nodes only provide 2 clocks and 1 reset,
does this break the hardware compatibility contract expected by older
software?

Should there be a corresponding dt-bindings schema update to document the
new compatible string and relax these resource constraints?

> +			reset-names = "hresetn";
> +			power-domains = <&cpg>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		xspi1: spi@801c1000 {
[ ... ]
> +			clock-names = "ahb", "spi";
> +			resets = <&cpg 5>;

[Severity: Low]
This isn't a bug, but the reset index is formatted as a decimal here,
whereas the xspi0 node above uses hexadecimal (0x4). Would it be better
to use consistent numeric formatting across adjacent, identical hardware
block definitions?

> +			reset-names = "hresetn";
> +			power-domains = <&cpg>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260526204045.3481604-1-prabhakar.mahadev-lad.rj@bp.renesas.com?part=1

Re: [PATCH 2/3] arm64: dts: renesas: r9a09g087: Add xSPI nodes

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The xSPI nodes provide incomplete clock and reset properties for the fallback compatible string (`renesas,r9a09g047-xspi`), which will cause schema validation errors.
- [Low] Mixed decimal and hexadecimal notation for reset indices in sibling nodes.
--

commit 7421051c9fdf7ba19830d3741837bab97e76f110
Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

arm64: dts: renesas: r9a09g087: Add xSPI nodes

Add device tree nodes for the two xSPI (Expanded SPI) controllers
integrated into the RZ/N2H (R9A09G087) SoC.

> diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> index f697e9698ed39..e63a6b74d90b0 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi

[ ... ]

> @@ -1009,6 +1009,44 @@ mii_conv3: mii-conv@3 {
>  			};
>  		};
>  
> +		xspi0: spi@801c0000 {
> +			compatible = "renesas,r9a09g087-xspi", "renesas,r9a09g047-xspi";
> +			reg = <0 0x801c0000 0 0x1000>,
> +			      <0 0x40000000 0 0x10000000>;
> +			reg-names = "regs", "dirmap";
> +			interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "pulse", "err_pulse";
> +			clocks = <&cpg CPG_MOD 4>,
> +				 <&cpg CPG_CORE R9A09G087_XSPI_CLK0>;
> +			clock-names = "ahb", "spi";
> +			resets = <&cpg 0x4>;
> +			reset-names = "hresetn";

[Severity: Medium]
Will this node pass schema validation for the r9a09g047-xspi fallback?

The YAML binding schema for renesas,r9a09g047-xspi requires four clocks (ahb,
axi, spi, spix2) and two resets (hresetn, aresetn), but only two clocks and
one reset are provided here.

Because device tree schema lists match positionally by index, providing spi
at index 1 of clock-names violates the schema that expects axi at that
position, which will cause dtbs_check to fail.

Additionally, should the primary compatible string renesas,r9a09g087-xspi be
documented in the bindings before adding it here?

> +			power-domains = <&cpg>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		xspi1: spi@801c1000 {
> +			compatible = "renesas,r9a09g087-xspi", "renesas,r9a09g047-xspi";
> +			reg = <0 0x801c1000 0 0x1000>,
> +			      <0 0x50000000 0 0x10000000>;
> +			reg-names = "regs", "dirmap";
> +			interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "pulse", "err_pulse";
> +			clocks = <&cpg CPG_MOD 5>,
> +				 <&cpg CPG_CORE R9A09G087_XSPI_CLK1>;
> +			clock-names = "ahb", "spi";
> +			resets = <&cpg 5>;

[Severity: Low]
This isn't a bug, but is it intentional to use decimal notation here
compared to hexadecimal notation for the reset index in the xspi0 node?

The xspi0 node uses <&cpg 0x4> while xspi1 uses <&cpg 5>. Should these use
a consistent notation base since they are identical adjacent hardware blocks?

> +			reset-names = "hresetn";
> +			power-domains = <&cpg>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260526204045.3481604-1-prabhakar.mahadev-lad.rj@bp.renesas.com?part=2

Re: [PATCH 3/3] arm64: dts: renesas: rzt2h-n2h-evk: Enable xSPI nodes

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The 'spi-max-frequency' property is missing from the SPI NOR flash peripheral nodes (flash@0) under both xspi0 and xspi1.
- [Low] The unit addresses in the partition node names for xspi0 do not match their corresponding 'reg' base addresses.
--

commit 61aa7aa9a0a6654d6fbf30169801908b8247d8cd
Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

arm64: dts: renesas: rzt2h-n2h-evk: Enable xSPI nodes

Enable the xSPI0 and xSPI1 controllers on the RZ/T2H N2H EVK board.

> diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> index f87c2492f414a..fff63d08e3a3c 100644
> --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi

[ ... ]

> @@ -395,3 +451,86 @@ &wdt2 {
>  	timeout-sec = <60>;
>  };
>  
> +&xspi0 {
> +	pinctrl-0 = <&xspi0_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +
> +	assigned-clocks = <&cpg CPG_CORE R9A09G077_XSPI_CLK0>;
> +	assigned-clock-rates = <50000000>;
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;

[Severity: Medium]
Should there be a 'spi-max-frequency' property specified here?

Standard SPI peripheral Device Tree bindings require the 'spi-max-frequency'
property on child nodes to explicitly specify the maximum SPI clock speed
the device can tolerate. Omitting this property will cause 'dtbs_check'
warnings.

Furthermore, without it, the SPI core framework initializes the device's
max_speed_hz to 0, forcing reliance on the controller's internal clock
fallback behavior.

> +		m25p,fast-read;

[ ... ]

> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "bl2-0";
> +				reg = <0x00000000 0x00060000>;
> +				read-only;
> +			};
> +
> +			partition@1fb000 {
> +				label = "fip-0";
> +				reg = <0x00060000 0x007a0000>;

[Severity: Low]
Does this unit address match the first address specified in its 'reg' property?

The Device Tree specification requires the unit-address (the part after '@') in
a node name to exactly match the first address specified in its 'reg'
property. Here, 'partition@1fb000' defines its base address as '0x00060000'.

This mismatch will trigger 'unit_address_vs_reg' warnings during device tree
compilation.

> +				read-only;
> +			};
> +
> +			partition@300000 {
> +				label = "user-0";
> +				reg = <0x800000 0x003800000>;

[Severity: Low]
Does this unit address match the first address specified in its 'reg' property?

The Device Tree specification requires the unit-address (the part after '@') in
a node name to exactly match the first address specified in its 'reg'
property. Here, 'partition@300000' defines its base address as '0x800000'.

This mismatch will trigger 'unit_address_vs_reg' warnings during device tree
compilation.

Additionally, does the size value '0x003800000' contain an extraneous leading
zero?

> +			};
> +		};
> +	};
> +};
> +
> +&xspi1 {
> +	pinctrl-0 = <&xspi1_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +
> +	assigned-clocks = <&cpg CPG_CORE R9A09G077_XSPI_CLK1>;
> +	assigned-clock-rates = <50000000>;
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;

[Severity: Medium]
Should there be a 'spi-max-frequency' property specified here?

Standard SPI peripheral Device Tree bindings require the 'spi-max-frequency'
property on child nodes to explicitly specify the maximum SPI clock speed
the device can tolerate. Omitting this property will cause 'dtbs_check'
warnings.

Furthermore, without it, the SPI core framework initializes the device's
max_speed_hz to 0, forcing reliance on the controller's internal clock
fallback behavior.

> +		m25p,fast-read;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260526204045.3481604-1-prabhakar.mahadev-lad.rj@bp.renesas.com?part=3

Re: [PATCH 1/3] arm64: dts: renesas: r9a09g077: Add xSPI nodes

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, 5 May 2026 at 14:02, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add xSPI (Expanded SPI) device nodes to the RZ/T2H (R9A09G077) SoC DTSI.
> The RZ/T2H integrates two xSPI interfaces.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> @@ -1006,6 +1006,44 @@ mii_conv3: mii-conv@3 {
>                         };
>                 };
>
> +               xspi0: spi@801c0000 {
> +                       compatible = "renesas,r9a09g077-xspi", "renesas,r9a09g047-xspi";
> +                       reg = <0 0x801c0000 0 0x1000>,
> +                             <0 0x40000000 0 0x10000000>;
> +                       reg-names = "regs", "dirmap";
> +                       interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "pulse", "err_pulse";
> +                       clocks = <&cpg CPG_MOD 4>,
> +                                <&cpg CPG_CORE R9A09G077_XSPI_CLK0>;
> +                       clock-names = "ahb", "spi";
> +                       resets = <&cpg 0x4>;

4

> +                       reset-names = "hresetn";
> +                       power-domains = <&cpg>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.2 with the above fixed.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/3] arm64: dts: renesas: r9a09g077: Add xSPI nodes

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Wed, May 27, 2026 at 11:13 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 5 May 2026 at 14:02, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add xSPI (Expanded SPI) device nodes to the RZ/T2H (R9A09G077) SoC DTSI.
> > The RZ/T2H integrates two xSPI interfaces.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > @@ -1006,6 +1006,44 @@ mii_conv3: mii-conv@3 {
> >                         };
> >                 };
> >
> > +               xspi0: spi@801c0000 {
> > +                       compatible = "renesas,r9a09g077-xspi", "renesas,r9a09g047-xspi";
> > +                       reg = <0 0x801c0000 0 0x1000>,
> > +                             <0 0x40000000 0 0x10000000>;
> > +                       reg-names = "regs", "dirmap";
> > +                       interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>;
> > +                       interrupt-names = "pulse", "err_pulse";
> > +                       clocks = <&cpg CPG_MOD 4>,
> > +                                <&cpg CPG_CORE R9A09G077_XSPI_CLK0>;
> > +                       clock-names = "ahb", "spi";
> > +                       resets = <&cpg 0x4>;
>
> 4
>
Ouch.
> > +                       reset-names = "hresetn";
> > +                       power-domains = <&cpg>;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       status = "disabled";
> > +               };
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-devel for v7.2 with the above fixed.
>
Thank you for taking care of this (and also patch 2/3).

Cheers,
Prabhakar

> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
>