From: sashiko-bot@kernel.org
To: "Santhosh Kumar K" <s-k6@ti.com>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 02/13] spi: dt-bindings: cdns,qspi-nor: add PHY tuning pattern partition property
Date: Wed, 27 May 2026 18:11:23 +0000 [thread overview]
Message-ID: <20260527181124.0DAA01F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260527175527.2247679-3-s-k6@ti.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `cdns,phy-pattern-partition` property references a software MTD partition via phandle, mixing software layout with hardware description.
--
commit febb42c38a1be5c88fbbc4e7b590710091550313
Author: Santhosh Kumar K <s-k6@ti.com>
spi: dt-bindings: cdns,qspi-nor: add PHY tuning pattern partition property
This commit introduces a new property, cdns,phy-pattern-partition, which
provides a phandle to the flash partition holding the PHY tuning pattern.
This allows the controller to locate the tuning data directly during
calibration rather than searching through partitions by label.
> diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor-peripheral-props.yaml
> index 510b82c177c05..0ffcdf5b00d03 100644
> --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor-peripheral-props.yaml
> +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor-peripheral-props.yaml
> @@ -39,4 +39,12 @@ properties:
> Delay in nanoseconds between setting qspi_n_ss_out low and
> first bit transfer.
>
> + cdns,phy-pattern-partition:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the flash partition containing the PHY tuning pattern.
[Severity: Medium]
Does this mix software layout abstractions with the hardware description?
Device Tree is intended to describe hardware topology, but MTD partitions
are a software partitioning scheme. Referencing a software partition node
directly from a hardware controller property tightly couples the hardware
configuration to a software concept.
If the standard NVMEM framework is unsuitable here because the SPI
controller requires a raw physical offset to issue hardware read commands,
would it be more appropriate to define a simple hardware-level property
like cdns,phy-pattern-offset instead of relying on partition phandles?
> + When present, the controller uses this partition to locate the
> + pattern data during PHY tuning instead of searching all partitions
> + by label.
> +
> additionalProperties: true
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260527175527.2247679-1-s-k6@ti.com?part=2
next prev parent reply other threads:[~2026-05-27 18:11 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-27 17:55 [PATCH v3 00/13] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-05-27 17:55 ` [PATCH v3 01/13] spi: dt-bindings: allow spi-max-frequency to specify a frequency pair Santhosh Kumar K
2026-05-27 18:17 ` sashiko-bot
2026-05-28 8:32 ` Miquel Raynal
2026-05-27 17:55 ` [PATCH v3 02/13] spi: dt-bindings: cdns,qspi-nor: add PHY tuning pattern partition property Santhosh Kumar K
2026-05-27 18:11 ` sashiko-bot [this message]
2026-05-28 8:34 ` Miquel Raynal
2026-05-27 17:55 ` [PATCH v3 03/13] spi: parse two-element spi-max-frequency property Santhosh Kumar K
2026-05-27 18:19 ` sashiko-bot
2026-05-28 8:37 ` Miquel Raynal
2026-05-27 17:55 ` [PATCH v3 04/13] spi: spi-mem: add spi_mem_apply_base_freq_cap() Santhosh Kumar K
2026-05-27 18:32 ` sashiko-bot
2026-05-28 8:43 ` Miquel Raynal
2026-05-27 17:55 ` [PATCH v3 05/13] spi: spi-mem: add execute_tuning callback and spi_mem_execute_tuning() Santhosh Kumar K
2026-05-27 18:21 ` sashiko-bot
2026-05-28 8:44 ` Miquel Raynal
2026-05-27 17:55 ` [PATCH v3 06/13] spi: cadence-quadspi: move cqspi_readdata_capture earlier Santhosh Kumar K
2026-05-27 17:55 ` [PATCH v3 07/13] spi: cadence-quadspi: add DQS support to read data capture Santhosh Kumar K
2026-05-27 18:17 ` sashiko-bot
2026-05-27 17:55 ` [PATCH v3 08/13] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-05-27 18:44 ` sashiko-bot
2026-05-28 8:54 ` Miquel Raynal
2026-05-27 17:55 ` [PATCH v3 09/13] spi: cadence-quadspi: reject 2-byte-address DDR ops on PHY-tunable hardware Santhosh Kumar K
2026-05-28 9:01 ` Miquel Raynal
2026-05-27 17:55 ` [PATCH v3 10/13] spi: cadence-quadspi: enable PHY for direct reads and indirect writes Santhosh Kumar K
2026-05-27 18:36 ` sashiko-bot
2026-05-28 9:09 ` Miquel Raynal
2026-05-27 17:55 ` [PATCH v3 11/13] mtd: spinand: run PHY tuning after init and update dirmap frequencies Santhosh Kumar K
2026-05-27 19:04 ` sashiko-bot
2026-05-28 9:27 ` Miquel Raynal
2026-05-27 17:55 ` [PATCH v3 12/13] mtd: spi-nor: extract read op template construction into helper Santhosh Kumar K
2026-05-27 17:55 ` [PATCH v3 13/13] mtd: spi-nor: run PHY tuning after init and update dirmap frequency Santhosh Kumar K
2026-05-27 18:59 ` sashiko-bot
2026-05-28 8:30 ` [PATCH v3 00/13] spi: cadence-quadspi: add PHY tuning support Miquel Raynal
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