From: sashiko-bot@kernel.org
To: "Imran Shaik" <imran.shaik@oss.qualcomm.com>
Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 02/12] dt-bindings: clock: qcom,qcm2290-dispcc: Add DSI1 PHY and sleep clocks
Date: Mon, 01 Jun 2026 18:32:03 +0000 [thread overview]
Message-ID: <20260601183203.A27731F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260601-shikra-dispcc-gpucc-v3-2-61c1ba3735e8@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Adding new items to the 'clocks' and 'clock-names' arrays without specifying a 'minItems' constraint breaks backward compatibility with existing device trees.
--
commit 85e4a2f46a61d48ee9c66caba34fbc7a3fa61a61
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>
dt-bindings: clock: qcom,qcm2290-dispcc: Add DSI1 PHY and sleep clocks
Update the QCM2290 DISPCC binding to document additional clock inputs
supported by the hardware, including DSI1 PHY byte/pixel clocks and
the sleep clock, alongside the existing clock list. This is an ABI
extension, and existing clock inputs ordering is unchanged.
> diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml
> --- a/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml
> @@ -25,8 +25,11 @@ properties:
> - description: Board active-only XO source
> - description: GPLL0 source from GCC
> - description: GPLL0 div source from GCC
> - - description: Byte clock from DSI PHY
> - - description: Pixel clock from DSI PHY
> + - description: Byte clock from DSI PHY0
> + - description: Pixel clock from DSI PHY0
> + - description: Byte clock from DSI PHY1
> + - description: Pixel clock from DSI PHY1
> + - description: Board sleep clock
[Severity: High]
Does adding these items to the clocks array without specifying a minItems
constraint cause a regression for backward compatibility with existing device
trees?
The commit message states "This is an ABI extension", but in dt-schema,
specifying an items list for an array implicitly sets both minItems and
maxItems to the length of the list unless overridden. Expanding the clocks
list from 6 to 9 items without adding minItems: 6 will result in dtbs_check
errors for older device trees that only provide 6 clocks.
>
> clock-names:
> items:
> @@ -36,6 +39,9 @@ properties:
> - const: gcc_disp_gpll0_div_clk_src
> - const: dsi0_phy_pll_out_byteclk
> - const: dsi0_phy_pll_out_dsiclk
> + - const: dsi1_phy_pll_out_byteclk
> + - const: dsi1_phy_pll_out_dsiclk
> + - const: sleep_clk
[Severity: High]
Similarly, does the clock-names array also need a minItems: 6 constraint?
Without it, the schema will strictly enforce that all 9 clock names must be
present, which might break compatibility with existing device trees that only
provide 6 clocks.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260601-shikra-dispcc-gpucc-v3-0-61c1ba3735e8@oss.qualcomm.com?part=2
next prev parent reply other threads:[~2026-06-01 18:32 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-01 18:21 [PATCH v3 00/12] clk: qcom: Add DISPCC and GPUCC support for the Qualcomm Shikra SoC Imran Shaik
2026-06-01 18:21 ` [PATCH v3 01/12] clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe Imran Shaik
2026-06-01 18:50 ` sashiko-bot
2026-06-01 18:21 ` [PATCH v3 02/12] dt-bindings: clock: qcom,qcm2290-dispcc: Add DSI1 PHY and sleep clocks Imran Shaik
2026-06-01 18:32 ` sashiko-bot [this message]
2026-06-01 18:21 ` [PATCH v3 03/12] dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller Imran Shaik
2026-06-01 18:38 ` sashiko-bot
2026-06-01 18:21 ` [PATCH v3 04/12] dt-bindings: clock: qcom: Add Qualcomm Shikra GPU " Imran Shaik
2026-06-01 18:21 ` [PATCH v3 05/12] clk: qcom: dispcc-qcm2290: Move to the latest common qcom_cc_probe() model Imran Shaik
2026-06-01 18:21 ` [PATCH v3 06/12] clk: qcom: dispcc-qcm2290: Switch to DT index based clk lookup Imran Shaik
2026-06-01 18:41 ` sashiko-bot
2026-06-01 18:21 ` [PATCH v3 07/12] clk: qcom: dispcc-qcm2290: Update GDSC *wait_val values and flags Imran Shaik
2026-06-01 18:33 ` sashiko-bot
2026-06-01 18:21 ` [PATCH v3 08/12] clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model Imran Shaik
2026-06-01 18:41 ` sashiko-bot
2026-06-01 18:21 ` [PATCH v3 09/12] clk: qcom: gpucc-qcm2290: Park RCG's clk source at XO during disable Imran Shaik
2026-06-01 18:21 ` [PATCH v3 10/12] clk: qcom: gpucc-qcm2290: Update GDSC *wait_val values and flags Imran Shaik
2026-06-01 18:21 ` [PATCH v3 11/12] clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra Imran Shaik
2026-06-01 18:21 ` [PATCH v3 12/12] arm64: dts: qcom: agatti: Add DSI1 PHY and sleep clocks to DISPCC node Imran Shaik
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260601183203.A27731F00893@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=imran.shaik@oss.qualcomm.com \
--cc=robh@kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox