Re: [PATCH v3 06/12] clk: qcom: dispcc-qcm2290: Switch to DT index based clk lookup

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The DSI1 PHY PLL byte clock input is not wired up in the parent mappings, making the DSI1 PHY support incomplete.
--

commit 6900a283b3a0edc157171145f5dc5bdc527dae67
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>

clk: qcom: dispcc-qcm2290: Switch to DT index based clk lookup

This commit updates the QCM2290 DISPCC driver to use DT index based
parent clock lookups and fixes the parent data for mdss ahb/mdp clocks.
It also introduces support for the DSI1 PHY PLL input clocks.

> diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
> index 1c21267ae0f7a..f5dbd19d0a033 100644
> --- a/drivers/clk/qcom/dispcc-qcm2290.c
> +++ b/drivers/clk/qcom/dispcc-qcm2290.c

[ ... ]

> @@ -72,8 +86,8 @@ static const struct parent_map disp_cc_parent_map_0[] = {
>  };
>  
>  static const struct clk_parent_data disp_cc_parent_data_0[] = {
> -	{ .fw_name = "bi_tcxo" },
> -	{ .fw_name = "dsi0_phy_pll_out_byteclk" },
> +	{ .index = DT_BI_TCXO },
> +	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
>  };

[Severity: High]
The commit message mentions adding DSI1 PHY PLL input clocks support, and
the enums for the DSI1 byte clock are added earlier in the patch.

Should P_DSI1_PHY_PLL_OUT_BYTECLK and DT_DSI1_PHY_PLL_OUT_BYTECLK be added
to disp_cc_parent_map_0 and disp_cc_parent_data_0 as well, similar to how
the DSICLK was added to disp_cc_parent_map_4 below?

Without it, does the hardware lack the ability to select the DSI1 byte
clock for disp_cc_mdss_byte0_clk_src?

[ ... ]

> @@ -101,19 +115,21 @@ static const struct parent_map disp_cc_parent_map_3[] = {
>  };
>  
>  static const struct clk_parent_data disp_cc_parent_data_3[] = {
> -	{ .fw_name = "bi_tcxo" },
> +	{ .index = DT_BI_TCXO },
>  	{ .hw = &disp_cc_pll0.clkr.hw },
> -	{ .fw_name = "gcc_disp_gpll0_clk_src" },
> +	{ .index = DT_GPLL0 },
>  };
>  
>  static const struct parent_map disp_cc_parent_map_4[] = {
>  	{ P_BI_TCXO, 0 },
>  	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
> +	{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
>  };
>  
>  static const struct clk_parent_data disp_cc_parent_data_4[] = {
> -	{ .fw_name = "bi_tcxo" },
> -	{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
> +	{ .index = DT_BI_TCXO },
> +	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
> +	{ .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260601-shikra-dispcc-gpucc-v3-0-61c1ba3735e8@oss.qualcomm.com?part=6