Re: [PATCH v3 07/12] clk: qcom: dispcc-qcm2290: Update GDSC *wait_val values and flags

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The patch incorrectly replaces `HW_CTRL` with `HW_CTRL_TRIGGER` for the MDSS GDSC, permanently disabling hardware control because the DRM MSM display framework does not implement dynamic hardware mode switching.
--

commit 6116e813ca331d00d8d79cfead6907de56f2475b
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>

clk: qcom: dispcc-qcm2290: Update GDSC *wait_val values and flags

This commit updates the QCM2290 DISPCC GDSC wait_val fields to match
hardware defaults and modifies GDSC flags. It adds flags to retain
registers, poll for CFG GDSCR, and dynamically switch between HW/SW modes.

> diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
> index f5dbd19d0a033..4c1eef79f41b6 100644
> --- a/drivers/clk/qcom/dispcc-qcm2290.c
> +++ b/drivers/clk/qcom/dispcc-qcm2290.c
> @@ -468,11 +468,14 @@ static const struct qcom_reset_map disp_cc_qcm2290_resets[] = {
>  
>  static struct gdsc mdss_gdsc = {
>  	.gdscr = 0x3000,
> +	.en_rest_wait_val = 0x2,
> +	.en_few_wait_val = 0x2,
> +	.clk_dis_wait_val = 0xf,
>  	.pd = {
>  		.name = "mdss_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> -	.flags = HW_CTRL,
> +	.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,

[Severity: Medium]
Does replacing HW_CTRL with HW_CTRL_TRIGGER here permanently disable hardware
control for the MDSS GDSC?

The HW_CTRL flag statically enables hardware mode during power-on. By changing
this to HW_CTRL_TRIGGER, hardware mode is disabled by default and must be
explicitly enabled by the consumer driver via dev_pm_genpd_set_hwmode().

Since the DRM MSM subsystem doesn't invoke dev_pm_genpd_set_hwmode(), will
the MDSS GDSC remain indefinitely in software mode, breaking hardware-managed
power scaling?

>  };
>  
>  static struct gdsc *disp_cc_qcm2290_gdscs[] = {

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Sashiko AI review · https://sashiko.dev/#/patchset/20260601-shikra-dispcc-gpucc-v3-0-61c1ba3735e8@oss.qualcomm.com?part=7