Re: [PATCH v3 08/12] clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing `.use_rpm = true` in `gpu_cc_qcm2290_desc` breaks power domain scaling and prevents the device from suspending, locking the VDDCX power domain permanently ON.
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commit 550d1d532a5ef23bc31943f5777d495cc864e4b4
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>

clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model

This commit updates the QCM2290 GPUCC driver to use the qcom_cc_probe() model.
It moves critical clocks and PLL configurations to driver_data and removes
explicit pm_clk handling.

> diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c
> index dc369dff882e6..1c8ed12f6bf81 100644
> --- a/drivers/clk/qcom/gpucc-qcm2290.c
> +++ b/drivers/clk/qcom/gpucc-qcm2290.c

[ ... ]

> @@ -350,6 +331,12 @@ static const struct regmap_config gpu_cc_qcm2290_regmap_config = {
>  	.fast_io = true,
>  };
>  
> +static const struct qcom_cc_driver_data gpu_cc_qcm2290_driver_data = {
> +	.alpha_plls = gpu_cc_qcm2290_plls,
> +	.num_alpha_plls = ARRAY_SIZE(gpu_cc_qcm2290_plls),
> +	.clk_cbcrs = gpu_cc_qcm2290_critical_cbcrs,
> +	.num_clk_cbcrs = ARRAY_SIZE(gpu_cc_qcm2290_critical_cbcrs),
> +};
>  
>  static const struct qcom_cc_desc gpu_cc_qcm2290_desc = {
>  	.config = &gpu_cc_qcm2290_regmap_config,
> @@ -359,6 +346,7 @@ static const struct qcom_cc_desc gpu_cc_qcm2290_desc = {
>  	.num_resets = ARRAY_SIZE(gpu_cc_qcm2290_resets),
>  	.gdscs = gpu_cc_qcm2290_gdscs,
>  	.num_gdscs = ARRAY_SIZE(gpu_cc_qcm2290_gdscs),
> +	.driver_data = &gpu_cc_qcm2290_driver_data,
>  };

[Severity: High]
Does this migration lock the VDDCX power domain permanently ON?

The previous probe function explicitly called devm_pm_runtime_enable() and
pm_runtime_put_sync(), allowing the device to drop its power domain vote.

Because .use_rpm = true is omitted in gpu_cc_qcm2290_desc, the common
clock framework will not manage runtime PM for this device.

Without runtime PM enabled, the device remains permanently active, which
can prevent the shared CX power domain from suspending.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260601-shikra-dispcc-gpucc-v3-0-61c1ba3735e8@oss.qualcomm.com?part=8