[PATCH v3] arm64: renesas: r8a779g0: add MFIS node

[PATCH v3] arm64: renesas: r8a779g0: add MFIS node

[Wolfram Sang]

Describe the MFIS core which is used for various tasks including
inter-processor communication. Interrupt numbers look irregular but they
all work as expected on a Renesas R-Car V4H SparrowHawk board.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---

Changes since v2:
* increased reg size to 0x10000 (Thanks, Geert!)
* shortened interrupt-names line length (Thanks, Geert!)

 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 82a7278836e5..3cff822fc609 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -603,6 +603,23 @@ tsn0: ethernet@e6460000 {
 			status = "disabled";
 		};
 
+		mfis: system-controller@e6260000 {
+			compatible = "renesas,r8a779g0-mfis";
+			reg = <0 0xe6260000 0 0x10000>;
+			reg-names = "common";
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0e", "ch1e", "ch2e", "ch3e", "ch4e", "ch5e", "ch6e", "ch7e",
+					  "ch8e", "ch9e", "ch10e", "ch11e";
+			#hwlock-cells = <1>;
+			#mbox-cells = <2>;
+			status = "disabled";
+		};
+
 		i2c0: i2c@e6500000 {
 			compatible = "renesas,i2c-r8a779g0",
 				     "renesas,rcar-gen4-i2c";
-- 
2.51.0

Re: [PATCH v3] arm64: renesas: r8a779g0: add MFIS node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `mfis` node violates unit-address sorting conventions within the `soc` node.
--

commit 103116fe94a9708e753fa97a039cb6fb2fa2c53c
Author: Wolfram Sang <wsa+renesas@sang-engineering.com>
arm64: renesas: r8a779g0: add MFIS node

This commit describes the MFIS core used for inter-processor communication
on the Renesas R-Car V4H SparrowHawk board. It adds the mfis node and its
associated interrupts to the device tree.

> diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> index 82a7278836e57..3cff822fc609a 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> @@ -603,6 +603,23 @@ tsn0: ethernet@e6460000 {
>  			status = "disabled";
>  		};
>  
> +		mfis: system-controller@e6260000 {

[Severity: Low]
This isn't a bug, but should this node be placed before the 
tsn0: ethernet@e6460000 node to maintain ascending unit-address order? 
The unit address 0xe6260000 is lower than 0xe6460000, and standard 
Device Tree conventions usually require sorting nodes sequentially.

> +			compatible = "renesas,r8a779g0-mfis";
> +			reg = <0 0xe6260000 0 0x10000>;

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260602153504.302388-2-wsa+renesas@sang-engineering.com?part=1

Re: [PATCH v3] arm64: renesas: r8a779g0: add MFIS node

[Wolfram Sang]

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On Tue, Jun 02, 2026 at 05:32:22PM +0200, Wolfram Sang wrote:
> Describe the MFIS core which is used for various tasks including
> inter-processor communication. Interrupt numbers look irregular but they
> all work as expected on a Renesas R-Car V4H SparrowHawk board.
> 
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Damn, messed up the ordering again :( Sorry, seems I did too many things
in parallel today...


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