* [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support
@ 2026-06-10 6:17 joakim.zhang
2026-06-10 6:17 ` [PATCH v3 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control joakim.zhang
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: joakim.zhang @ 2026-06-10 6:17 UTC (permalink / raw)
To: mturquette, sboyd, bmasney, robh, krzk+dt, conor+dt, p.zabel,
gary.yang
Cc: cix-kernel-upstream, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Joakim Zhang
From: Joakim Zhang <joakim.zhang@cixtech.com>
This patch set adds the clock and reset support for AUDSS. The AUDSS groups
audio-related peripherals (HDA, I2S, DSP, DMA, mailboxes, watchdog, timer, etc.)
behind a single Clock and Reset Unit (CRU) register block.
Clock and reset changes normally belong to separate subsystems and would
ideally be submitted as independent series. They are combined here because the
AUDSS DT bindings cross-reference each other: the system-control binding
describes the clock child node, the clock binding documents reset lines exposed
on the parent syscon, and the DTS example wires both together. Keeping clock
and reset in one series gives reviewers the full picture when evaluating the
binding layout, dependencies, and integration.
Patches apply in the following order:
1. Reset support
- dt-bindings: soc: cix,sky1-system-control: add audss system control
- reset: cix: add audss support to sky1 reset driver
2. Clock support
- dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller
- clk: cix: add sky1 audss clock controller
3. Device tree
- arm64: dts: cix: sky1: add audss system control
The reset and clock parts have each been build-tested and checked with
dt_binding_check independently. If reviewers prefer separate series for the
reset and clock maintainers, I can split and resubmit after this round of
review once the overall design is agreed on.
ChangeLogs:
v2->v3:
* clk part:
* devm_reset_control_get()->devm_reset_control_get_exclusive()
* assert noc reset from suspend
* clock parents changes from 6 to 4, and rename the clock names,
explain more about this: confirm with our designer, In fact,
there are 6 clock sources going into the audio subsystem. audio_clk1
and audio_clk3 are redundant in design and are not actually needed
in practice, so they are not shown here.
* refine clocks and clock-names property
* add detailed description of clocks
* drop parent node from clk binding
* drop define AUDSS_MAX_CLKS
* reset part:
* rename reset signal macro, remove _N
* drop SKY1_AUDSS_SW_RESET_NUM
* switching to compatible-style of defining subnodes in parent schema
v1->v2:
* remove audss_rst device node since it doesn't has resource, and
move to reset-sky1.c driver.
* remove hda related which would be sent after this patch set accepted
* soc componnet is okay by default from dtsi
* fix for audss clk driver:
* remove "comment "Clock options for Cixtech audss:""
* add select MFD_SYSCON
* move lock and clk_data into struct sky1_audss_clks_priv
* const char *name -> const char * const * name
* remove CLK_GET_RATE_NOCACHE
* divicer -> divider
* Reverse Christmas tree order
* return reg ? 1 : 0; -> return !!reg;
* return ERR_CAST(hw); -> return hw;
* of_device_get_match_data(dev) -> device_get_match_data()
* add lock from runtime_suspend/resume
* loop to more mailing lists
Joakim Zhang (5):
dt-bindings: soc: cix,sky1-system-control: add audss system control
reset: cix: add audss support to sky1 reset driver
dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller
clk: cix: add sky1 audss clock controller
arm64: dts: cix: sky1: add audss system control
.../bindings/clock/cix,sky1-audss-clock.yaml | 80 ++
.../soc/cix/cix,sky1-system-control.yaml | 47 +-
arch/arm64/boot/dts/cix/sky1.dtsi | 24 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/cix/Kconfig | 16 +
drivers/clk/cix/Makefile | 3 +
drivers/clk/cix/clk-sky1-audss.c | 1175 +++++++++++++++++
drivers/reset/reset-sky1.c | 36 +-
include/dt-bindings/clock/cix,sky1-audss.h | 60 +
.../reset/cix,sky1-audss-system-control.h | 25 +
11 files changed, 1461 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml
create mode 100644 drivers/clk/cix/Kconfig
create mode 100644 drivers/clk/cix/Makefile
create mode 100644 drivers/clk/cix/clk-sky1-audss.c
create mode 100644 include/dt-bindings/clock/cix,sky1-audss.h
create mode 100644 include/dt-bindings/reset/cix,sky1-audss-system-control.h
--
2.50.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v3 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control 2026-06-10 6:17 [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support joakim.zhang @ 2026-06-10 6:17 ` joakim.zhang 2026-06-10 6:25 ` sashiko-bot 2026-06-10 6:17 ` [PATCH v3 2/5] reset: cix: add audss support to sky1 reset driver joakim.zhang ` (4 subsequent siblings) 5 siblings, 1 reply; 11+ messages in thread From: joakim.zhang @ 2026-06-10 6:17 UTC (permalink / raw) To: mturquette, sboyd, bmasney, robh, krzk+dt, conor+dt, p.zabel, gary.yang Cc: cix-kernel-upstream, linux-clk, devicetree, linux-kernel, linux-arm-kernel, Joakim Zhang From: Joakim Zhang <joakim.zhang@cixtech.com> The Cix Sky1 Audio Subsystem (AUDSS) groups audio-related clock, reset and control registers in a dedicated CRU block. Software reset lines are exposed on the syscon parent via #reset-cells, following the same model as the existing Sky1 FCH and S5 system control bindings. Add the cix,sky1-audss-system-control compatible to cix,sky1-system-control.yaml for the MFD/syscon parent node, and define AUDSS software reset indices in include/dt-bindings/reset/cix,sky1-audss-system-control.h for I2S, HDA, DMAC, mailbox, watchdog and timer blocks. Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com> --- .../soc/cix/cix,sky1-system-control.yaml | 47 +++++++++++++++++-- .../reset/cix,sky1-audss-system-control.h | 25 ++++++++++ 2 files changed, 67 insertions(+), 5 deletions(-) create mode 100644 include/dt-bindings/reset/cix,sky1-audss-system-control.h diff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml index a01a515222c6..6c887b04cf25 100644 --- a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml +++ b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml @@ -15,11 +15,16 @@ description: properties: compatible: - items: - - enum: - - cix,sky1-system-control - - cix,sky1-s5-system-control - - const: syscon + oneOf: + - items: + - enum: + - cix,sky1-system-control + - cix,sky1-s5-system-control + - const: syscon + - items: + - const: cix,sky1-audss-system-control + - const: simple-mfd + - const: syscon reg: maxItems: 1 @@ -27,6 +32,28 @@ properties: '#reset-cells': const: 1 + clock-controller: + type: object + properties: + compatible: + const: cix,sky1-audss-clock + required: + - compatible + additionalProperties: true + +allOf: + - if: + properties: + compatible: + contains: + const: cix,sky1-audss-system-control + then: + required: + - clock-controller + else: + properties: + clock-controller: false + required: - compatible - reg @@ -40,3 +67,13 @@ examples: reg = <0x4160000 0x100>; #reset-cells = <1>; }; + - | + audss_syscon: system-controller@7110000 { + compatible = "cix,sky1-audss-system-control", "simple-mfd", "syscon"; + reg = <0x7110000 0x10000>; + #reset-cells = <1>; + + clock-controller { + compatible = "cix,sky1-audss-clock"; + }; + }; diff --git a/include/dt-bindings/reset/cix,sky1-audss-system-control.h b/include/dt-bindings/reset/cix,sky1-audss-system-control.h new file mode 100644 index 000000000000..aabdce60b094 --- /dev/null +++ b/include/dt-bindings/reset/cix,sky1-audss-system-control.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright 2026 Cix Technology Group Co., Ltd. + */ +#ifndef DT_BINDING_RESET_CIX_SKY1_AUDSS_SYSTEM_CONTROL_H +#define DT_BINDING_RESET_CIX_SKY1_AUDSS_SYSTEM_CONTROL_H + +#define AUDSS_I2S0_SW_RST 0 +#define AUDSS_I2S1_SW_RST 1 +#define AUDSS_I2S2_SW_RST 2 +#define AUDSS_I2S3_SW_RST 3 +#define AUDSS_I2S4_SW_RST 4 +#define AUDSS_I2S5_SW_RST 5 +#define AUDSS_I2S6_SW_RST 6 +#define AUDSS_I2S7_SW_RST 7 +#define AUDSS_I2S8_SW_RST 8 +#define AUDSS_I2S9_SW_RST 9 +#define AUDSS_WDT_SW_RST 10 +#define AUDSS_TIMER_SW_RST 11 +#define AUDSS_MB0_SW_RST 12 +#define AUDSS_MB1_SW_RST 13 +#define AUDSS_HDA_SW_RST 14 +#define AUDSS_DMAC_SW_RST 15 + +#endif -- 2.50.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control 2026-06-10 6:17 ` [PATCH v3 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control joakim.zhang @ 2026-06-10 6:25 ` sashiko-bot 0 siblings, 0 replies; 11+ messages in thread From: sashiko-bot @ 2026-06-10 6:25 UTC (permalink / raw) To: joakim.zhang; +Cc: conor+dt, devicetree, robh Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] The `clock-controller` child node in the `cix,sky1-audss-system-control` example completely omits `#clock-cells` and other properties (`clocks`, `clock-names`, `resets`, `power-domains`) required by its schema. According to subsystem guidelines, the `examples` section must include all required properties to pass schema validation. -- commit f2cf10fde483506768695633b3e23cc67dd4acf0 Author: Joakim Zhang <joakim.zhang@cixtech.com> dt-bindings: soc: cix,sky1-system-control: add audss system control This commit adds a new compatible string cix,sky1-audss-system-control to the cix,sky1-system-control device tree binding schema. It represents the Sky1 audio subsystem system control block, which acts as a syscon parent and simple-mfd for audio-related clocks and resets. It also adds a new reset indices header file for the software resets. > diff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml > --- a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml > +++ b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml [ ... ] > @@ -40,3 +67,13 @@ examples: > reg = <0x4160000 0x100>; > #reset-cells = <1>; > }; > + - | > + audss_syscon: system-controller@7110000 { > + compatible = "cix,sky1-audss-system-control", "simple-mfd", "syscon"; > + reg = <0x7110000 0x10000>; > + #reset-cells = <1>; > + > + clock-controller { > + compatible = "cix,sky1-audss-clock"; > + }; [Severity: Low] Are required properties like #clock-cells, clocks, clock-names, resets, and power-domains omitted from this clock-controller child node? According to subsystem guidelines, the examples section must include all required properties to pass schema validation. Will this incomplete node cause a regression during make dt_binding_check when the example is evaluated against the cix,sky1-audss-clock schema? > + }; -- Sashiko AI review · https://sashiko.dev/#/patchset/20260610061712.3203984-1-joakim.zhang@cixtech.com?part=1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 2/5] reset: cix: add audss support to sky1 reset driver 2026-06-10 6:17 [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support joakim.zhang 2026-06-10 6:17 ` [PATCH v3 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control joakim.zhang @ 2026-06-10 6:17 ` joakim.zhang 2026-06-10 6:17 ` [PATCH v3 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller joakim.zhang ` (3 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: joakim.zhang @ 2026-06-10 6:17 UTC (permalink / raw) To: mturquette, sboyd, bmasney, robh, krzk+dt, conor+dt, p.zabel, gary.yang Cc: cix-kernel-upstream, linux-clk, devicetree, linux-kernel, linux-arm-kernel, Joakim Zhang From: Joakim Zhang <joakim.zhang@cixtech.com> Extend the Sky1 reset controller driver for the AUDSS CRU syscon. The AUDSS block provides sixteen active-low software reset bits in one register for audio subsystem peripherals. Add a device tree match for cix,sky1-audss-system-control and the corresponding reset signal table in reset-sky1.c, reusing the existing regmap-based reset ops used by the FCH and S5 system control variants. Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com> --- drivers/reset/reset-sky1.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-sky1.c b/drivers/reset/reset-sky1.c index 78e80a533c39..88100c631cee 100644 --- a/drivers/reset/reset-sky1.c +++ b/drivers/reset/reset-sky1.c @@ -16,6 +16,7 @@ #include <dt-bindings/reset/cix,sky1-system-control.h> #include <dt-bindings/reset/cix,sky1-s5-system-control.h> +#include <dt-bindings/reset/cix,sky1-audss-system-control.h> #define SKY1_RESET_SLEEP_MIN_US 50 #define SKY1_RESET_SLEEP_MAX_US 100 @@ -258,6 +259,34 @@ static const struct sky1_src_variant variant_sky1_fch = { .signals_num = ARRAY_SIZE(sky1_src_fch_signals), }; +enum { + AUDSS_SW_RST = 0x78, +}; + +static const struct sky1_src_signal sky1_audss_signals[] = { + [AUDSS_I2S0_SW_RST] = { AUDSS_SW_RST, BIT(0) }, + [AUDSS_I2S1_SW_RST] = { AUDSS_SW_RST, BIT(1) }, + [AUDSS_I2S2_SW_RST] = { AUDSS_SW_RST, BIT(2) }, + [AUDSS_I2S3_SW_RST] = { AUDSS_SW_RST, BIT(3) }, + [AUDSS_I2S4_SW_RST] = { AUDSS_SW_RST, BIT(4) }, + [AUDSS_I2S5_SW_RST] = { AUDSS_SW_RST, BIT(5) }, + [AUDSS_I2S6_SW_RST] = { AUDSS_SW_RST, BIT(6) }, + [AUDSS_I2S7_SW_RST] = { AUDSS_SW_RST, BIT(7) }, + [AUDSS_I2S8_SW_RST] = { AUDSS_SW_RST, BIT(8) }, + [AUDSS_I2S9_SW_RST] = { AUDSS_SW_RST, BIT(9) }, + [AUDSS_WDT_SW_RST] = { AUDSS_SW_RST, BIT(10) }, + [AUDSS_TIMER_SW_RST] = { AUDSS_SW_RST, BIT(11) }, + [AUDSS_MB0_SW_RST] = { AUDSS_SW_RST, BIT(12) }, + [AUDSS_MB1_SW_RST] = { AUDSS_SW_RST, BIT(13) }, + [AUDSS_HDA_SW_RST] = { AUDSS_SW_RST, BIT(14) }, + [AUDSS_DMAC_SW_RST] = { AUDSS_SW_RST, BIT(15) }, +}; + +static const struct sky1_src_variant variant_sky1_audss = { + .signals = sky1_audss_signals, + .signals_num = ARRAY_SIZE(sky1_audss_signals), +}; + static struct sky1_src *to_sky1_src(struct reset_controller_dev *rcdev) { return container_of(rcdev, struct sky1_src, rcdev); @@ -329,6 +358,8 @@ static int sky1_reset_probe(struct platform_device *pdev) return -ENOMEM; variant = of_device_get_match_data(dev); + if (!variant) + return -ENODEV; sky1src->regmap = device_node_to_regmap(dev->of_node); if (IS_ERR(sky1src->regmap)) { @@ -347,8 +378,9 @@ static int sky1_reset_probe(struct platform_device *pdev) } static const struct of_device_id sky1_sysreg_of_match[] = { - { .compatible = "cix,sky1-system-control", .data = &variant_sky1_fch}, - { .compatible = "cix,sky1-s5-system-control", .data = &variant_sky1}, + { .compatible = "cix,sky1-system-control", .data = &variant_sky1_fch }, + { .compatible = "cix,sky1-s5-system-control", .data = &variant_sky1 }, + { .compatible = "cix,sky1-audss-system-control", .data = &variant_sky1_audss }, {}, }; MODULE_DEVICE_TABLE(of, sky1_sysreg_of_match); -- 2.50.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller 2026-06-10 6:17 [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support joakim.zhang 2026-06-10 6:17 ` [PATCH v3 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control joakim.zhang 2026-06-10 6:17 ` [PATCH v3 2/5] reset: cix: add audss support to sky1 reset driver joakim.zhang @ 2026-06-10 6:17 ` joakim.zhang 2026-06-10 6:24 ` sashiko-bot 2026-06-10 6:17 ` [PATCH v3 4/5] clk: cix: add sky1 " joakim.zhang ` (2 subsequent siblings) 5 siblings, 1 reply; 11+ messages in thread From: joakim.zhang @ 2026-06-10 6:17 UTC (permalink / raw) To: mturquette, sboyd, bmasney, robh, krzk+dt, conor+dt, p.zabel, gary.yang Cc: cix-kernel-upstream, linux-clk, devicetree, linux-kernel, linux-arm-kernel, Joakim Zhang From: Joakim Zhang <joakim.zhang@cixtech.com> The AUDSS CRU contains an internal clock tree of muxes, dividers and gates for DSP, I2S, HDA, DMAC and related blocks. The clock provider is a child node of the cix,sky1-audss-system-control syscon and accesses registers through the parent MMIO region. Add the devicetree binding for cix,sky1-audss-clock and clock indices in include/dt-bindings/clock/cix,sky1-audss.h. Document the parent syscon indices. Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com> --- .../bindings/clock/cix,sky1-audss-clock.yaml | 80 +++++++++++++++++++ include/dt-bindings/clock/cix,sky1-audss.h | 60 ++++++++++++++ 2 files changed, 140 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml create mode 100644 include/dt-bindings/clock/cix,sky1-audss.h diff --git a/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml b/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml new file mode 100644 index 000000000000..dff56f3a425b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/cix,sky1-audss-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 audio subsystem clock controller + +maintainers: + - Joakim Zhang <joakim.zhang@cixtech.com> + +description: | + Clock provider for the Cix Sky1 audio subsystem (AUDSS). + + This node is a child of a cix,sky1-audss-system-control MFD/syscon node + (see cix,sky1-system-control.yaml). It does not have a reg property; clock + mux, divider and gate fields are accessed through the parent register block. + + Software reset lines for AUDSS blocks are exposed on the parent syscon via + #reset-cells. Reset indices are defined in + include/dt-bindings/reset/cix,sky1-audss-system-control.h. + + Four SoC-level reference clocks listed in clocks/clock-names feed the AUDSS + clock tree. The provider exposes the internal AUDSS clocks to other devices + via #clock-cells; indices are defined in cix,sky1-audss.h. + +properties: + compatible: + const: cix,sky1-audss-clock + + '#clock-cells': + const: 1 + description: + Clock indices are defined in include/dt-bindings/clock/cix,sky1-audss.h. + + clocks: + items: + - description: I2S parent clock for sampling rates multiple of 8kHz. + - description: I2S parent clock for sampling rates multiple of 11.025kHz. + - description: clock feeding most devices in audss (NOC, DSP, SRAM, HDA, DMAC, I2S, and Mailbox). + - description: clock feeding for HDA, Timer and Watchdog, which is a delicated 48MHz clock. + + clock-names: + items: + - const: x8k + - const: x11k + - const: sys + - const: 48m + + resets: + maxItems: 1 + description: Audio subsystem NoC (or bus) reset line. + + power-domains: + maxItems: 1 + description: Audio subsystem power domain. + +required: + - compatible + - '#clock-cells' + - clocks + - clock-names + - resets + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/cix,sky1.h> + + clock-controller { + compatible = "cix,sky1-audss-clock"; + power-domains = <&smc_devpd 0>; + #clock-cells = <1>; + clocks = <&scmi_clk CLK_TREE_AUDIO_CLK0>, <&scmi_clk CLK_TREE_AUDIO_CLK2>, + <&scmi_clk CLK_TREE_AUDIO_CLK4>, <&scmi_clk CLK_TREE_AUDIO_CLK5>; + clock-names = "x8k", "x11k", "sys", "48m"; + resets = <&s5_syscon 31>; + }; diff --git a/include/dt-bindings/clock/cix,sky1-audss.h b/include/dt-bindings/clock/cix,sky1-audss.h new file mode 100644 index 000000000000..033046407dee --- /dev/null +++ b/include/dt-bindings/clock/cix,sky1-audss.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2026 Cix Technology Group Co., Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_CIX_SKY1_AUDSS_H +#define _DT_BINDINGS_CLK_CIX_SKY1_AUDSS_H + +#define CLK_AUD_CLK4_DIV2 0 +#define CLK_AUD_CLK4_DIV4 1 +#define CLK_AUD_CLK5_DIV2 2 + +#define CLK_DSP_CLK 3 +#define CLK_DSP_BCLK 4 +#define CLK_DSP_PBCLK 5 + +#define CLK_SRAM_AXI 6 + +#define CLK_HDA_SYS 7 +#define CLK_HDA_HDA 8 + +#define CLK_DMAC_AXI 9 + +#define CLK_WDG_APB 10 +#define CLK_WDG_WDG 11 + +#define CLK_TIMER_APB 12 +#define CLK_TIMER_TIMER 13 + +#define CLK_MB_0_APB 14 /* MB0: ap->dsp */ +#define CLK_MB_1_APB 15 /* MB1: dsp->ap */ + +#define CLK_I2S0_APB 16 +#define CLK_I2S1_APB 17 +#define CLK_I2S2_APB 18 +#define CLK_I2S3_APB 19 +#define CLK_I2S4_APB 20 +#define CLK_I2S5_APB 21 +#define CLK_I2S6_APB 22 +#define CLK_I2S7_APB 23 +#define CLK_I2S8_APB 24 +#define CLK_I2S9_APB 25 +#define CLK_I2S0 26 +#define CLK_I2S1 27 +#define CLK_I2S2 28 +#define CLK_I2S3 29 +#define CLK_I2S4 30 +#define CLK_I2S5 31 +#define CLK_I2S6 32 +#define CLK_I2S7 33 +#define CLK_I2S8 34 +#define CLK_I2S9 35 + +#define CLK_MCLK0 36 +#define CLK_MCLK1 37 +#define CLK_MCLK2 38 +#define CLK_MCLK3 39 +#define CLK_MCLK4 40 + +#endif -- 2.50.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v3 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller 2026-06-10 6:17 ` [PATCH v3 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller joakim.zhang @ 2026-06-10 6:24 ` sashiko-bot 0 siblings, 0 replies; 11+ messages in thread From: sashiko-bot @ 2026-06-10 6:24 UTC (permalink / raw) To: joakim.zhang; +Cc: devicetree, robh, conor+dt Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] The newly introduced `cix,sky1-audss-clock` schema causes a `dt_binding_check` validation failure in the parent `cix,sky1-system-control.yaml` example. -- commit 266331103ef923d7816fb4abbe0e462ec90cdfb6 Author: Joakim Zhang <joakim.zhang@cixtech.com> dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller The AUDSS CRU contains an internal clock tree of muxes, dividers and gates for DSP, I2S, HDA, DMAC and related blocks. The clock provider is a child node of the cix,sky1-audss-system-control syscon and accesses registers through the parent MMIO region. > diff --git a/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml b/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml > new file mode 100644 > index 0000000000000..dff56f3a425b9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml > @@ -0,0 +1,80 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/cix,sky1-audss-clock.yaml# [ ... ] > +required: > + - compatible > + - '#clock-cells' > + - clocks > + - clock-names > + - resets > + - power-domains [Severity: Low] Will this cause a dt_binding_check validation failure in the parent cix,sky1-system-control.yaml example? The parent binding contains an incomplete subnode example that will fail validation against this newly introduced clock schema: Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml: clock-controller { compatible = "cix,sky1-audss-clock"; }; Could the example in cix,sky1-system-control.yaml be updated to include these newly required properties to prevent validation errors? > + > +additionalProperties: false -- Sashiko AI review · https://sashiko.dev/#/patchset/20260610061712.3203984-1-joakim.zhang@cixtech.com?part=3 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 4/5] clk: cix: add sky1 audss clock controller 2026-06-10 6:17 [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support joakim.zhang ` (2 preceding siblings ...) 2026-06-10 6:17 ` [PATCH v3 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller joakim.zhang @ 2026-06-10 6:17 ` joakim.zhang 2026-06-10 6:29 ` sashiko-bot 2026-06-10 6:17 ` [PATCH v3 5/5] arm64: dts: cix: sky1: add audss system control joakim.zhang 2026-06-10 6:48 ` [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support Joakim Zhang 5 siblings, 1 reply; 11+ messages in thread From: joakim.zhang @ 2026-06-10 6:17 UTC (permalink / raw) To: mturquette, sboyd, bmasney, robh, krzk+dt, conor+dt, p.zabel, gary.yang Cc: cix-kernel-upstream, linux-clk, devicetree, linux-kernel, linux-arm-kernel, Joakim Zhang From: Joakim Zhang <joakim.zhang@cixtech.com> Add a platform driver for the Cix Sky1 Audio Subsystem (AUDSS) internal clock controller. The driver binds to a cix,sky1-audss-clock device tree node under the AUDSS syscon, obtains the parent regmap via syscon_node_to_regmap(), and registers mux/divider/gate composite clocks for DSP, SRAM, HDA, DMAC, watchdog, timer, mailbox and I2S outputs. Four SoC-level audio reference clocks are brought up as inputs to the tree. Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com> --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/cix/Kconfig | 16 + drivers/clk/cix/Makefile | 3 + drivers/clk/cix/clk-sky1-audss.c | 1175 ++++++++++++++++++++++++++++++ 5 files changed, 1196 insertions(+) create mode 100644 drivers/clk/cix/Kconfig create mode 100644 drivers/clk/cix/Makefile create mode 100644 drivers/clk/cix/clk-sky1-audss.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index b2efbe9f6acb..ead41e45c0f6 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -503,6 +503,7 @@ source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/aspeed/Kconfig" source "drivers/clk/bcm/Kconfig" +source "drivers/clk/cix/Kconfig" source "drivers/clk/eswin/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/imgtec/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index a3e2862ebd7e..9135ea6e5a8f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -118,6 +118,7 @@ obj-$(CONFIG_ARCH_ARTPEC) += axis/ obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ obj-y += bcm/ obj-$(CONFIG_ARCH_BERLIN) += berlin/ +obj-y += cix/ obj-$(CONFIG_ARCH_DAVINCI) += davinci/ obj-$(CONFIG_COMMON_CLK_ESWIN) += eswin/ obj-$(CONFIG_ARCH_HISI) += hisilicon/ diff --git a/drivers/clk/cix/Kconfig b/drivers/clk/cix/Kconfig new file mode 100644 index 000000000000..3909796f8656 --- /dev/null +++ b/drivers/clk/cix/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +# Audio subsystem clock support for Cixtech SoC family +menu "Clock support for Cixtech audss" + +config CLK_SKY1_AUDSS + tristate "Cixtech Sky1 Audio Subsystem Clock Driver" + depends on ARCH_CIX || COMPILE_TEST + select MFD_SYSCON + select REGMAP_MMIO + select RESET_CONTROLLER + help + Support for the Audio Subsystem clock controller present on + Cixtech Sky1 SoC. This driver provides mux, divider and gate + clocks for DSP, I2S, HDA and related blocks in the audio + subsystem. Say M or Y here if you want to build this driver. +endmenu diff --git a/drivers/clk/cix/Makefile b/drivers/clk/cix/Makefile new file mode 100644 index 000000000000..bc612f1d08b2 --- /dev/null +++ b/drivers/clk/cix/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_CLK_SKY1_AUDSS) += clk-sky1-audss.o diff --git a/drivers/clk/cix/clk-sky1-audss.c b/drivers/clk/cix/clk-sky1-audss.c new file mode 100644 index 000000000000..3ec6bea93b73 --- /dev/null +++ b/drivers/clk/cix/clk-sky1-audss.c @@ -0,0 +1,1175 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright 2026 Cix Technology Group Co., Ltd. + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/reset.h> + +#include <dt-bindings/clock/cix,sky1-audss.h> + +#define INFO_HIFI0 0x00 +#define INFO_CLK_GATE 0x10 +#define INFO_CLK_DIV 0x14 +#define INFO_CLK_MUX 0x18 +#define INFO_MCLK 0x70 + +#define SKY1_AUDSS_CLK_PARENTS_CNT 4 +#define SKY1_AUDSS_NUM_CLKS (CLK_MCLK4 + 1) + +static u32 sky1_reg_save[][2] = { + { INFO_HIFI0, 0 }, + { INFO_CLK_GATE, 0 }, + { INFO_CLK_DIV, 0 }, + { INFO_CLK_MUX, 0 }, + { INFO_MCLK, 0 }, +}; + +static const char * const sky1_audss_clk_names[SKY1_AUDSS_CLK_PARENTS_CNT] = { + "x8k", "x11k", "sys", "48m", +}; + +static const u32 sky1_clk_rate_default[SKY1_AUDSS_CLK_PARENTS_CNT] = { + 294912000, + 270950400, + 800000000, + 48000000, +}; + +static const char * const dsp_clk_parent[] = { + "audio_clk4" +}; + +static const char * const dsp_bclk_parent[] = { + "audio_clk4_div2" +}; + +static const char * const dsp_pbclk_parent[] = { + "audio_clk4_div4" +}; + +static const char * const sram_axi_parent[] = { + "audio_clk4_div2" +}; + +static const char * const hda_sys_parent[] = { + "audio_clk4_div2" +}; + +static const char * const hda_hda_parent[] = { + "audio_clk5" +}; + +static const char * const dmac_axi_parent[] = { + "audio_clk4_div2" +}; + +static const char * const wdg_apb_parent[] = { + "audio_clk5_div2" +}; + +static const char * const wdg_wdg_parent[] = { + "audio_clk5_div2" +}; + +static const char * const timer_apb_parent[] = { + "audio_clk4_div4" +}; + +static const char * const timer_timer_parent[] = { + "audio_clk5_div2" +}; + +static const char * const mailbox_apb_parent[] = { + "audio_clk4_div4" +}; + +static const char * const i2s_apb_parent[] = { + "audio_clk4_div4" +}; + +static const char * const i2s0_parents[] = { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s1_parents[] = { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s2_parents[] = { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s3_parents[] = { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s4_parents[] = { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s5_parents[] = { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s6_parents[] = { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s7_parents[] = { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s8_parents[] = { + "audio_clk0", "audio_clk2" +}; + +static const char * const i2s9_parents[] = { + "audio_clk0", "audio_clk2" +}; + +static const char * const mclk_parents[] = { + "audio_clk0", "audio_clk2" +}; + +static const u32 i2s3_mux_table[] = { 0, 2 }; +static const u32 i2s4_mux_table[] = { 0, 2 }; + +/* + * audss composite clock definition + */ +struct muxdiv_cfg { + int offset; + u8 shift; + u8 width; + u8 flags; +}; + +struct gate_cfg { + int offset; + u8 shift; + u8 flags; +}; + +struct composite_clk_cfg { + u32 id; + const char * const name; + const char * const *parent_names; + int num_parents; + const u32 *mux_table; + struct muxdiv_cfg *mux_cfg; + struct muxdiv_cfg *div_cfg; + struct gate_cfg *gate_cfg; + unsigned long flags; +}; + +#define CFG(_id,\ + _name,\ + _parent_names,\ + _mux_table,\ + _mux_offset, _mux_shift, _mux_width, _mux_flags,\ + _div_offset, _div_shift, _div_width, _div_flags,\ + _gate_offset, _gate_shift, _gate_flags,\ + _flags)\ +{\ + .id = _id,\ + .name = _name,\ + .parent_names = _parent_names,\ + .num_parents = ARRAY_SIZE(_parent_names),\ + .mux_table = _mux_table,\ + .mux_cfg = &(struct muxdiv_cfg) { _mux_offset, _mux_shift, _mux_width, _mux_flags },\ + .div_cfg = &(struct muxdiv_cfg) { _div_offset, _div_shift, _div_width, _div_flags },\ + .gate_cfg = &(struct gate_cfg) { _gate_offset, _gate_shift, _gate_flags },\ + .flags = _flags,\ +} + +static const struct composite_clk_cfg sky1_audss_clks[] = { + /* dsp */ + CFG(CLK_DSP_CLK, + "audss_dsp_clk", + dsp_clk_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_HIFI0, 0, 0, + 0), + CFG(CLK_DSP_BCLK, + "audss_dsp_bclk", + dsp_bclk_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + -1, 0, 0, + 0), + CFG(CLK_DSP_PBCLK, + "audss_dsp_pbclk", + dsp_pbclk_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + -1, 0, 0, + 0), + /* sram */ + CFG(CLK_SRAM_AXI, + "audss_sram_axi", + sram_axi_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 16, 0, + 0), + /* hda */ + CFG(CLK_HDA_SYS, + "audss_hda_sys", + hda_sys_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 14, 0, + 0), + CFG(CLK_HDA_HDA, + "audss_hda_hda", + hda_hda_parent, + NULL, + -1, 0, 0, 0, + -1, 0, 0, 0, + INFO_CLK_GATE, 14, 0, + 0), + /* dmac */ + CFG(CLK_DMAC_AXI, + "audss_dmac_axi", + dmac_axi_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 15, 0, + 0), + /* wdg */ + CFG(CLK_WDG_APB, + "audss_wdg_apb", + wdg_apb_parent, + NULL, + -1, 0, 0, 0, + -1, 0, 0, 0, + INFO_CLK_GATE, 10, 0, + 0), + CFG(CLK_WDG_WDG, + "audss_wdg_wdg", + wdg_wdg_parent, + NULL, + -1, 0, 0, 0, + -1, 0, 0, 0, + INFO_CLK_GATE, 10, 0, + 0), + /* timer */ + CFG(CLK_TIMER_APB, + "audss_timer_apb", + timer_apb_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 11, 0, + 0), + CFG(CLK_TIMER_TIMER, + "audss_timer_timer", + timer_timer_parent, + NULL, + -1, 0, 0, 0, + -1, 0, 0, 0, + INFO_CLK_GATE, 11, 0, + 0), + /* mailbox: mb0(ap->dsp), mb1(dsp->ap) */ + CFG(CLK_MB_0_APB, + "audss_mb_0_apb", + mailbox_apb_parent, + NULL, + -1, 0, 0, 0, + -1, 0, 0, 0, + INFO_CLK_GATE, 12, 0, + 0), + CFG(CLK_MB_1_APB, + "audss_mb_1_apb", + mailbox_apb_parent, + NULL, + -1, 0, 0, 0, + -1, 0, 0, 0, + INFO_CLK_GATE, 13, 0, + 0), + /* i2s */ + CFG(CLK_I2S0_APB, + "audss_i2s0_apb", + i2s_apb_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 0, 0, + 0), + CFG(CLK_I2S1_APB, + "audss_i2s1_apb", + i2s_apb_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 1, 0, + 0), + CFG(CLK_I2S2_APB, + "audss_i2s2_apb", + i2s_apb_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 2, 0, + 0), + CFG(CLK_I2S3_APB, + "audss_i2s3_apb", + i2s_apb_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 3, 0, + 0), + CFG(CLK_I2S4_APB, + "audss_i2s4_apb", + i2s_apb_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 4, 0, + 0), + CFG(CLK_I2S5_APB, + "audss_i2s5_apb", + i2s_apb_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 5, 0, + 0), + CFG(CLK_I2S6_APB, + "audss_i2s6_apb", + i2s_apb_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 6, 0, + 0), + CFG(CLK_I2S7_APB, + "audss_i2s7_apb", + i2s_apb_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 7, 0, + 0), + CFG(CLK_I2S8_APB, + "audss_i2s8_apb", + i2s_apb_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 8, 0, + 0), + CFG(CLK_I2S9_APB, + "audss_i2s9_apb", + i2s_apb_parent, + NULL, + -1, 0, 0, 0, + INFO_CLK_DIV, 0, 2, 0, + INFO_CLK_GATE, 9, 0, + 0), + CFG(CLK_I2S0, + "audss_i2s0", + i2s0_parents, + NULL, + INFO_CLK_MUX, 0, 2, 0, + INFO_CLK_DIV, 2, 2, 0, + INFO_CLK_GATE, 0, 0, + 0), + CFG(CLK_I2S1, + "audss_i2s1", + i2s1_parents, + NULL, + INFO_CLK_MUX, 2, 2, 0, + INFO_CLK_DIV, 4, 2, 0, + INFO_CLK_GATE, 1, 0, + 0), + CFG(CLK_I2S2, + "audss_i2s2", + i2s2_parents, + NULL, + INFO_CLK_MUX, 4, 2, 0, + INFO_CLK_DIV, 6, 2, 0, + INFO_CLK_GATE, 2, 0, + 0), + CFG(CLK_I2S3, + "audss_i2s3", + i2s3_parents, + i2s3_mux_table, + INFO_CLK_MUX, 6, 2, 0, + INFO_CLK_DIV, 8, 2, 0, + INFO_CLK_GATE, 3, 0, + 0), + CFG(CLK_I2S4, + "audss_i2s4", + i2s4_parents, + i2s4_mux_table, + INFO_CLK_MUX, 8, 2, 0, + INFO_CLK_DIV, 10, 2, 0, + INFO_CLK_GATE, 4, 0, + 0), + CFG(CLK_I2S5, + "audss_i2s5", + i2s5_parents, + NULL, + INFO_CLK_MUX, 10, 2, 0, + INFO_CLK_DIV, 12, 2, 0, + INFO_CLK_GATE, 5, 0, + 0), + CFG(CLK_I2S6, + "audss_i2s6", + i2s6_parents, + NULL, + INFO_CLK_MUX, 12, 2, 0, + INFO_CLK_DIV, 14, 2, 0, + INFO_CLK_GATE, 6, 0, + 0), + CFG(CLK_I2S7, + "audss_i2s7", + i2s7_parents, + NULL, + INFO_CLK_MUX, 14, 2, 0, + INFO_CLK_DIV, 16, 2, 0, + INFO_CLK_GATE, 7, 0, + 0), + CFG(CLK_I2S8, + "audss_i2s8", + i2s8_parents, + NULL, + INFO_CLK_MUX, 16, 2, 0, + INFO_CLK_DIV, 18, 2, 0, + INFO_CLK_GATE, 8, 0, + 0), + CFG(CLK_I2S9, + "audss_i2s9", + i2s9_parents, + NULL, + INFO_CLK_MUX, 18, 2, 0, + INFO_CLK_DIV, 20, 2, 0, + INFO_CLK_GATE, 9, 0, + 0), + /* mclk */ + CFG(CLK_MCLK0, + "audss_mclk0", + mclk_parents, + NULL, + INFO_MCLK, 5, 1, 0, + -1, 0, 0, 0, + INFO_MCLK, 0, 0, + 0), + CFG(CLK_MCLK1, + "audss_mclk1", + mclk_parents, + NULL, + INFO_MCLK, 6, 1, 0, + -1, 0, 0, 0, + INFO_MCLK, 1, 0, + 0), + CFG(CLK_MCLK2, + "audss_mclk2", + mclk_parents, + NULL, + INFO_MCLK, 7, 1, 0, + -1, 0, 0, 0, + INFO_MCLK, 2, 0, + 0), + CFG(CLK_MCLK3, + "audss_mclk3", + mclk_parents, + NULL, + INFO_MCLK, 8, 1, 0, + -1, 0, 0, 0, + INFO_MCLK, 3, 0, + 0), + CFG(CLK_MCLK4, + "audss_mclk4", + mclk_parents, + NULL, + INFO_MCLK, 9, 1, 0, + -1, 0, 0, 0, + INFO_MCLK, 4, 0, + 0), +}; + +struct sky1_audss_clks_devtype_data { + u32 (*reg_save)[2]; + size_t reg_save_size; + const char * const *clk_names; + size_t clk_num; + const u32 *clk_rate_default; + const struct composite_clk_cfg *clk_cfg; + size_t clk_cfg_size; +}; + +struct sky1_audss_clks_priv { + struct device *dev; + struct regmap *regmap_cru; + struct clk *clks[SKY1_AUDSS_CLK_PARENTS_CNT]; + struct reset_control *rst_noc; + const struct sky1_audss_clks_devtype_data *devtype_data; + spinlock_t lock; + struct clk_hw_onecell_data *clk_data; +}; + +/* + * clk_ops for audss clock mux/divider/gate + */ +struct sky1_clk_divider { + struct clk_divider div; + struct regmap *regmap; + int offset; +}; + +struct sky1_clk_gate { + struct clk_gate gate; + struct regmap *regmap; + int offset; +}; + +struct sky1_clk_mux { + struct clk_mux mux; + struct regmap *regmap; + int offset; +}; + +static inline struct sky1_clk_mux *to_sky1_clk_mux(struct clk_mux *mux) +{ + return container_of(mux, struct sky1_clk_mux, mux); +} + +static u8 sky1_audss_clk_mux_get_parent(struct clk_hw *hw) +{ + struct clk_mux *mux = to_clk_mux(hw); + struct sky1_clk_mux *sky1_mux = to_sky1_clk_mux(mux); + u32 val; + + regmap_read(sky1_mux->regmap, sky1_mux->offset, &val); + val = val >> mux->shift; + val &= mux->mask; + + return clk_mux_val_to_index(hw, mux->table, mux->flags, val); +} + +static int sky1_audss_clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_mux *mux = to_clk_mux(hw); + u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); + struct sky1_clk_mux *sky1_mux = to_sky1_clk_mux(mux); + unsigned long flags = 0; + u32 reg; + + if (mux->lock) + spin_lock_irqsave(mux->lock, flags); + else + __acquire(mux->lock); + + if (mux->flags & CLK_MUX_HIWORD_MASK) { + reg = mux->mask << (mux->shift + 16); + } else { + regmap_read(sky1_mux->regmap, sky1_mux->offset, ®); + reg &= ~(mux->mask << mux->shift); + } + val = val << mux->shift; + reg |= val; + regmap_write(sky1_mux->regmap, sky1_mux->offset, reg); + + if (mux->lock) + spin_unlock_irqrestore(mux->lock, flags); + else + __release(mux->lock); + + return 0; +} + +static int sky1_audss_clk_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_mux *mux = to_clk_mux(hw); + + return clk_mux_determine_rate_flags(hw, req, mux->flags); +} + +static const struct clk_ops sky1_audss_clk_mux_ops = { + .get_parent = sky1_audss_clk_mux_get_parent, + .set_parent = sky1_audss_clk_mux_set_parent, + .determine_rate = sky1_audss_clk_mux_determine_rate, +}; + +static inline struct sky1_clk_divider *to_sky1_clk_divider(struct clk_divider *div) +{ + return container_of(div, struct sky1_clk_divider, div); +} + +static unsigned long sky1_audss_clk_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_divider *divider = to_clk_divider(hw); + struct sky1_clk_divider *sky1_div = to_sky1_clk_divider(divider); + unsigned int val; + + regmap_read(sky1_div->regmap, sky1_div->offset, &val); + val = val >> divider->shift; + val &= clk_div_mask(divider->width); + + return divider_recalc_rate(hw, parent_rate, val, divider->table, + divider->flags, divider->width); +} + +static int sky1_audss_clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_divider *divider = to_clk_divider(hw); + struct sky1_clk_divider *sky1_div = to_sky1_clk_divider(divider); + + /* if read only, just return current value */ + if (divider->flags & CLK_DIVIDER_READ_ONLY) { + u32 val; + + regmap_read(sky1_div->regmap, sky1_div->offset, &val); + val = val >> divider->shift; + val &= clk_div_mask(divider->width); + + return divider_ro_determine_rate(hw, req, divider->table, + divider->width, + divider->flags, val); + } + + return divider_determine_rate(hw, req, divider->table, divider->width, + divider->flags); +} + +static int sky1_audss_clk_divider_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct clk_divider *divider = to_clk_divider(hw); + struct sky1_clk_divider *sky1_div = to_sky1_clk_divider(divider); + int value; + unsigned long flags = 0; + u32 val; + + value = divider_get_val(rate, parent_rate, divider->table, + divider->width, divider->flags); + if (value < 0) + return value; + + if (divider->lock) + spin_lock_irqsave(divider->lock, flags); + else + __acquire(divider->lock); + + if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { + val = clk_div_mask(divider->width) << (divider->shift + 16); + } else { + regmap_read(sky1_div->regmap, sky1_div->offset, &val); + val &= ~(clk_div_mask(divider->width) << divider->shift); + } + val |= (u32)value << divider->shift; + regmap_write(sky1_div->regmap, sky1_div->offset, val); + + if (divider->lock) + spin_unlock_irqrestore(divider->lock, flags); + else + __release(divider->lock); + + return 0; +} + +static const struct clk_ops sky1_audss_clk_divider_ops = { + .recalc_rate = sky1_audss_clk_divider_recalc_rate, + .determine_rate = sky1_audss_clk_divider_determine_rate, + .set_rate = sky1_audss_clk_divider_set_rate, +}; + +static inline struct sky1_clk_gate *to_sky1_clk_gate(struct clk_gate *gate) +{ + return container_of(gate, struct sky1_clk_gate, gate); +} + +static void sky1_audss_clk_gate_endisable(struct clk_hw *hw, int enable) +{ + struct clk_gate *gate = to_clk_gate(hw); + struct sky1_clk_gate *sky1_gate = to_sky1_clk_gate(gate); + int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; + unsigned long flags = 0; + u32 reg; + + set ^= enable; + + if (gate->lock) + spin_lock_irqsave(gate->lock, flags); + else + __acquire(gate->lock); + + if (gate->flags & CLK_GATE_HIWORD_MASK) { + reg = BIT(gate->bit_idx + 16); + if (set) + reg |= BIT(gate->bit_idx); + } else { + regmap_read(sky1_gate->regmap, sky1_gate->offset, ®); + + if (set) + reg |= BIT(gate->bit_idx); + else + reg &= ~BIT(gate->bit_idx); + } + + regmap_write(sky1_gate->regmap, sky1_gate->offset, reg); + + if (gate->lock) + spin_unlock_irqrestore(gate->lock, flags); + else + __release(gate->lock); +} + +static int sky1_audss_clk_gate_enable(struct clk_hw *hw) +{ + sky1_audss_clk_gate_endisable(hw, 1); + + return 0; +} + +static void sky1_audss_clk_gate_disable(struct clk_hw *hw) +{ + sky1_audss_clk_gate_endisable(hw, 0); +} + +static int sky1_audss_clk_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_gate *gate = to_clk_gate(hw); + struct sky1_clk_gate *sky1_gate = to_sky1_clk_gate(gate); + u32 reg; + + regmap_read(sky1_gate->regmap, sky1_gate->offset, ®); + + /* if a set bit disables this clk, flip it before masking */ + if (gate->flags & CLK_GATE_SET_TO_DISABLE) + reg ^= BIT(gate->bit_idx); + + reg &= BIT(gate->bit_idx); + + return !!reg; +} + +static const struct clk_ops sky1_audss_clk_gate_ops = { + .enable = sky1_audss_clk_gate_enable, + .disable = sky1_audss_clk_gate_disable, + .is_enabled = sky1_audss_clk_gate_is_enabled, +}; + +static struct clk_hw *sky1_audss_clk_register(struct device *dev, + const char *name, + const char * const *parent_names, + int num_parents, + struct regmap *regmap, + const u32 *mux_table, + struct muxdiv_cfg *mux_cfg, + struct muxdiv_cfg *div_cfg, + struct gate_cfg *gate_cfg, + unsigned long flags, + spinlock_t *lock) +{ + const struct clk_ops *sky1_mux_ops = NULL; + const struct clk_ops *sky1_div_ops = NULL; + const struct clk_ops *sky1_gate_ops = NULL; + struct clk_hw *hw = ERR_PTR(-ENOMEM); + struct sky1_clk_divider *sky1_div = NULL; + struct sky1_clk_gate *sky1_gate = NULL; + struct sky1_clk_mux *sky1_mux = NULL; + + if (mux_cfg->offset >= 0) { + sky1_mux = devm_kzalloc(dev, sizeof(*sky1_mux), GFP_KERNEL); + if (!sky1_mux) + return ERR_PTR(-ENOMEM); + + sky1_mux->mux.reg = NULL; + sky1_mux->mux.shift = mux_cfg->shift; + sky1_mux->mux.mask = BIT(mux_cfg->width) - 1; + sky1_mux->mux.flags = mux_cfg->flags; + sky1_mux->mux.table = mux_table; + sky1_mux->mux.lock = lock; + sky1_mux_ops = &sky1_audss_clk_mux_ops; + sky1_mux->regmap = regmap; + sky1_mux->offset = mux_cfg->offset; + } + + if (div_cfg->offset >= 0) { + sky1_div = devm_kzalloc(dev, sizeof(*sky1_div), GFP_KERNEL); + if (!sky1_div) + return ERR_PTR(-ENOMEM); + + sky1_div->div.reg = NULL; + sky1_div->div.shift = div_cfg->shift; + sky1_div->div.width = div_cfg->width; + sky1_div->div.flags = div_cfg->flags | CLK_DIVIDER_POWER_OF_TWO; + sky1_div->div.lock = lock; + sky1_div_ops = &sky1_audss_clk_divider_ops; + sky1_div->regmap = regmap; + sky1_div->offset = div_cfg->offset; + } + + if (gate_cfg->offset >= 0) { + sky1_gate = devm_kzalloc(dev, sizeof(*sky1_gate), GFP_KERNEL); + if (!sky1_gate) + return ERR_PTR(-ENOMEM); + + sky1_gate->gate.reg = NULL; + sky1_gate->gate.bit_idx = gate_cfg->shift; + sky1_gate->gate.flags = gate_cfg->flags; + sky1_gate->gate.lock = lock; + sky1_gate_ops = &sky1_audss_clk_gate_ops; + sky1_gate->regmap = regmap; + sky1_gate->offset = gate_cfg->offset; + } + + hw = clk_hw_register_composite(dev, name, parent_names, num_parents, + sky1_mux ? &sky1_mux->mux.hw : NULL, sky1_mux_ops, + sky1_div ? &sky1_div->div.hw : NULL, sky1_div_ops, + sky1_gate ? &sky1_gate->gate.hw : NULL, sky1_gate_ops, + flags); + if (IS_ERR(hw)) { + dev_err(dev, "register %s clock failed with err = %ld\n", + name, PTR_ERR(hw)); + return hw; + } + + return hw; +} + +static int sky1_audss_clks_get(struct sky1_audss_clks_priv *priv) +{ + const struct sky1_audss_clks_devtype_data *devtype_data = priv->devtype_data; + int i; + + for (i = 0; i < devtype_data->clk_num; i++) { + priv->clks[i] = devm_clk_get(priv->dev, devtype_data->clk_names[i]); + if (IS_ERR(priv->clks[i])) + return dev_err_probe(priv->dev, PTR_ERR(priv->clks[i]), + "failed to get clock %s", devtype_data->clk_names[i]); + } + + return 0; +} + +static int sky1_audss_clks_enable(struct sky1_audss_clks_priv *priv) +{ + const struct sky1_audss_clks_devtype_data *devtype_data = priv->devtype_data; + int i, err; + + for (i = 0; i < devtype_data->clk_num; i++) { + err = clk_prepare_enable(priv->clks[i]); + if (err) { + dev_err(priv->dev, "failed to enable clock %s\n", + devtype_data->clk_names[i]); + goto err_clks; + } + } + + return 0; + +err_clks: + while (--i >= 0) + clk_disable_unprepare(priv->clks[i]); + + return err; +} + +static void sky1_audss_clks_disable(struct sky1_audss_clks_priv *priv) +{ + const struct sky1_audss_clks_devtype_data *devtype_data = priv->devtype_data; + int i; + + for (i = 0; i < devtype_data->clk_num; i++) + clk_disable_unprepare(priv->clks[i]); +} + +static int sky1_audss_clks_set_rate(struct sky1_audss_clks_priv *priv) +{ + const struct sky1_audss_clks_devtype_data *devtype_data = priv->devtype_data; + int i, err; + + for (i = 0; i < devtype_data->clk_num; i++) { + err = clk_set_rate(priv->clks[i], devtype_data->clk_rate_default[i]); + if (err) { + dev_err(priv->dev, "failed to set clock rate %s\n", + devtype_data->clk_names[i]); + return err; + } + } + + return 0; +} + +/* register sky1 audio subsystem clocks */ +static int sky1_audss_clk_probe(struct platform_device *pdev) +{ + const struct sky1_audss_clks_devtype_data *devtype_data; + struct sky1_audss_clks_priv *priv; + struct device_node *parent_np; + struct device *dev = &pdev->dev; + struct reset_control *rst_noc; + struct clk_hw **clk_table; + struct regmap *regmap_cru; + int i, ret; + + parent_np = of_get_parent(pdev->dev.of_node); + regmap_cru = syscon_node_to_regmap(parent_np); + of_node_put(parent_np); + if (IS_ERR(regmap_cru)) + return dev_err_probe(dev, PTR_ERR(regmap_cru), + "unable to get audss cru regmap"); + + devtype_data = device_get_match_data(dev); + if (!devtype_data) + return -ENODEV; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->lock); + + priv->clk_data = devm_kzalloc(&pdev->dev, + struct_size(priv->clk_data, hws, SKY1_AUDSS_NUM_CLKS), + GFP_KERNEL); + if (!priv->clk_data) + return -ENOMEM; + + priv->clk_data->num = SKY1_AUDSS_NUM_CLKS; + clk_table = priv->clk_data->hws; + + priv->dev = dev; + priv->regmap_cru = regmap_cru; + priv->devtype_data = devtype_data; + + ret = sky1_audss_clks_get(priv); + if (ret) + return ret; + + rst_noc = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(rst_noc)) + return dev_err_probe(dev, PTR_ERR(rst_noc), + "failed to get noc reset"); + priv->rst_noc = rst_noc; + + platform_set_drvdata(pdev, priv); + + ret = sky1_audss_clks_enable(priv); + if (ret) { + dev_err(dev, "failed to enable clocks\n"); + return ret; + } + + /* + * Enable runtime PM here to allow the clock core using runtime PM + * for the registered clocks. + */ + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + ret = sky1_audss_clks_set_rate(priv); + if (ret) { + dev_err(dev, "failed to set clocks rate\n"); + goto fail_clks_set; + } + + /* assert reset */ + reset_control_assert(rst_noc); + usleep_range(1, 2); + + /* deassert reset */ + reset_control_deassert(rst_noc); + + /* audio_clk4 clock fixed divider */ + clk_table[CLK_AUD_CLK4_DIV2] = + devm_clk_hw_register_fixed_factor(dev, + "audio_clk4_div2", + "audio_clk4", + 0, + 1, 2); + if (IS_ERR(clk_table[CLK_AUD_CLK4_DIV2])) { + ret = PTR_ERR(clk_table[CLK_AUD_CLK4_DIV2]); + dev_err(dev, "failed to register clock %d, ret:%d\n", CLK_AUD_CLK4_DIV2, ret); + goto fail_fixed_clk; + } + + clk_table[CLK_AUD_CLK4_DIV4] = + devm_clk_hw_register_fixed_factor(dev, + "audio_clk4_div4", + "audio_clk4", + 0, + 1, 4); + if (IS_ERR(clk_table[CLK_AUD_CLK4_DIV4])) { + ret = PTR_ERR(clk_table[CLK_AUD_CLK4_DIV4]); + dev_err(dev, "failed to register clock %d, ret:%d\n", CLK_AUD_CLK4_DIV4, ret); + goto fail_fixed_clk; + } + + /* audio_clk5 clock fixed divider */ + clk_table[CLK_AUD_CLK5_DIV2] = + devm_clk_hw_register_fixed_factor(dev, + "audio_clk5_div2", + "audio_clk5", + 0, + 1, 2); + if (IS_ERR(clk_table[CLK_AUD_CLK5_DIV2])) { + ret = PTR_ERR(clk_table[CLK_AUD_CLK5_DIV2]); + dev_err(dev, "failed to register clock %d, ret:%d\n", CLK_AUD_CLK5_DIV2, ret); + goto fail_fixed_clk; + } + + for (i = 0; i < devtype_data->clk_cfg_size; i++) { + clk_table[devtype_data->clk_cfg[i].id] = + sky1_audss_clk_register(dev, + devtype_data->clk_cfg[i].name, + devtype_data->clk_cfg[i].parent_names, + devtype_data->clk_cfg[i].num_parents, + regmap_cru, + devtype_data->clk_cfg[i].mux_table, + devtype_data->clk_cfg[i].mux_cfg, + devtype_data->clk_cfg[i].div_cfg, + devtype_data->clk_cfg[i].gate_cfg, + devtype_data->clk_cfg[i].flags, + &priv->lock); + if (IS_ERR(clk_table[devtype_data->clk_cfg[i].id])) { + ret = PTR_ERR(clk_table[devtype_data->clk_cfg[i].id]); + dev_err(dev, "failed to register clock %d, ret:%d\n", + devtype_data->clk_cfg[i].id, ret); + goto fail_array_clk; + } + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv->clk_data); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + goto fail_register; + } + + pm_runtime_put_sync(dev); + + return 0; + +fail_register: +fail_array_clk: + while (i--) + clk_hw_unregister_composite(clk_table[devtype_data->clk_cfg[i].id]); +fail_fixed_clk: +fail_clks_set: + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + return ret; +} + +static void sky1_audss_clk_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sky1_audss_clks_priv *priv = dev_get_drvdata(dev); + const struct sky1_audss_clks_devtype_data *devtype_data = priv->devtype_data; + int i = 0; + + for (i = 0; i < devtype_data->clk_cfg_size; i++) + clk_hw_unregister_composite(priv->clk_data->hws[devtype_data->clk_cfg[i].id]); + + if (!pm_runtime_status_suspended(dev)) + pm_runtime_force_suspend(dev); + + pm_runtime_disable(dev); +} + +static int __maybe_unused sky1_audss_clk_runtime_suspend(struct device *dev) +{ + struct sky1_audss_clks_priv *priv = dev_get_drvdata(dev); + const struct sky1_audss_clks_devtype_data *devtype_data = priv->devtype_data; + unsigned long flags; + int i; + + spin_lock_irqsave(&priv->lock, flags); + for (i = 0; i < devtype_data->reg_save_size; i++) + regmap_read(priv->regmap_cru, + devtype_data->reg_save[i][0], &devtype_data->reg_save[i][1]); + spin_unlock_irqrestore(&priv->lock, flags); + + reset_control_assert(priv->rst_noc); + + sky1_audss_clks_disable(priv); + + return 0; +} + +static int __maybe_unused sky1_audss_clk_runtime_resume(struct device *dev) +{ + struct sky1_audss_clks_priv *priv = dev_get_drvdata(dev); + const struct sky1_audss_clks_devtype_data *devtype_data = priv->devtype_data; + unsigned long flags; + int i, ret; + + ret = sky1_audss_clks_enable(priv); + if (ret) { + dev_err(dev, "failed to enable clocks\n"); + return ret; + } + + reset_control_deassert(priv->rst_noc); + + spin_lock_irqsave(&priv->lock, flags); + for (i = 0; i < devtype_data->reg_save_size; i++) + regmap_write(priv->regmap_cru, + devtype_data->reg_save[i][0], devtype_data->reg_save[i][1]); + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static const struct dev_pm_ops sky1_audss_clk_pm_ops = { + SET_RUNTIME_PM_OPS(sky1_audss_clk_runtime_suspend, + sky1_audss_clk_runtime_resume, NULL) + SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static const struct sky1_audss_clks_devtype_data sky1_devtype_data = { + .reg_save = sky1_reg_save, + .reg_save_size = ARRAY_SIZE(sky1_reg_save), + .clk_names = sky1_audss_clk_names, + .clk_num = ARRAY_SIZE(sky1_audss_clk_names), + .clk_rate_default = sky1_clk_rate_default, + .clk_cfg = sky1_audss_clks, + .clk_cfg_size = ARRAY_SIZE(sky1_audss_clks), +}; + +static const struct of_device_id sky1_audss_clk_of_match[] = { + { .compatible = "cix,sky1-audss-clock", .data = &sky1_devtype_data, }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, sky1_audss_clk_of_match); + +static struct platform_driver sky1_audss_clk_driver = { + .probe = sky1_audss_clk_probe, + .remove = sky1_audss_clk_remove, + .driver = { + .name = "sky1-audss-clk", + .suppress_bind_attrs = true, + .of_match_table = sky1_audss_clk_of_match, + .pm = &sky1_audss_clk_pm_ops, + }, +}; +module_platform_driver(sky1_audss_clk_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Joakim Zhang <joakim.zhang@cixtech.com>"); +MODULE_DESCRIPTION("Cixtech Sky1 Audio Subsystem Clock Controller Driver"); -- 2.50.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v3 4/5] clk: cix: add sky1 audss clock controller 2026-06-10 6:17 ` [PATCH v3 4/5] clk: cix: add sky1 " joakim.zhang @ 2026-06-10 6:29 ` sashiko-bot 0 siblings, 0 replies; 11+ messages in thread From: sashiko-bot @ 2026-06-10 6:29 UTC (permalink / raw) To: joakim.zhang; +Cc: conor+dt, devicetree, robh Thank you for your contribution! Sashiko AI review found 8 potential issue(s) to consider: - [High] Device-specific suspend/resume register state is stored in a globally shared static array, breaking multi-instance support and causing state corruption. - [High] Unchecked regmap_read() results in usage of uninitialized stack variables. - [High] Clock operations access hardware registers without PM runtime protection, potentially causing bus faults or lost register updates. - [High] Race condition during device removal leading to Use-After-Free of composite clock structures due to LIFO inversion. - [High] A massive copy-paste error causes nearly all clocks in the system to write to the exact same divider register bits, leading to silently corrupted hardware states. - [High] Non-atomic read-modify-write sequences are performed on a shared syscon regmap, leading to race conditions. - [Medium] Parent clocks enabled during probe are leaked on device removal and probe error paths when CONFIG_PM is disabled. - [Low] The `dev_pm_ops` structure pointer is assigned unconditionally in the driver, producing dead code when CONFIG_PM is disabled. -- commit f6414eab975c93e0178027203d04f1647fb5efdb Author: Joakim Zhang <joakim.zhang@cixtech.com> Date: Wed Jun 10 06:17:11 2026 +0000 clk: cix: add sky1 audss clock controller Add a platform driver for the Cix Sky1 Audio Subsystem (AUDSS) internal clock controller. The driver binds to a cix,sky1-audss-clock device tree node under the AUDSS syscon, obtains the parent regmap via syscon_node_to_regmap(), and registers mux/divider/gate composite clocks for DSP, SRAM, HDA, DMAC, watchdog, timer, mailbox and I2S outputs. Four SoC-level audio reference clocks are brought up as inputs to the tree. > diff --git a/drivers/clk/cix/clk-sky1-audss.c b/drivers/clk/cix/clk-sky1-audss.c > new file mode 100644 > index 0000000000000..3ec6bea93b73c > --- /dev/null > +++ b/drivers/clk/cix/clk-sky1-audss.c [ ... ] > +static u32 sky1_reg_save[][2] = { > + { INFO_HIFI0, 0 }, > + { INFO_CLK_GATE, 0 }, > + { INFO_CLK_DIV, 0 }, > + { INFO_CLK_MUX, 0 }, > + { INFO_MCLK, 0 }, > +}; [Severity: High] Will this global static array cause state corruption if there are multiple instances of the device? It looks like multiple instances would concurrently overwrite each other's saved register context during suspend/resume. Should this save buffer be allocated per-instance inside struct sky1_audss_clks_priv? [ ... ] > + CFG(CLK_I2S0_APB, > + "audss_i2s0_apb", > + i2s_apb_parent, > + NULL, > + -1, 0, 0, 0, > + INFO_CLK_DIV, 0, 2, 0, [Severity: High] Does this configuration accidentally assign the same register and bit shift to multiple clocks? Looking at the array, clocks like CLK_I2S0_APB through CLK_I2S9_APB, as well as CLK_DSP_CLK, CLK_SRAM_AXI, and others, all specify INFO_CLK_DIV, 0, 2, 0 for their divider. Will updating the rate for any of these clocks silently overwrite the hardware divider for all the others? [ ... ] > +static u8 sky1_audss_clk_mux_get_parent(struct clk_hw *hw) > +{ > + struct clk_mux *mux = to_clk_mux(hw); > + struct sky1_clk_mux *sky1_mux = to_sky1_clk_mux(mux); > + u32 val; > + > + regmap_read(sky1_mux->regmap, sky1_mux->offset, &val); > + val = val >> mux->shift; [Severity: High] If regmap_read() fails, could this use an uninitialized stack variable? The return value of regmap_read() is ignored, meaning val could remain uninitialized when shifted and returned. A similar pattern appears in sky1_audss_clk_divider_recalc_rate(). [ ... ] > +static int sky1_audss_clk_mux_set_parent(struct clk_hw *hw, u8 index) > +{ [ ... ] > + if (mux->flags & CLK_MUX_HIWORD_MASK) { > + reg = mux->mask << (mux->shift + 16); > + } else { > + regmap_read(sky1_mux->regmap, sky1_mux->offset, ®); > + reg &= ~(mux->mask << mux->shift); > + } > + val = val << mux->shift; > + reg |= val; > + regmap_write(sky1_mux->regmap, sky1_mux->offset, reg); [Severity: High] Is it safe to access hardware registers here without ensuring the device is active via PM runtime functions? If the clock callbacks are invoked while the subsystem is suspended, this might access powered-down MMIO or the changes might be immediately overwritten when sky1_audss_clk_runtime_resume() restores the old state. [Severity: High] Can this sequence lose concurrent register updates? Since the regmap is shared via syscon_node_to_regmap(), the private lock doesn't serialize these accesses against other drivers modifying different bits in the same syscon. Would regmap_update_bits() be safer here to atomically perform the update? A similar pattern appears in sky1_audss_clk_divider_set_rate() and the gate callbacks. [ ... ] > +fail_clks_set: > + pm_runtime_put_sync(dev); > + pm_runtime_disable(dev); > + return ret; > +} [Severity: Medium] Will the parent clocks leak their prepare/enable references if CONFIG_PM is disabled? The driver relies on pm_runtime_put_sync() to trigger the suspend callback to disable the clocks. If runtime PM is stubbed out, the clocks enabled during probe might never be disabled on error paths or during device removal. [ ... ] > +static void sky1_audss_clk_remove(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct sky1_audss_clks_priv *priv = dev_get_drvdata(dev); > + const struct sky1_audss_clks_devtype_data *devtype_data = priv->devtype_data; > + int i = 0; > + > + for (i = 0; i < devtype_data->clk_cfg_size; i++) > + clk_hw_unregister_composite(priv->clk_data->hws[devtype_data->clk_cfg[i].id]); [Severity: High] Does this create a use-after-free window? The OF clock provider is registered using devm_of_clk_add_hw_provider() which will run its cleanup after remove() finishes. If we manually unregister and free the composite clocks here, consumers might look up a freed clock pointer via the device tree during that window. [ ... ] > +static struct platform_driver sky1_audss_clk_driver = { > + .probe = sky1_audss_clk_probe, > + .remove = sky1_audss_clk_remove, > + .driver = { > + .name = "sky1-audss-clk", > + .suppress_bind_attrs = true, > + .of_match_table = sky1_audss_clk_of_match, > + .pm = &sky1_audss_clk_pm_ops, [Severity: Low] Is it intended to leave the dev_pm_ops pointer assigned unconditionally? If CONFIG_PM is disabled, this prevents the compiler from discarding the sky1_audss_clk_pm_ops structure and its referenced callbacks as dead code. Could we use the pm_ptr() wrapper here? -- Sashiko AI review · https://sashiko.dev/#/patchset/20260610061712.3203984-1-joakim.zhang@cixtech.com?part=4 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 5/5] arm64: dts: cix: sky1: add audss system control 2026-06-10 6:17 [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support joakim.zhang ` (3 preceding siblings ...) 2026-06-10 6:17 ` [PATCH v3 4/5] clk: cix: add sky1 " joakim.zhang @ 2026-06-10 6:17 ` joakim.zhang 2026-06-10 6:48 ` [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support Joakim Zhang 5 siblings, 0 replies; 11+ messages in thread From: joakim.zhang @ 2026-06-10 6:17 UTC (permalink / raw) To: mturquette, sboyd, bmasney, robh, krzk+dt, conor+dt, p.zabel, gary.yang Cc: cix-kernel-upstream, linux-clk, devicetree, linux-kernel, linux-arm-kernel, Joakim Zhang From: Joakim Zhang <joakim.zhang@cixtech.com> Add audss system control device node, which would provides clocks and resets for devices in audss domain. Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com> --- arch/arm64/boot/dts/cix/sky1.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index bb5cfb1f2113..368a1d85c93d 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -6,6 +6,10 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/cix,sky1.h> +#include <dt-bindings/clock/cix,sky1-audss.h> +#include <dt-bindings/reset/cix,sky1-system-control.h> +#include <dt-bindings/reset/cix,sky1-s5-system-control.h> +#include <dt-bindings/reset/cix,sky1-audss-system-control.h> #include "sky1-power.h" / { @@ -488,6 +492,26 @@ mbox_pm2ap: mailbox@65a0080 { cix,mbox-dir = "rx"; }; + audss_cru: system-controller@7110000 { + compatible = "cix,sky1-audss-system-control", "simple-mfd", "syscon"; + reg = <0x0 0x07110000 0x0 0x10000>; + #reset-cells = <1>; + status = "okay"; + + audss_clk: clock-controller { + compatible = "cix,sky1-audss-clock"; + power-domains = <&smc_devpd SKY1_PD_AUDIO>; + resets = <&s5_syscon SKY1_AUDIO_HIFI5_NOC_RESET_N>; + clocks = <&scmi_clk CLK_TREE_AUDIO_CLK0>, + <&scmi_clk CLK_TREE_AUDIO_CLK2>, + <&scmi_clk CLK_TREE_AUDIO_CLK4>, + <&scmi_clk CLK_TREE_AUDIO_CLK5>; + clock-names = "x8k", "x11k", "sys", "48m"; + #clock-cells = <1>; + status = "okay"; + }; + }; + mbox_sfh2ap: mailbox@8090000 { compatible = "cix,sky1-mbox"; reg = <0x0 0x08090000 0x0 0x10000>; -- 2.50.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* RE: [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support 2026-06-10 6:17 [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support joakim.zhang ` (4 preceding siblings ...) 2026-06-10 6:17 ` [PATCH v3 5/5] arm64: dts: cix: sky1: add audss system control joakim.zhang @ 2026-06-10 6:48 ` Joakim Zhang 5 siblings, 0 replies; 11+ messages in thread From: Joakim Zhang @ 2026-06-10 6:48 UTC (permalink / raw) To: Joakim Zhang, mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, Gary Yang Cc: cix-kernel-upstream, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sorry, I only checked the corresponding files, but forgot to do the overall check. make -j8 ARCH=arm64 CROSS_COMPILEaarch64-none-linux-gnu- dt_binding_check upstream/clk/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.example.dtb: clock-controller (cix,sky1-audss-clock): '#clock-cells' is a required property from schema $id: http://devicetree.org/schemas/clock/cix,sky1-audss-clock.yaml upstream/clk/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.example.dtb: clock-controller (cix,sky1-audss-clock): 'clocks' is a required property from schema $id: http://devicetree.org/schemas/clock/cix,sky1-audss-clock.yaml upstream/clk/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.example.dtb: clock-controller (cix,sky1-audss-clock): 'clock-names' is a required property from schema $id: http://devicetree.org/schemas/clock/cix,sky1-audss-clock.yaml upstream/clk/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.example.dtb: clock-controller (cix,sky1-audss-clock): 'resets' is a required property from schema $id: http://devicetree.org/schemas/clock/cix,sky1-audss-clock.yaml upstream/clk/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.example.dtb: clock-controller (cix,sky1-audss-clock): 'power-domains' is a required property from schema $id: http://devicetree.org/schemas/clock/cix,sky1-audss-clock.yaml I will fix it then resend the patch set. Joakim > -----Original Message----- > From: joakim.zhang@cixtech.com <joakim.zhang@cixtech.com> > Sent: Wednesday, June 10, 2026 2:17 PM > To: mturquette@baylibre.com; sboyd@kernel.org; bmasney@redhat.com; > robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; > p.zabel@pengutronix.de; Gary Yang <gary.yang@cixtech.com> > Cc: cix-kernel-upstream <cix-kernel-upstream@cixtech.com>; linux- > clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; Joakim Zhang > <joakim.zhang@cixtech.com> > Subject: [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support > > From: Joakim Zhang <joakim.zhang@cixtech.com> > > This patch set adds the clock and reset support for AUDSS. The AUDSS groups > audio-related peripherals (HDA, I2S, DSP, DMA, mailboxes, watchdog, timer, > etc.) behind a single Clock and Reset Unit (CRU) register block. > > Clock and reset changes normally belong to separate subsystems and would > ideally be submitted as independent series. They are combined here because > the AUDSS DT bindings cross-reference each other: the system-control binding > describes the clock child node, the clock binding documents reset lines exposed > on the parent syscon, and the DTS example wires both together. Keeping clock > and reset in one series gives reviewers the full picture when evaluating the > binding layout, dependencies, and integration. > > Patches apply in the following order: > > 1. Reset support > - dt-bindings: soc: cix,sky1-system-control: add audss system control > - reset: cix: add audss support to sky1 reset driver > > 2. Clock support > - dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller > - clk: cix: add sky1 audss clock controller > > 3. Device tree > - arm64: dts: cix: sky1: add audss system control > > The reset and clock parts have each been build-tested and checked with > dt_binding_check independently. If reviewers prefer separate series for the > reset and clock maintainers, I can split and resubmit after this round of review > once the overall design is agreed on. > > ChangeLogs: > v2->v3: > * clk part: > * devm_reset_control_get()->devm_reset_control_get_exclusive() > * assert noc reset from suspend > * clock parents changes from 6 to 4, and rename the clock names, > explain more about this: confirm with our designer, In fact, > there are 6 clock sources going into the audio subsystem. audio_clk1 > and audio_clk3 are redundant in design and are not actually needed > in practice, so they are not shown here. > * refine clocks and clock-names property > * add detailed description of clocks > * drop parent node from clk binding > * drop define AUDSS_MAX_CLKS > * reset part: > * rename reset signal macro, remove _N > * drop SKY1_AUDSS_SW_RESET_NUM > * switching to compatible-style of defining subnodes in parent schema > > v1->v2: > * remove audss_rst device node since it doesn't has resource, and > move to reset-sky1.c driver. > * remove hda related which would be sent after this patch set accepted > * soc componnet is okay by default from dtsi > * fix for audss clk driver: > * remove "comment "Clock options for Cixtech audss:"" > * add select MFD_SYSCON > * move lock and clk_data into struct sky1_audss_clks_priv > * const char *name -> const char * const * name > * remove CLK_GET_RATE_NOCACHE > * divicer -> divider > * Reverse Christmas tree order > * return reg ? 1 : 0; -> return !!reg; > * return ERR_CAST(hw); -> return hw; > * of_device_get_match_data(dev) -> device_get_match_data() > * add lock from runtime_suspend/resume > * loop to more mailing lists > > Joakim Zhang (5): > dt-bindings: soc: cix,sky1-system-control: add audss system control > reset: cix: add audss support to sky1 reset driver > dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller > clk: cix: add sky1 audss clock controller > arm64: dts: cix: sky1: add audss system control > > .../bindings/clock/cix,sky1-audss-clock.yaml | 80 ++ > .../soc/cix/cix,sky1-system-control.yaml | 47 +- > arch/arm64/boot/dts/cix/sky1.dtsi | 24 + > drivers/clk/Kconfig | 1 + > drivers/clk/Makefile | 1 + > drivers/clk/cix/Kconfig | 16 + > drivers/clk/cix/Makefile | 3 + > drivers/clk/cix/clk-sky1-audss.c | 1175 +++++++++++++++++ > drivers/reset/reset-sky1.c | 36 +- > include/dt-bindings/clock/cix,sky1-audss.h | 60 + > .../reset/cix,sky1-audss-system-control.h | 25 + > 11 files changed, 1461 insertions(+), 7 deletions(-) create mode 100644 > Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml > create mode 100644 drivers/clk/cix/Kconfig create mode 100644 > drivers/clk/cix/Makefile create mode 100644 drivers/clk/cix/clk-sky1-audss.c > create mode 100644 include/dt-bindings/clock/cix,sky1-audss.h > create mode 100644 include/dt-bindings/reset/cix,sky1-audss-system-control.h > > -- > 2.50.1 ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support
@ 2026-06-10 7:56 joakim.zhang
2026-06-10 7:56 ` [PATCH v3 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control joakim.zhang
0 siblings, 1 reply; 11+ messages in thread
From: joakim.zhang @ 2026-06-10 7:56 UTC (permalink / raw)
To: mturquette, sboyd, bmasney, robh, krzk+dt, conor+dt, p.zabel,
gary.yang
Cc: cix-kernel-upstream, linux-clk, devicetree, linux-kernel,
linux-arm-kernel, Joakim Zhang
From: Joakim Zhang <joakim.zhang@cixtech.com>
This patch set adds the clock and reset support for AUDSS. The AUDSS groups
audio-related peripherals (HDA, I2S, DSP, DMA, mailboxes, watchdog, timer, etc.)
behind a single Clock and Reset Unit (CRU) register block.
Clock and reset changes normally belong to separate subsystems and would
ideally be submitted as independent series. They are combined here because the
AUDSS DT bindings cross-reference each other: the system-control binding
describes the clock child node, the clock binding documents reset lines exposed
on the parent syscon, and the DTS example wires both together. Keeping clock
and reset in one series gives reviewers the full picture when evaluating the
binding layout, dependencies, and integration.
Patches apply in the following order:
1. Reset support
- dt-bindings: soc: cix,sky1-system-control: add audss system control
- reset: cix: add audss support to sky1 reset driver
2. Clock support
- dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller
- clk: cix: add sky1 audss clock controller
3. Device tree
- arm64: dts: cix: sky1: add audss system control
The reset and clock parts have each been build-tested and checked with
dt_binding_check independently. If reviewers prefer separate series for the
reset and clock maintainers, I can split and resubmit after this round of
review once the overall design is agreed on.
---
ChangeLogs:
v2->v3:
* clk part:
* devm_reset_control_get()->devm_reset_control_get_exclusive()
* assert noc reset from suspend
* clock parents changes from 6 to 4, and rename the clock names,
explain more about this: confirm with our designer, In fact,
there are 6 clock sources going into the audio subsystem. audio_clk1
and audio_clk3 are redundant in design and are not actually needed
in practice, so they are not shown here.
* refine clocks and clock-names property
* add detailed description of clocks
* drop parent node from clk binding
* drop define AUDSS_MAX_CLKS
* reset part:
* rename reset signal macro, remove _N
* drop SKY1_AUDSS_SW_RESET_NUM
* switching to compatible-style of defining subnodes in parent schema
v1->v2:
* remove audss_rst device node since it doesn't has resource, and
move to reset-sky1.c driver.
* remove hda related which would be sent after this patch set accepted
* soc componnet is okay by default from dtsi
* fix for audss clk driver:
* remove "comment "Clock options for Cixtech audss:""
* add select MFD_SYSCON
* move lock and clk_data into struct sky1_audss_clks_priv
* const char *name -> const char * const * name
* remove CLK_GET_RATE_NOCACHE
* divicer -> divider
* Reverse Christmas tree order
* return reg ? 1 : 0; -> return !!reg;
* return ERR_CAST(hw); -> return hw;
* of_device_get_match_data(dev) -> device_get_match_data()
* add lock from runtime_suspend/resume
* loop to more mailing lists
Joakim Zhang (5):
dt-bindings: soc: cix,sky1-system-control: add audss system control
reset: cix: add audss support to sky1 reset driver
dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller
clk: cix: add sky1 audss clock controller
arm64: dts: cix: sky1: add audss system control
.../bindings/clock/cix,sky1-audss-clock.yaml | 80 ++
.../soc/cix/cix,sky1-system-control.yaml | 47 +-
arch/arm64/boot/dts/cix/sky1.dtsi | 24 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/cix/Kconfig | 16 +
drivers/clk/cix/Makefile | 3 +
drivers/clk/cix/clk-sky1-audss.c | 1175 +++++++++++++++++
drivers/reset/reset-sky1.c | 36 +-
include/dt-bindings/clock/cix,sky1-audss.h | 60 +
.../reset/cix,sky1-audss-system-control.h | 25 +
11 files changed, 1461 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml
create mode 100644 drivers/clk/cix/Kconfig
create mode 100644 drivers/clk/cix/Makefile
create mode 100644 drivers/clk/cix/clk-sky1-audss.c
create mode 100644 include/dt-bindings/clock/cix,sky1-audss.h
create mode 100644 include/dt-bindings/reset/cix,sky1-audss-system-control.h
--
2.50.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v3 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control 2026-06-10 7:56 joakim.zhang @ 2026-06-10 7:56 ` joakim.zhang 0 siblings, 0 replies; 11+ messages in thread From: joakim.zhang @ 2026-06-10 7:56 UTC (permalink / raw) To: mturquette, sboyd, bmasney, robh, krzk+dt, conor+dt, p.zabel, gary.yang Cc: cix-kernel-upstream, linux-clk, devicetree, linux-kernel, linux-arm-kernel, Joakim Zhang From: Joakim Zhang <joakim.zhang@cixtech.com> The Cix Sky1 Audio Subsystem (AUDSS) groups audio-related clock, reset and control registers in a dedicated CRU block. Software reset lines are exposed on the syscon parent via #reset-cells, following the same model as the existing Sky1 FCH and S5 system control bindings. Add the cix,sky1-audss-system-control compatible to cix,sky1-system-control.yaml for the MFD/syscon parent node, and define AUDSS software reset indices in include/dt-bindings/reset/cix,sky1-audss-system-control.h for I2S, HDA, DMAC, mailbox, watchdog and timer blocks. Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com> --- .../soc/cix/cix,sky1-system-control.yaml | 52 +++++++++++++++++-- .../reset/cix,sky1-audss-system-control.h | 25 +++++++++ 2 files changed, 72 insertions(+), 5 deletions(-) create mode 100644 include/dt-bindings/reset/cix,sky1-audss-system-control.h diff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml index a01a515222c6..61d26a69fd44 100644 --- a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml +++ b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml @@ -15,11 +15,16 @@ description: properties: compatible: - items: - - enum: - - cix,sky1-system-control - - cix,sky1-s5-system-control - - const: syscon + oneOf: + - items: + - enum: + - cix,sky1-system-control + - cix,sky1-s5-system-control + - const: syscon + - items: + - const: cix,sky1-audss-system-control + - const: simple-mfd + - const: syscon reg: maxItems: 1 @@ -27,6 +32,28 @@ properties: '#reset-cells': const: 1 + clock-controller: + type: object + properties: + compatible: + const: cix,sky1-audss-clock + required: + - compatible + additionalProperties: true + +allOf: + - if: + properties: + compatible: + contains: + const: cix,sky1-audss-system-control + then: + required: + - clock-controller + else: + properties: + clock-controller: false + required: - compatible - reg @@ -40,3 +67,18 @@ examples: reg = <0x4160000 0x100>; #reset-cells = <1>; }; + - | + audss_syscon: system-controller@7110000 { + compatible = "cix,sky1-audss-system-control", "simple-mfd", "syscon"; + reg = <0x7110000 0x10000>; + #reset-cells = <1>; + + clock-controller { + compatible = "cix,sky1-audss-clock"; + power-domains = <&smc_devpd 0>; + #clock-cells = <1>; + clocks = <&scmi_clk 0>, <&scmi_clk 2>, <&scmi_clk 4>, <&scmi_clk 5>; + clock-names = "x8k", "x11k", "sys", "48m"; + resets = <&s5_syscon 31>; + }; + }; diff --git a/include/dt-bindings/reset/cix,sky1-audss-system-control.h b/include/dt-bindings/reset/cix,sky1-audss-system-control.h new file mode 100644 index 000000000000..aabdce60b094 --- /dev/null +++ b/include/dt-bindings/reset/cix,sky1-audss-system-control.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright 2026 Cix Technology Group Co., Ltd. + */ +#ifndef DT_BINDING_RESET_CIX_SKY1_AUDSS_SYSTEM_CONTROL_H +#define DT_BINDING_RESET_CIX_SKY1_AUDSS_SYSTEM_CONTROL_H + +#define AUDSS_I2S0_SW_RST 0 +#define AUDSS_I2S1_SW_RST 1 +#define AUDSS_I2S2_SW_RST 2 +#define AUDSS_I2S3_SW_RST 3 +#define AUDSS_I2S4_SW_RST 4 +#define AUDSS_I2S5_SW_RST 5 +#define AUDSS_I2S6_SW_RST 6 +#define AUDSS_I2S7_SW_RST 7 +#define AUDSS_I2S8_SW_RST 8 +#define AUDSS_I2S9_SW_RST 9 +#define AUDSS_WDT_SW_RST 10 +#define AUDSS_TIMER_SW_RST 11 +#define AUDSS_MB0_SW_RST 12 +#define AUDSS_MB1_SW_RST 13 +#define AUDSS_HDA_SW_RST 14 +#define AUDSS_DMAC_SW_RST 15 + +#endif -- 2.50.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2026-06-10 7:56 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-06-10 6:17 [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support joakim.zhang 2026-06-10 6:17 ` [PATCH v3 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control joakim.zhang 2026-06-10 6:25 ` sashiko-bot 2026-06-10 6:17 ` [PATCH v3 2/5] reset: cix: add audss support to sky1 reset driver joakim.zhang 2026-06-10 6:17 ` [PATCH v3 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller joakim.zhang 2026-06-10 6:24 ` sashiko-bot 2026-06-10 6:17 ` [PATCH v3 4/5] clk: cix: add sky1 " joakim.zhang 2026-06-10 6:29 ` sashiko-bot 2026-06-10 6:17 ` [PATCH v3 5/5] arm64: dts: cix: sky1: add audss system control joakim.zhang 2026-06-10 6:48 ` [PATCH v3 0/5] Add Cix Sky1 AUDSS clock and reset support Joakim Zhang -- strict thread matches above, loose matches on Subject: below -- 2026-06-10 7:56 joakim.zhang 2026-06-10 7:56 ` [PATCH v3 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control joakim.zhang
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