[PATCH 0/4] arm64: dts: imx8qm: collect some small update and fixes

[PATCH 0/4] arm64: dts: imx8qm: collect some small update and fixes

[Frank.Li]

Collect some small update and fixes.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Frank Li (4):
      arm64: dts: imx8qm-ss-dma: add lpuart4 node
      arm64: dts: imx8qm-ss-audio: add spdif1 node
      arm64: dts: imx8qm-ss-lsio: add lsio mu6,8,8b
      arm64: dts: imx8-ss-audio: Fix LPCG clock indices for ASRC0

 arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi   |  8 ++---
 arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi | 38 ++++++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi   | 16 +++++++++
 arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi  | 29 +++++++++++++++++
 4 files changed, 87 insertions(+), 4 deletions(-)
---
base-commit: 31bd73273b9bf03a3fe32227b417f00d4a94c6ac
change-id: 20260706-qm_dts-043646b4675b

Best regards,
--  
Frank Li <Frank.Li@nxp.com>

[PATCH 1/4] arm64: dts: imx8qm-ss-dma: add lpuart4 node

[Frank.Li]

From: Frank Li <Frank.Li@nxp.com>

Add lpuart4 node for imx8qm.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
index 974e193f8dcb9..caa2a7f89ab99 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
@@ -8,6 +8,22 @@
 /delete-node/ &adma_pwm_lpcg;
 
 &dma_subsys {
+	lpuart4: serial@5a0a0000 {
+		compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
+		reg = <0x5a0a0000 0x1000>;
+		interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&uart4_lpcg IMX_LPCG_CLK_4>, <&uart4_lpcg IMX_LPCG_CLK_0>;
+		clock-names = "ipg", "baud";
+		assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd IMX_SC_R_UART_4>;
+		power-domain-names = "uart";
+		dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 21 0 0>;
+		dma-names = "rx","tx";
+		status = "disabled";
+	};
+
 	uart4_lpcg: clock-controller@5a4a0000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x5a4a0000 0x10000>;

-- 
2.43.0

[PATCH 2/4] arm64: dts: imx8qm-ss-audio: add spdif1 node

[Frank.Li]

From: Frank Li <Frank.Li@nxp.com>

Add spdif1 and related lpcg node for imx8qm.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi | 38 ++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
index 7c5386d4ab2b7..5cb644837d936 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
@@ -74,6 +74,31 @@ &asrc1_lpcg {
 };
 
 &audio_subsys {
+	spdif1: spdif@59030000 {
+		compatible = "fsl,imx8qm-spdif";
+		reg = <0x59030000 0x10000>;
+		interrupts =  <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, /* rx */
+			      <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+		clocks = <&spdif1_lpcg IMX_LPCG_CLK_4>, /* core */
+			 <&clk_dummy>, /* rxtx0 */
+			 <&spdif1_lpcg IMX_LPCG_CLK_5>, /* rxtx1 */
+			 <&clk_dummy>, /* rxtx2 */
+			 <&clk_dummy>, /* rxtx3 */
+			 <&clk_dummy>, /* rxtx4 */
+			 <&audio_ipg_clk>, /* rxtx5 */
+			 <&clk_dummy>, /* rxtx6 */
+			 <&clk_dummy>, /* rxtx7 */
+			 <&clk_dummy>; /* spba */
+		clock-names = "core", "rxtx0",
+			      "rxtx1", "rxtx2",
+			      "rxtx3", "rxtx4",
+			      "rxtx5", "rxtx6",
+			      "rxtx7", "spba";
+		dmas = <&edma0 10 0 5>, <&edma0 11 0 4>;
+		dma-names = "rx", "tx";
+		power-domains = <&pd IMX_SC_R_SPDIF_1>;
+		status = "disabled";
+	};
 
 	sai4: sai@59080000 {
 		compatible = "fsl,imx8qm-sai";
@@ -109,6 +134,19 @@ sai5: sai@59090000 {
 		status = "disabled";
 	};
 
+	spdif1_lpcg: clock-controller@59430000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x59430000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>,
+			 <&audio_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_4>;
+		clock-output-names = "spdif1_lpcg_tx_clk",
+				     "spdif1_lpcg_gclkw";
+		power-domains = <&pd IMX_SC_R_SPDIF_1>;
+		status = "disabled";
+	};
+
 	sai4_lpcg: clock-controller@59480000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x59480000 0x10000>;

-- 
2.43.0

[PATCH 3/4] arm64: dts: imx8qm-ss-lsio: add lsio mu6,8,8b

[Frank.Li]

From: Frank Li <Frank.Li@nxp.com>

Add mu6,8,8b mailbox nodes.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi | 29 +++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
index b483134f84d18..fb503c93447d1 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
@@ -3,6 +3,35 @@
  * Copyright 2019-2020 NXP
  *	Dong Aisheng <aisheng.dong@nxp.com>
  */
+&lsio_subsys {
+	lsio_mu6: mailbox@5d210000 {
+		compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+		reg = <0x5d210000 0x10000>;
+		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <2>;
+		power-domains = <&pd IMX_SC_R_MU_6A>;
+	};
+
+	lsio_mu8: mailbox@5d230000 {
+		compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+		reg = <0x5d230000 0x10000>;
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <2>;
+		power-domains = <&pd IMX_SC_R_MU_8A>;
+		status = "disabled";
+	};
+
+	lsio_mu8b: mailbox@5d2c0000 {
+		compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+		reg = <0x5d2c0000 0x10000>;
+		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <2>;
+		fsl,mu-side-b;
+		power-domains = <&pd IMX_SC_R_MU_8B>;
+		status = "disabled";
+	};
+
+};
 
 &lsio_gpio0 {
 	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";

-- 
2.43.0

[PATCH 4/4] arm64: dts: imx8-ss-audio: Fix LPCG clock indices for ASRC0

[Frank.Li]

From: Frank Li <Frank.Li@nxp.com>

The LPCG clock indices for ASRC0 and AUD_PLL_DIV0 are swapped. The ASRC0
LPCG provides only IMX_LPCG_CLK_4, so update the ASRC0 clock consumer to
use IMX_LPCG_CLK_4 instead of the non-existent IMX_LPCG_CLK_0.

Likewise, the AUD_PLL_DIV0 LPCG provides only IMX_LPCG_CLK_0, so update its
clock consumer to use IMX_LPCG_CLK_0 instead of the non-existent
IMX_LPCG_CLK_4.

Fixes: 5125617c7a4d3 ("arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif0 and sai[4,5]")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
index 5e4233ccfde46..f473d81f67ffa 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
@@ -124,10 +124,10 @@ asrc0: asrc@59000000 {
 		compatible = "fsl,imx8qm-asrc";
 		reg = <0x59000000 0x10000>;
 		interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>,
-			 <&asrc0_lpcg IMX_LPCG_CLK_0>,
-			 <&aud_pll_div0_lpcg IMX_LPCG_CLK_4>,
-			 <&aud_pll_div1_lpcg IMX_LPCG_CLK_4>,
+		clocks = <&asrc0_lpcg IMX_LPCG_CLK_4>,
+			 <&asrc0_lpcg IMX_LPCG_CLK_4>,
+			 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
+			 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
 			 <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
 			 <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
 			 <&clk_dummy>,

-- 
2.43.0

Re: [PATCH 1/4] arm64: dts: imx8qm-ss-dma: add lpuart4 node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The newly added `lpuart4` node includes a `power-domain-names` property which is undocumented in the `fsl-lpuart.yaml` device tree binding, causing a devicetree schema validation failure.
--

--- Patch [1]: [PATCH 1/4] arm64: dts: imx8qm-ss-dma: add lpuart4 node ---
commit 5d53e06892d921423b269317c3426f0a50c063e7
Author: Frank Li <Frank.Li@nxp.com>

arm64: dts: imx8qm-ss-dma: add lpuart4 node
    
This commit adds the lpuart4 node for the imx8qm SoC to the imx8qm-ss-dma.dtsi
device tree source.

> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
> --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
> @@ -8,6 +8,22 @@
>  /delete-node/ &adma_pwm_lpcg;
>  
>  &dma_subsys {
> +	lpuart4: serial@5a0a0000 {
> +		compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
> +		reg = <0x5a0a0000 0x1000>;
[ ... ]
> +		assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates = <80000000>;
> +		power-domains = <&pd IMX_SC_R_UART_4>;
> +		power-domain-names = "uart";

[Severity: Low]
Is this power-domain-names property strictly necessary here? 

This property is undocumented in the fsl-lpuart.yaml device tree binding,
which restricts allowed properties. As a result, including it causes a
devicetree schema validation failure during dtbs_check. 

Since there is only a single power domain specified for lpuart4, the kernel
PM core handles it automatically without needing it to be explicitly named.

> +		dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 21 0 0>;
> +		dma-names = "rx","tx";
> +		status = "disabled";
> +	};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260706-qm_dts-v1-0-14117a48fbdb@nxp.com?part=1

Re: [PATCH 3/4] arm64: dts: imx8qm-ss-lsio: add lsio mu6,8,8b

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Redundant re-declaration of the `lsio_mu6` node and label.
--

--- Patch [3]: [PATCH 3/4] arm64: dts: imx8qm-ss-lsio: add lsio mu6,8,8b ---
commit e95e394180e13045095ad2b094d537158b113f5c
Author: Frank Li <Frank.Li@nxp.com>

arm64: dts: imx8qm-ss-lsio: add lsio mu6,8,8b

This commit adds mu6, 8, and 8b mailbox nodes to the imx8qm-ss-lsio
device tree.

> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
> index b483134f84d18..fb503c93447d1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
> @@ -3,6 +3,35 @@
>   * Copyright 2019-2020 NXP
>   *	Dong Aisheng <aisheng.dong@nxp.com>
>   */
> +&lsio_subsys {
> +	lsio_mu6: mailbox@5d210000 {
> +		compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
> +		reg = <0x5d210000 0x10000>;
> +		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
> +		#mbox-cells = <2>;
> +		power-domains = <&pd IMX_SC_R_MU_6A>;
> +	};

[Severity: Low]
Is this full node definition for lsio_mu6 redundant?

The properties defined here, such as reg, interrupts, #mbox-cells, and
power-domains, appear to already be inherited from the base imx8-ss-lsio.dtsi
file. Furthermore, the QM-specific compatibles are already applied via a
reference at the bottom of this file.

Could this block be safely omitted to avoid duplication? As it currently
stands, it also does not override the status = "disabled" property from the
base file, which might mean the mailbox is still left disabled.

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260706-qm_dts-v1-0-14117a48fbdb@nxp.com?part=3