[PATCH 0/5] drm/panel: jd9365da: add support for DCLTek DT300250

[PATCH 0/5] drm/panel: jd9365da: add support for DCLTek DT300250

[Marc-Olivier Champagne]

This series adds support for the DCLTek DT300250 9.35-inch MIPI DSI
panel based on the Jadard JD9365DA-H3 controller.

The series includes the prerequisites needed by this panel support:
enable LPM mode for the jd9365da path and add the prepare_prev_first
flag to drm_panel. It then adds the dcltek vendor prefix, documents
the new compatible string in the binding, and finally adds the panel
descriptor and initialization sequence to the driver.

Marc-Olivier Champagne (5):
  drm: panel: jd9365da: Enable LPM mode
  drm: panel: jd9365da: Add prepare_prev_first flag to drm_panel
  dt-bindings: vendor-prefixes: Add DCLTEK
  dt-bindings: display: panel: add compatible for DCLTek 300250 9.35in
    panel
  drm: panel: jd9365da: Add DCLTek 300250 9.35in display

 .../display/panel/jadard,jd9365da-h3.yaml     |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 .../gpu/drm/panel/panel-jadard-jd9365da-h3.c  | 251 +++++++++++++++++-
 3 files changed, 253 insertions(+), 1 deletion(-)


base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
-- 
2.34.1

[PATCH 1/5] drm: panel: jd9365da: Enable LPM mode

[Marc-Olivier Champagne]

The JD9365DA-H3 uses DSI LPM for command transmissions, make sure
this is configured correctly in the DSI mode flags.

Suggested-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Signed-off-by: Marc-Olivier Champagne <marc-olivier.champagne@savoirfairelinux.com>
---
 drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
index f6b04de1182e..1ef0c937863a 100644
--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
@@ -2950,7 +2950,8 @@ static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
 	else
 		dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
 				  MIPI_DSI_MODE_VIDEO_BURST |
-				  MIPI_DSI_MODE_NO_EOT_PACKET;
+				  MIPI_DSI_MODE_NO_EOT_PACKET |
+				  MIPI_DSI_MODE_LPM;
 
 	dsi->format = desc->format;
 	dsi->lanes = desc->lanes;
-- 
2.34.1

[PATCH 2/5] drm: panel: jd9365da: Add prepare_prev_first flag to drm_panel

[Marc-Olivier Champagne]

The DSI host must be enabled for the panel to be initialized in
prepare(). Set the prepare_prev_first flag to guarantee this.
This fixes the panel operation on Renesas RZ/G2LC SoC DSI host.

Suggested-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Signed-off-by: Marc-Olivier Champagne <marc-olivier.champagne@savoirfairelinux.com>
---
 drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
index 1ef0c937863a..a79dc8f8d5af 100644
--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
@@ -2993,6 +2993,8 @@ static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
 		return dev_err_probe(&dsi->dev, PTR_ERR(jadard->vccio),
 				"failed to get vccio regulator\n");
 
+	jadard->panel.prepare_prev_first = true;
+
 	ret = of_drm_get_panel_orientation(dev->of_node, &jadard->orientation);
 	if (ret < 0)
 		return dev_err_probe(dev, ret, "failed to get orientation\n");
-- 
2.34.1

[PATCH 3/5] dt-bindings: vendor-prefixes: Add DCLTEK

[Marc-Olivier Champagne]

Add DCL Technologies Inc. (DCLTEK) to the devicetree vendor prefixes
registry.

Link: https://www.dcltek.com/

Signed-off-by: Marc-Olivier Champagne <marc-olivier.champagne@savoirfairelinux.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 396044f368e7..1e7af6de2afe 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -407,6 +407,8 @@ patternProperties:
     description: DataImage, Inc.
   "^davicom,.*":
     description: DAVICOM Semiconductor, Inc.
+  "^dcltek,.*":
+    description: DCL Technologies Inc.
   "^deepcomputing,.*":
     description: DeepComputing (HK) Limited
   "^dell,.*":
-- 
2.34.1

[PATCH 4/5] dt-bindings: display: panel: add compatible for DCLTek 300250 9.35in panel

[Marc-Olivier Champagne]

The DCLTek dt300250 is a panel using the jadard-jd9365da controller.
Add a new compatible for it.

Suggested-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Signed-off-by: Marc-Olivier Champagne <marc-olivier.champagne@savoirfairelinux.com>
---
 .../devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml    | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
index 4eae802de9fd..9e20e2faf82f 100644
--- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
+++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
@@ -19,6 +19,7 @@ properties:
           - anbernic,rg-ds-display-bottom
           - anbernic,rg-ds-display-top
           - chongzhou,cz101b4001
+          - dcltek,dt300250
           - kingdisplay,kd101ne3-40ti
           - melfas,lmfbx101117480
           - radxa,display-10hd-ad001
-- 
2.34.1

[PATCH 5/5] drm: panel: jd9365da: Add DCLTek 300250 9.35in display

[Marc-Olivier Champagne]

The DCLTek dt300250 is a LCD panel using the jd9365da controller.
Add the panel to the driver.

Suggested-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Signed-off-by: Marc-Olivier Champagne <marc-olivier.champagne@savoirfairelinux.com>
---
 .../gpu/drm/panel/panel-jadard-jd9365da-h3.c  | 246 ++++++++++++++++++
 1 file changed, 246 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
index a79dc8f8d5af..970c64d6054d 100644
--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
@@ -2931,6 +2931,248 @@ static const struct jadard_panel_desc waveshare_10_1_inch_b_desc = {
 		MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
 };
 
+static int dcltek_dt300250_init_cmds(struct jadard *jadard)
+{
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
+
+	jd9365da_switch_page(&dsi_ctx, 0x00);
+	jadard_enable_standard_cmds(&dsi_ctx);
+
+	jd9365da_switch_page(&dsi_ctx, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x2B);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x2B);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xCF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xCF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xFE);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x5C);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x7F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x02);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xC8);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x66);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x10);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x8D);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x29);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x1A);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x7F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x65);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x53);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x45);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x3E);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x30);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x33);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x3B);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x3C);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x3F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x5D);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x49);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x4D);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x3D);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x37);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x28);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x15);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x65);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x53);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x45);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x3E);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x30);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x33);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3B);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x3C);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x3F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x5D);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x49);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x4D);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x3D);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x44);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x28);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x15);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00);
+
+	jd9365da_switch_page(&dsi_ctx, 0x02);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x41);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x4B);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x5C);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x5A);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x47);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x4F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x45);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4D);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x5E);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x51);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x4A);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x5B);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x48);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x59);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x46);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x4E);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4C);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x5E);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x50);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x5F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2C, 0x10);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2D, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2E, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2F, 0x0C);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x0E);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x06);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x1B);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0x0A);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0x1E);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x11);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x0D);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x05);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x0F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4A, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x07);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4C, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4D, 0x1A);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4E, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4F, 0x09);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x1C);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x0B);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x1E);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x10);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x70);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x70);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x06);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x4A);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x56);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x4F);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0xF7);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x01);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x06);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x4A);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x10);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x00);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88);
+
+	jd9365da_switch_page(&dsi_ctx, 0x04);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x4A);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0F);
+
+	jd9365da_switch_page(&dsi_ctx, 0x05);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x34);
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x76);
+
+	jd9365da_switch_page(&dsi_ctx, 0x00);
+
+	mipi_dsi_msleep(&dsi_ctx, 120);
+
+	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+
+	mipi_dsi_msleep(&dsi_ctx, 120);
+
+	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+
+	mipi_dsi_msleep(&dsi_ctx, 20);
+
+	mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+
+	return dsi_ctx.accum_err;
+}
+
+static const struct jadard_panel_desc dcltek_dt300250_desc = {
+	.mode_4ln = &(const struct drm_display_mode) {
+		.clock		= (600 + 48 + 32 + 80) * (1600 + 18 + 6 + 23) * 60 / 1000,
+
+		.hdisplay	= 600,
+		.hsync_start	= 600 + 48,
+		.hsync_end	= 600 + 48 + 32,
+		.htotal		= 600 + 48 + 32 + 80,
+
+		.vdisplay	= 1600,
+		.vsync_start	= 1600 + 18,
+		.vsync_end	= 1600 + 18 + 6,
+		.vtotal		= 1600 + 18 + 6 + 23,
+
+		.width_mm	= 83,
+		.height_mm	= 221,
+		.type		= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+	},
+	.lanes = 4,
+	.format = MIPI_DSI_FMT_RGB888,
+	.init = dcltek_dt300250_init_cmds,
+};
+
 static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
 {
 	struct device *dev = &dsi->dev;
@@ -3039,6 +3281,10 @@ static const struct of_device_id jadard_of_match[] = {
 		.compatible = "chongzhou,cz101b4001",
 		.data = &cz101b4001_desc
 	},
+	{
+		.compatible = "dcltek,dt300250",
+		.data = &dcltek_dt300250_desc
+	},
 	{
 		.compatible = "kingdisplay,kd101ne3-40ti",
 		.data = &kingdisplay_kd101ne3_40ti_desc
-- 
2.34.1

Re: [PATCH 2/5] drm: panel: jd9365da: Add prepare_prev_first flag to drm_panel

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [Low] Redundant duplicate assignment of `prepare_prev_first` flag.

Pre-existing issues:
- [High] Missing cleanup in the error paths of `jadard_prepare()` causes a permanent leak of the regulator enable counts.
- [High] Premature publication of the panel in `jadard_dsi_probe()` allows a race condition leading to a NULL pointer dereference.
--

--- Patch [2]: [PATCH 2/5] drm: panel: jd9365da: Add prepare_prev_first flag to drm_panel ---
commit 1a793dbc7476444fc7003da84dbce8a3bff9ad98
Author: Marc-Olivier Champagne <marc-olivier.champagne@savoirfairelinux.com>

drm: panel: jd9365da: Add prepare_prev_first flag to drm_panel

The DSI host must be enabled for the panel to be initialized in
prepare(). Set the prepare_prev_first flag to guarantee this.
This fixes the panel operation on Renesas RZ/G2LC SoC DSI host.

> diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
> index 1ef0c937863a2..a79dc8f8d5af9 100644
> --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
> +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
> @@ -2993,6 +2993,8 @@ static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
>  		return dev_err_probe(&dsi->dev, PTR_ERR(jadard->vccio),
>  				"failed to get vccio regulator\n");
>  
> +	jadard->panel.prepare_prev_first = true;
> +

[Severity: Low]
Does this introduce a redundant assignment?

Looking further down in jadard_dsi_probe(), the exact same flag appears to be
set again just before panel registration:

jadard_dsi_probe() {
	...
	jadard->panel.prepare_prev_first = true;

	drm_panel_add(&jadard->panel);
	...
}

Can we remove one of these duplicate assignments?

[Severity: High]
This is a pre-existing issue, but does jadard_prepare() leak regulator
reference counts on error paths?

If regulator_enable(jadard->vccio) succeeds, but a subsequent step fails:

jadard_prepare() {
	...
	ret = regulator_enable(jadard->vccio);
	...
	ret = regulator_enable(jadard->vdd);
	if (ret)
		return ret;

and later with mipi_dsi_dcs_nop():

	ret = mipi_dsi_dcs_nop(jadard->dsi);
	if (ret)
		return ret;
}

The function returns without disabling the previously enabled regulators.
Because the panel prepare fails, the DRM core won't mark it as prepared, and
jadard_unprepare() will never be called to clean up.
    
Can this prevent the system from entering low-power states or re-initializing
the display properly?

[Severity: High]
This isn't a bug introduced by this patch, but is there a race condition with
premature panel publication in jadard_dsi_probe()?

The panel is added to the global list before its required internal pointers
are initialized:

jadard_dsi_probe() {
	...
	drm_panel_add(&jadard->panel);

	mipi_dsi_set_drvdata(dsi, jadard);
	jadard->dsi = dsi;
	jadard->desc = desc;
}

If a display controller finds the panel concurrently (e.g., via probe deferral
resolution) and calls drm_panel_prepare(), jadard_prepare() could execute
before jadard_dsi_probe() finishes:

jadard_prepare() {
	...
	if (jadard->desc->vcioo_to_lp11_delay_ms)
	...
}

Can this dereference a NULL jadard->desc pointer? Should drm_panel_add() be
moved to the very end of the probe function?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260708213500.1867092-1-marc-olivier.champagne@savoirfairelinux.com?part=2

Re: [PATCH 4/5] dt-bindings: display: panel: add compatible for DCLTek 300250 9.35in panel

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The newly added compatible string `dcltek,dt300250` will not be probed by the panel driver due to missing `of_match_table` entry.
- [Low] Redundant assignment of `jadard->panel.prepare_prev_first = true;`.
--

--- Patch [4]: [PATCH 4/5] dt-bindings: display: panel: add compatible for DCLTek 300250 9.35in panel ---
commit eaec789ca9baff9cff690aca5a539d1f1eb81d5f
Author: Marc-Olivier Champagne <marc-olivier.champagne@savoirfairelinux.com>

dt-bindings: display: panel: add compatible for DCLTek 300250 9.35in panel

The DCLTek dt300250 is a panel using the jadard-jd9365da controller.
Add a new compatible for it.

> diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
> index 4eae802de9fd5..9e20e2faf82fa 100644
> --- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
> +++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
> @@ -19,6 +19,7 @@ properties:
>            - anbernic,rg-ds-display-bottom
>            - anbernic,rg-ds-display-top
>            - chongzhou,cz101b4001
> +          - dcltek,dt300250

[Severity: Medium]
Will the panel driver successfully bind to this new compatible string?

Looking at jadard_of_match in drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c,
it seems neither this new compatible string nor a generic fallback is present
in the match table:

drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c:jadard_of_match[] = {
    {
        .compatible = "anbernic,rg-ds-display-bottom",
        ...

Without a matching entry in the of_match_table, does this regression cause
the device to fail to probe?


[Severity: Low]
Looking at the driver changes introduced earlier in this series by commit
1a793dbc7476, is there a redundant assignment to prepare_prev_first?

drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c:jadard_dsi_probe() {
    ...
    jadard->panel.prepare_prev_first = true;
    ...
    jadard->panel.prepare_prev_first = true;
    ...
}

Could this regression be a duplicated assignment in the same function?

>            - kingdisplay,kd101ne3-40ti
>            - melfas,lmfbx101117480
>            - radxa,display-10hd-ad001

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260708213500.1867092-1-marc-olivier.champagne@savoirfairelinux.com?part=4