Re: [PATCH v5 1/7] arm64: dts: qcom: Add device tree for Nord SoC series

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] The UFS host controller node specifies a unit address but is missing a `reg` property.
- [Low] The `watchdog@17826000` node references a `sleep_clk` clock label, but this label/phandle is not defined anywhere in the SoC `.dtsi`.
- [Low] The SPI controller nodes within the QUPv3 wrappers are missing the mandatory `#address-cells` and `#size-cells` properties.
- [Low] The QUPv3 wrapper and serial engine nodes (`i2c`, `spi`, `uart`) are missing mandatory `clocks` and `clock-names` properties.
--

--- Patch [1]: [PATCH v5 1/7] arm64: dts: qcom: Add device tree for Nord SoC series ---
commit 85da8a1968eae51c682bf41212bb6ddfbb6a4ee8
Author: Shawn Guo <shengchao.guo@oss.qualcomm.com>

arm64: dts: qcom: Add device tree for Nord SoC series

This commit adds the base device tree include (nord.dtsi) for the Nord SoC
series, describing core hardware components like Oryon cores, GICv3, TLMM,
SMMU, and QUP blocks.

> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> new file mode 100644
> index 0000000000000..716297bcc9a63
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi

[ ... ]

> +		qupv3_2: geniqup@8c0000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0x0 0x008c0000 0x0 0x2000>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			iommus = <&apps_smmu_0 0x15a3 0x0>;
> +			ranges;

[Severity: Low]
The QUPv3 wrapper and its child serial engine nodes (i2c, spi, uart) appear to
be missing the mandatory clocks and clock-names properties. Are dummy or fixed
clocks needed here to prevent dtbs_check validation errors if the clock
controller is not yet available?

[ ... ]

> +			spi14: spi@880000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x0 0x00880000 0x0 0x4000>;
> +				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
> +
> +				status = "disabled";
> +			};

[Severity: Low]
This spi node, and others throughout the file, seems to be missing the
#address-cells = <1> and #size-cells = <0> properties. Without these, won't
child peripheral nodes fail to specify their chip select addresses, causing
dtbs_check schema validation errors?

[ ... ]

> +		ufs_mem_hc: ufshc@1d44000 {
> +			compatible = "qcom,nord-ufshc",
> +				     "qcom,ufshc",
> +				     "jedec,ufs-2.0";
> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> +			lanes-per-direction = <2>;
> +			iommus = <&apps_smmu_0 0x14c0 0x0>;
> +			dma-coherent;
> +			msi-parent = <&gic_its 0x14c0>;
> +		};

[Severity: High]
Does this UFS host controller node need a reg property? Since it specifies a
unit address (ufshc@1d44000), omitting the reg property violates the device
tree specification.

Could this also cause the ufshc driver probe to fail when it attempts to
fetch the MMIO base?

[ ... ]

> +		watchdog@17826000 {
> +			compatible = "qcom,apss-wdt-nord",
> +				     "qcom,kpss-wdt";
> +			reg = <0x0 0x17826000 0x0 0x1000>;
> +			clocks = <&sleep_clk>;
> +			interrupts = <GIC_ESPI 848 IRQ_TYPE_EDGE_RISING>;
> +		};

[Severity: Low]
The clocks property references &sleep_clk, but this phandle does not appear
to be defined anywhere in this SoC .dtsi.

If a board file includes this file without explicitly declaring sleep_clk,
will it cause a dtc compilation error for a non-existent node or label?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260709132013.4096850-1-shengchao.guo@oss.qualcomm.com?part=1