Re: [PATCH v5 7/7] arm64: dts: qcom: Add device tree for IQ10 RRD board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] UFS reset GPIO pin index out of bounds for `gpio-ranges` in base devicetree.
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--- Patch [7]: [PATCH v5 7/7] arm64: dts: qcom: Add device tree for IQ10 RRD board ---
commit ba7031927b18197ba50b6046132b0fba1999d651
Author: Shawn Guo <shengchao.guo@oss.qualcomm.com>

arm64: dts: qcom: Add device tree for IQ10 RRD board

This patch adds the initial device tree for the Qualcomm IQ10 RRD board, built
on the Nord Embedded variant. It enables the debug UART, UFS storage, PMICs,
I2C, and SPI.

> diff --git a/arch/arm64/boot/dts/qcom/iq10-rrd.dts b/arch/arm64/boot/dts/qcom/iq10-rrd.dts
> new file mode 100644
> index 0000000000000..39d254b49c147
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/iq10-rrd.dts
[ ... ]
> +&ufs_mem_hc {
> +	reset-gpios = <&tlmm 181 GPIO_ACTIVE_LOW>;

[Severity: Low]
Does this requested GPIO exceed the mapped gpio-ranges?

Looking at nord.dtsi, the gpio-ranges count is 181, which only covers
indices 0 through 180:

arch/arm64/boot/dts/qcom/nord.dtsi:tlmm {
        ...
        gpio-ranges = <&tlmm 0 0 181>;
        ...
}

Since the UFS reset pin is at index 181, requesting it falls outside the
pinctrl mapping. While this avoids a probe failure because the global GPIO
range overlaps and bypasses pinmux allocation, any attempt to apply pin
configuration (such as gpiod_set_config()) to the UFS reset pin will fail
because the pinctrl core will not be able to resolve the pin.

Should the gpio-ranges count in the base devicetree be updated to 182 to
accurately describe the hardware?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260709132013.4096850-1-shengchao.guo@oss.qualcomm.com?part=7