[PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-eb: enable GPIOs on CN12

[PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-eb: enable GPIOs on CN12

[Wolfram Sang]

CN12 offers some GPIOs independently of switch settings. Add the nodes.
Verified all the pins with a multimeter successfully.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---

 .../boot/dts/renesas/r9a06g032-rzn1d400-eb.dts  | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
index ead379988fb1..7d6ddc91bb2e 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
+++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
@@ -57,6 +57,12 @@ &gpio2 {
 	status = "okay";
 };
 
+&gpio2b {
+	pinctrl-0 = <&pins_gpio2b>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &i2c2 {
 	/* Sensors are different across revisions. All are LM75B compatible */
 	sensor@49 {
@@ -136,6 +142,17 @@ pins_eth2: pins-eth2 {
 		bias-disable;
 	};
 
+	pins_gpio2b: pins-gpio2b {
+		pinmux = <RZN1_PINMUX(164, RZN1_FUNC_GPIO)>,
+			 <RZN1_PINMUX(165, RZN1_FUNC_GPIO)>,
+			 <RZN1_PINMUX(166, RZN1_FUNC_GPIO)>,
+			 <RZN1_PINMUX(167, RZN1_FUNC_GPIO)>,
+			 <RZN1_PINMUX(168, RZN1_FUNC_GPIO)>,
+			 <RZN1_PINMUX(169, RZN1_FUNC_GPIO)>;
+		drive-strength = <6>;
+		bias-disable;
+	};
+
 	pins_mdio0: pins-mdio0 {
 		pinmux = <RZN1_PINMUX(150, RZN1_FUNC_MDIO0_GMAC0)>,
 			 <RZN1_PINMUX(151, RZN1_FUNC_MDIO0_GMAC0)>;
-- 
2.47.3

Re: [PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-eb: enable GPIOs on CN12

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `pinctrl-0` and `pinctrl-names` properties added to the `&gpio2b` subnode will be silently ignored by the kernel because the `snps,dw-apb-gpio` driver does not probe its subnodes as independent platform devices.
--

--- Patch [1]: [PATCH] ARM: dts: renesas: r9a06g032-rzn1d400-eb: enable GPIOs on CN12 ---
commit a17e87c79ff350400e4cf32dff0313dad00fefe9
Author: Wolfram Sang <wsa+renesas@sang-engineering.com>

ARM: dts: renesas: r9a06g032-rzn1d400-eb: enable GPIOs on CN12

This commit adds device tree nodes to enable GPIOs on CN12 for the
r9a06g032-rzn1d400-eb board.

> diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
> index ead379988fb1c..7d6ddc91bb2e4 100644
> --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
> +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
> @@ -57,6 +57,12 @@ &gpio2 {
>  	status = "okay";
>  };
>  
> +&gpio2b {
> +	pinctrl-0 = <&pins_gpio2b>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};

[Severity: Medium]
Will the pinctrl core actually apply these settings when attached to this
subnode?

The snps,dw-apb-gpio driver iterates over its port subnodes (like gpio2b)
to register gpio_chip interfaces, but it doesn't appear to register these
subnodes as independent platform devices.

Because the driver core only applies pinctrl-0 properties automatically
during probe for fully initialized device instances, this configuration
might be silently ignored by the kernel.

Should these pinctrl properties be moved to the parent &gpio2 node instead
so they are properly applied to the hardware?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260715122341.47838-2-wsa+renesas@sang-engineering.com?part=1