Re: [PATCH v3 2/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO

Re: [PATCH v3 2/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Silently ignored clock configuration on MDIO PHY node.
--

--- Patch [2]: [PATCH v3 2/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO ---
commit 235c0c71486f5323f7d8535da556a6e07eb3e094
Author: Jiaxing Hu <gahing@gahingwoo.com>
Subject: arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO

This patch adds the ArmSoM CM5 compute module and its CM5-IO carrier board,
configuring peripherals such as GMAC0 with an on-module Ethernet PHY, USB,
PCIe, and HDMI. It also describes the reset and 25 MHz reference clock
required for the YT8531 Ethernet PHY.

> diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi
> new file mode 100644
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi
[ ... ]
> +&mdio0 {
> +	reset-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
> +	reset-delay-us = <20000>;
> +	reset-post-delay-us = <100000>;
> +
> +	rgmii_phy0: phy@1 {
> +		compatible = "ethernet-phy-ieee802.3-c22";
> +		reg = <0x1>;
> +		clocks = <&cru REFCLKO25M_GMAC0_OUT>;
> +		assigned-clocks = <&cru REFCLKO25M_GMAC0_OUT>;
> +		assigned-clock-rates = <25000000>;

[Severity: Medium]
Will these assigned clock properties be processed by the kernel?

Since this PHY is placed on the mdio bus, which doesn't process assigned-clocks
automatically like the platform bus does, it appears this configuration will be
silently ignored.

If the bootloader leaves this clock unconfigured, the Ethernet PHY might fail to
operate. Should these properties be moved to the parent platform device (gmac0)
instead, so that the 25 MHz reference clock rate takes effect?

> +	};
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260716081711.2482259-1-gahing@gahingwoo.com?part=2

Re: [PATCH v3 2/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The DisplayPort controller (`dp`) is not enabled and not routed to the VOP2, breaking the advertised Type-C DP alt-mode.
- [Medium] The `sai6` CPU DAI node is not enabled, which prevents the HDMI sound card from probing.
--

--- Patch [2]: [PATCH v3 2/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO ---
commit 6aa295a8cc84993de39b6dae02d2c7333d9385bb
Author: Jiaxing Hu <gahing@gahingwoo.com>

arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO
    
This commit adds device tree files for the ArmSoM CM5, an RK3576 compute
module, and its CM5-IO carrier board. It configures peripherals such as
the RK806 PMIC, GMAC0, eMMC, HDMI, USB, and an M.2 PCIe slot.

> diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts
> new file mode 100644
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts
[ ... ]
> @@ -174,6 +174,10 @@ hdmi_out_con: endpoint {
>  	};
>  };
>  
> +&hdmi_sound {
> +	status = "okay";
> +};

[Severity: Medium]
Will the HDMI sound card fail to probe without the sai6 CPU DAI enabled?

Since hdmi_sound relies on sai6 as its CPU endpoint (defined in the base
SoC dtsi), leaving &sai6 disabled in this board file might prevent ALSA
from registering the sound card, resulting in broken HDMI audio.

> +
>  &hdptxphy {
>  	status = "okay";
>  };
[ ... ]
> @@ -317,6 +321,21 @@ &usb_drd1_dwc3 {
>  	status = "okay";
>  };
>  
> +&usbdp_phy {
> +	status = "okay";
> +	mode-switch;
> +	orientation-switch;
> +	sbu1-dc-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
> +	sbu2-dc-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;

[Severity: Medium]
Does the DisplayPort controller also need to be enabled for DP alt-mode to
function properly?

The usbdp_phy is configured for mode switching here, but the corresponding
&dp node and its VOP2 display pipeline endpoint appear to be missing or
disabled. Without the controller generating video data, will the Type-C
port fail to output a video signal?

> +
> +	port {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260716095101.2498464-1-gahing@gahingwoo.com?part=2

Re: [PATCH v3 2/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO

[Andrew Lunn]

> +&gmac0 {
> +	/* The RX delay is added by the PHY, the TX delay by the MAC below. */
> +	phy-mode = "rgmii-rxid";

Please read.

https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/net/ethernet-controller.yaml#L287

> +	clock_in_out = "output";
> +	clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>,
> +		 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
> +		 <&cru CLK_GMAC0_PTP_REF>, <&cru REFCLKO25M_GMAC0_OUT>;
> +	clock-names = "stmmaceth", "clk_mac_ref", "pclk_mac", "aclk_mac",
> +		      "ptp_ref", "clk_mac_refout";
> +	tx_delay = <0x21>;
> +	rx_delay = <0x00>;

Try setting phy-mode to rgmii-id, and these delays to 0, or removing
them.

	Andrew