[PATCH v3 0/2] soc/tegra: pmc: Add Tegra210B01 support

[PATCH v3 0/2] soc/tegra: pmc: Add Tegra210B01 support

[Aaron Kling via B4 Relay]

This series adds support for the Tegra210B01 SoC to the Tegra PMC driver
and documents the new compatible.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
Changes in v3:
- Update patch 2 commit author and sign-off tag as requested off list by
  author
- Update patch 2 commit message to describe the powergate differences
  compared to t210
- Drop sata powergate in patch 2
- Fix has_io_pad_wren value in patch 2
- Link to v2: https://lore.kernel.org/r/20260720-t210b01-pmc-v2-0-ca5317f8507b@gmail.com

Changes in v2:
- Address sashiko report and drop duplicated structs
- Link to v1: https://lore.kernel.org/r/20260717-t210b01-pmc-v1-0-bf776be8b3a7@gmail.com

---
Aaron Kling (1):
      dt-bindings: soc: tegra: pmc: Document Tegra210B01

Alexandre Hamamdjian (1):
      soc/tegra: pmc: Add Tegra210B01 support

 .../bindings/soc/tegra/nvidia,tegra20-pmc.yaml     |  5 +-
 drivers/soc/tegra/pmc.c                            | 61 ++++++++++++++++++++++
 2 files changed, 65 insertions(+), 1 deletion(-)
---
base-commit: 1a1757b76427f6201bfe0bf1bea9f7574f332a93
change-id: 20260713-t210b01-pmc-1a3f8b908044

Best regards,
-- 
Aaron Kling <webgeek1234@gmail.com>

[PATCH v3 1/2] dt-bindings: soc: tegra: pmc: Document Tegra210B01

[Aaron Kling via B4 Relay]

From: Aaron Kling <webgeek1234@gmail.com>

The PMC in Tegra210B01 is very similar to the one in the original
Tegra210, but has a few powergate differences. Document this soc.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
 Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml
index f516960dbbefb..8ec36c49f9594 100644
--- a/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml
@@ -18,6 +18,7 @@ properties:
       - nvidia,tegra114-pmc
       - nvidia,tegra124-pmc
       - nvidia,tegra210-pmc
+      - nvidia,tegra210b01-pmc
 
   reg:
     maxItems: 1
@@ -346,7 +347,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: nvidia,tegra210-pmc
+            enum:
+              - nvidia,tegra210-pmc
+              - nvidia,tegra210b01-pmc
     then:
       properties:
         pinmux:

-- 
2.54.0

[PATCH v3 2/2] soc/tegra: pmc: Add Tegra210B01 support

[Aaron Kling via B4 Relay]

From: Alexandre Hamamdjian <azkali.limited@gmail.com>

The PMC in Tegra210B01 is very similar to the one in the original
Tegra210, but has a few powergate differences. Specifically sata, venc,
and ve2 are removed.

Signed-off-by: Alexandre Hamamdjian <azkali.limited@gmail.com>
Co-developed-by: Thomas Makin <halorocker89@gmail.com>
Signed-off-by: Thomas Makin <halorocker89@gmail.com>
Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
 drivers/soc/tegra/pmc.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index f419a5395545f..d133f445e4ec4 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -3897,6 +3897,66 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
 	.has_single_mmio_aperture = true,
 };
 
+static const char * const tegra210b01_powergates[] = {
+	[TEGRA_POWERGATE_CPU] = "crail",
+	[TEGRA_POWERGATE_3D] = "3d",
+	[TEGRA_POWERGATE_PCIE] = "pcie",
+	[TEGRA_POWERGATE_MPE] = "mpe",
+	[TEGRA_POWERGATE_CPU1] = "cpu1",
+	[TEGRA_POWERGATE_CPU2] = "cpu2",
+	[TEGRA_POWERGATE_CPU3] = "cpu3",
+	[TEGRA_POWERGATE_CPU0] = "cpu0",
+	[TEGRA_POWERGATE_C0NC] = "c0nc",
+	[TEGRA_POWERGATE_SOR] = "sor",
+	[TEGRA_POWERGATE_DIS] = "dis",
+	[TEGRA_POWERGATE_DISB] = "disb",
+	[TEGRA_POWERGATE_XUSBA] = "xusba",
+	[TEGRA_POWERGATE_XUSBB] = "xusbb",
+	[TEGRA_POWERGATE_XUSBC] = "xusbc",
+	[TEGRA_POWERGATE_VIC] = "vic",
+	[TEGRA_POWERGATE_IRAM] = "iram",
+	[TEGRA_POWERGATE_NVDEC] = "nvdec",
+	[TEGRA_POWERGATE_NVJPG] = "nvjpg",
+	[TEGRA_POWERGATE_AUD] = "aud",
+	[TEGRA_POWERGATE_DFD] = "dfd",
+};
+
+static const struct tegra_pmc_soc tegra210b01_pmc_soc = {
+	.supports_core_domain = false,
+	.num_powergates = ARRAY_SIZE(tegra210b01_powergates),
+	.powergates = tegra210b01_powergates,
+	.num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
+	.cpu_powergates = tegra210_cpu_powergates,
+	.has_tsense_reset = true,
+	.has_gpu_clamps = true,
+	.needs_mbist_war = false,
+	.has_io_pad_wren = true,
+	.maybe_tz_only = true,
+	.num_io_pads = ARRAY_SIZE(tegra210_io_pads),
+	.io_pads = tegra210_io_pads,
+	.num_io_pad_vctrls = ARRAY_SIZE(tegra210_io_pad_vctrls),
+	.io_pad_vctrls = tegra210_io_pad_vctrls,
+	.num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
+	.pin_descs = tegra210_pin_descs,
+	.regs = &tegra20_pmc_regs,
+	.init = tegra20_pmc_init,
+	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
+	.powergate_set = tegra114_powergate_set,
+	.irq_set_wake = tegra210_pmc_irq_set_wake,
+	.irq_set_type = tegra210_pmc_irq_set_type,
+	.reset_sources = tegra210_reset_sources,
+	.num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
+	.reset_levels = NULL,
+	.num_reset_levels = 0,
+	.num_wake_events = ARRAY_SIZE(tegra210_wake_events),
+	.wake_events = tegra210_wake_events,
+	.pmc_clks_data = tegra_pmc_clks_data,
+	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
+	.has_blink_output = true,
+	.has_usb_sleepwalk = true,
+	.has_single_mmio_aperture = true,
+};
+
 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, "csia"),
 	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, "csib"),
@@ -4824,6 +4884,7 @@ static const struct of_device_id tegra_pmc_match[] = {
 	{ .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
 	{ .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
 	{ .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
+	{ .compatible = "nvidia,tegra210b01-pmc", .data = &tegra210b01_pmc_soc },
 	{ .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
 	{ .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
 	{ .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },

-- 
2.54.0

Re: [PATCH v3 1/2] dt-bindings: soc: tegra: pmc: Document Tegra210B01

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Incomplete documentation of powergate differences for Tegra210B01.
--

--- Patch [1]: [PATCH v3 1/2] dt-bindings: soc: tegra: pmc: Document Tegra210B01 ---
commit 4ee623d1a1b305589950060beca1ad845d9ac09e
Author: Aaron Kling <webgeek1234@gmail.com>

dt-bindings: soc: tegra: pmc: Document Tegra210B01

This commit documents the Tegra210B01 SoC in the Tegra PMC bindings.
It notes that the hardware is very similar to the original Tegra210
but has a few powergate differences.

> diff --git a/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml
> index f516960dbbefb..8ec36c49f9594 100644
> --- a/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml
> +++ b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml
> @@ -18,6 +18,7 @@ properties:
>        - nvidia,tegra114-pmc
>        - nvidia,tegra124-pmc
>        - nvidia,tegra210-pmc
> +      - nvidia,tegra210b01-pmc
>  
>    reg:
>      maxItems: 1

[Severity: Low]
The commit message mentions that Tegra210B01 "has a few powergate
differences." Should the documentation table further down in this file
under the powergates property also be updated to include Tegra210B01?

Currently, the Devices Applicable table does not list the new hardware,
leaving device tree authors without a reference for its valid powergates:

        Name     Description                   Devices Applicable
        --------------------------------------------------------------
        3d       3D Graphics                   Tegra20/114/124/210

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260722-t210b01-pmc-v3-0-1c5b970788f2@gmail.com?part=1

Re: [PATCH v3 2/2] soc/tegra: pmc: Add Tegra210B01 support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Undocumented behavioral change: MBIST workaround disabled for Tegra210B01.
--

--- Patch [2]: [PATCH v3 2/2] soc/tegra: pmc: Add Tegra210B01 support ---
commit 5ceea53482957796a181bc224b13a9428679c927
Author: Alexandre Hamamdjian <azkali.limited@gmail.com>

soc/tegra: pmc: Add Tegra210B01 support

This commit introduces support for the PMC in the Tegra210B01 SoC. The
new SoC is described as being very similar to the original Tegra210,
with specific powergate removals for sata, venc, and ve2.

> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index f419a5395545f..d133f445e4ec4 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c

[ ... ]

> @@ -3897,6 +3897,66 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {

[ ... ]

> +static const struct tegra_pmc_soc tegra210b01_pmc_soc = {
> +	.supports_core_domain = false,
> +	.num_powergates = ARRAY_SIZE(tegra210b01_powergates),
> +	.powergates = tegra210b01_powergates,
> +	.num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
> +	.cpu_powergates = tegra210_cpu_powergates,
> +	.has_tsense_reset = true,
> +	.has_gpu_clamps = true,
> +	.needs_mbist_war = false,

[Severity: Medium]
The commit message mentions that the new SoC is very similar to the original
Tegra210 and specifically lists sata, venc, and ve2 as the only powergate
differences.

However, this line disables the MBIST workaround, differing from the original
tegra210_pmc_soc which has it enabled.

If the silicon erratum was fixed in the B01 stepping, could this hardware
behavioral change be documented in the commit message? Or is this an
accidental omission that might lead to powergating failures or hardware
instability on this silicon?

> +	.has_io_pad_wren = true,
> +	.maybe_tz_only = true,

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260722-t210b01-pmc-v3-0-1c5b970788f2@gmail.com?part=2