[PATCH v13 0/5] Update designware pwm driver

[PATCH v13 0/5] Update designware pwm driver

[dongxuyang]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

There is already a patch [1] for the DesignWare PWM driver,
which is posted by Ben and still under review.
Based on this patch, this series is a continuation of [1]
to add support for IP versions 2.11a and later, which
includes support for "Pulse Width Modulation with 0%
and 100% Duty Cycle".

Supported chips:
ESWIN EIC7700 series SoC.

Test:
Tested this patch on the Sifive HiFive Premier P550 (which uses the EIC7700
SoC).

[1] https://lore.kernel.org/lkml/20230907161242.67190-1-ben.dooks@codethink.co.uk/

Updates:
  Changes in v13:
  - YAML:
    - Dropped Conor's Acked-by due to significant schema changes for
      patch 1 and 2.
    - Add 'Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>'
      for patch 4.
    - Add a reset-names property in snps,dw-apb-timers-pwm2.yaml.
    - Add description "Combined APB interface and timer logic reset"
      for the eswin,eic7700-pwm resets property, because the single
      entry is the combined interface bus and timer logic reset.
    - Mark reset-names as not applicable (reset-names: false) for
      this compatible, since there is only one reset.
  - Driver:
    - Remove the structure 'dwc_pwm_plat_data', because it is not needed
      to distinguish whether to support resets.
    - Drop reset_required and use
      devm_reset_control_array_get_optional_exclusive().
    - Replace dev_err() with dev_err_probe() in the probe function.
    - Add patch 5 for dw_apb_timer_of.c. Replace of_reset_control_get()
      with of_reset_control_array_get_optional_exclusive() to get both
      resets from the device tree (Sashiko review of v12).

  - Link to v12: https://lore.kernel.org/all/20260721120757.1134-1-dongxuyang@eswincomputing.com/

  Changes in v12:
  - YAML:
    - Update snps,dw-apb-timer binding to allow up to two reset lines
      (Sashiko review of v11).
  - Driver:
    - Update the boundary check to match hardware specification.
      Check the low and high boundary no more than 1 << 32
      (Sashiko review of v11).
    - Replace "dwc->feature" with "ctrl" in dwc_pwm_get_state().
      Check DWC_TIM_CTRL_0N100PWM_EN bit from the hardware control
      register to determine the actual timing formula in use
      (Sashiko review of v11).
    - Save the initial hardware state into dwc->ctx in probe() before
      clocks are gated (Sashiko review of v11).

  - Link to v11: https://lore.kernel.org/all/20260709081337.2022-1-dongxuyang@eswincomputing.com/

  Changes in v11:
  - YAML:
    - The timer binding does not need to be updated
      (Sashiko review of v10).
  - Driver:
    - Mask the interrupt by setting the DWC_TIM_CTRL_INT_MASK bit
      (Sashiko review of v10).
    - Call pm_runtime_disable() before manually rolling back the clock
      state (Sashiko review of v10).
      Drop pm_runtime_resume_and_get() and pm_runtime_put_sync(). Access
      registers and disable clocks only in the resumed state.
    - Remove reset assert in remove function, as disabling PM and clocks
      prevents further operation (Sashiko review of v10).

  - Link to v10: https://lore.kernel.org/all/20260703093308.482-1-dongxuyang@eswincomputing.com/

  Changes in v10:
  - Driver:
    - Do not add a dependency on PM. Additionally, the issues below will
      be fixed to ensure compatibility with and without PM support
      (Sashiko review of v9).
    - Note that writes to dwc->clk_rate in apply()/get_state() cannot race
      due to PWM core's chip->nonatomic_lock (Sashiko review of v9).
    - Fix __dwc_pwm_configure_timer() precision loss from dual rounding
      (compute period_cyc once); reject sub-clock-cycle periods in 0N100
      mode (add !period_cyc check to avoid writing 0 to LD_CNT/LD_CNT2).
    - dwc_pwm_get_state():
      Fix pm_runtime_resume_and_get() error check to use 'if (ret < 0)' to
      allow stub return value 1 when CONFIG_PM=n.
    - Deassert reset before reading MMIO in probe() to avoid bus stalls on
      SoCs that leave the block in reset (Sashiko review of v9).
    - Keep clocks enabled when CONFIG_PM=n.
      Condition the clock gating on IS_ENABLED(CONFIG_PM)
      (Sashiko review of v9).
    - Move register save/restore into runtime PM callbacks.
      Replace legacy suspend/resume with pm_runtime_force_suspend()/resume()
      to properly manage the generic power domain.

  - Link to v9: https://lore.kernel.org/all/20260701004139.347-1-dongxuyang@eswincomputing.com/

  Changes in v9:
  - YAML:
    - Add 'Acked-by: Conor Dooley <conor.dooley@microchip.com>' for
      patch 1 and 2.
  - Driver:
    - __dwc_pwm_configure_timer():
      reads state->polarity and swaps registers:
      NORMAL (active-high): duty_cycle to DWC_TIM_LD_CNT2 (HIGH),
      remainder to DWC_TIM_LD_CNT (LOW)
      INVERSED (active-low): duty_cycle to DWC_TIM_LD_CNT (LOW),
      remainder to DWC_TIM_LD_CNT2 (HIGH)
      Applies to both 0N100 and classic paths.
      dwc_pwm_apply():
      removed -EINVAL polarity guard; both polarities accepted.
      dwc_pwm_get_state():
      reconstructs polarity from pwm->state.polarity (last apply() value);
      initial read zero-initialized to PWM_POLARITY_NORMAL; decode mirrors
      apply() swap logic for consistent round-trip (Sashiko review of v8).
    - Replace pm_runtime_get_sync() with pm_runtime_resume_and_get() in
      dwc_pwm_apply() and add error checking (Sashiko review of v8).
    - Add a non-zero check for clk_rate in dwc_pwm_get_state().
      Add a non-zero check for dwc->clk_rate in probe (Sashiko review of v8).
    - When pwm_en is true, adding 'goto disable_clk;'. When pwm_en is false,
      return early from pm_disable without falling through to disable_clk.
      (Sashiko review of v8).
    - Replace pm_runtime_get_sync() with pm_runtime_resume_and_get() in
      dwc_pwm_plat_remove() and add error checking.
      On failure, skip register reads and pm_runtime_put_sync()
      (Sashiko review of v8).
    - Remove the -EBUSY check in dwc_pwm_suspend() and save all contexts
      (Sashiko review of v8).
    - Replace pm_runtime_get_sync() with pm_runtime_resume_and_get() in
      dwc_pwm_resume() (Sashiko review of v8).

  - Link to v8: https://lore.kernel.org/all/20260623071329.2034-1-dongxuyang@eswincomputing.com/

  Changes in v8:
  - YAML:
    - Split the v7 binding into two patches.
      Patch 1 explains why to add the resets property.
      Patch 2 adds the eswin compatible string and specified reset.
  - Driver:
    - Use mul_u64_u64_div_u64() to safely scale the values and avoid
      64-bit multiplication overflow in __dwc_pwm_configure_timer()
      and dwc_pwm_get_state().
      Add the include for linux/math64.h (Sashiko review of v7).
    - Keep the current usage of pwm->args.polarity until a better solution
      is available.
    - Use pm_runtime_resume_and_get() in dwc_pwm_get_state() instead of
      pm_runtime_get_sync(), so that register access is skipped if the
      device fails to resume (Sashiko review of v7).
    - Replace devm_pwmchip_add() with pwmchip_add() and move it after
      pm_runtime_enable(), so that the PWM chip is registered only after
      runtime PM has been fully initialized (Sashiko review of v7).
    - Remove the reset_assert label and reset_control_assert()
      (Sashiko review of v7).
    - Remove the pm_runtime_status_suspended() check and unconditionally
      use pm_runtime_get_sync() instead (Sashiko review of v7).
    - Remove  the pwm_en flag, but keep the pm_runtime_put_noidle() call
      (Sashiko review of v7; see email for explanation)
    - Use pm_runtime_status_suspended() to check the runtime PM status.
      If the device is not suspended (i.e., active), call
      clk_disable_unprepare(). If it is suspended, skip this block
      (Sashiko review of v7).
    - Use an explicit pwmchip_remove() as the first step of .remove(),
      instead of relying on devm_pwmchip_add() to unregister the chip
      after .remove() returns. This prevents the hardware teardown that
      follows from racing against a still-registered chip
      (Sashiko review of v7).
    - Add a check for dwc->rst before asserting reset in the remove path
      (Sashiko review of v7).
    - Drop the return value check from pm_runtime_put_sync()
      (Sashiko review of v7).

  - Link to v7: https://lore.kernel.org/all/20260605082242.1541-1-dongxuyang@eswincomputing.com/

  Changes in v7:
  - YAML:
    - Dropped Conor's Acked-by due to significant schema changes.
    - Rename patch 1 from "dt-bindings: pwm: dwc: add optional reset" to
      "dt-bindings: pwm: dwc: Add eswin compatible and resets property".
    - Update the commit message to explain why the EIC7700 supports only
      one reset.
    - Add constraints 'minItems: 1' and 'maxItems: 1' for the 'resets'
      property of eswin,eic7700-pwm.
    - Add an example for eswin,eic7700-pwm.

  - Link to v6: https://lore.kernel.org/all/20260424094529.1691-1-dongxuyang@eswincomputing.com/

  Changes in v6:
  - YAML:
    - Drop properties resets and its items description for eswin,eic7700-pwm.

  - Link to v5: https://lore.kernel.org/all/20260423083644.1168-1-dongxuyang@eswincomputing.com/

  Changes in v5:
  - YAML:
    - Add 'eswin,eic7700-pwm' compatible string.
    - Add the items description for the resets property and set minItems to 1.
    - Require resets property with exactly 1 reset for eswin,eic7700-pwm compatible.
  - Driver:
    - Add support for 'eswin,eic7700-pwm' compatible.
    - Add structure dwc_pwm_plat_data to manage the API for obtaining resets.

  - Link to v4: https://lore.kernel.org/all/20260415094908.1539-1-dongxuyang@eswincomputing.com/

  Changes in v4:
  - YAML:
    - Change maxItems from 1 to 2. As there is a corresponding reset signal
      for each clock domain, the effective maxItems of the resets property
      is set to 2.
    - Update the YAML commit message to describe the hardware.
  - Driver:
    - Replace devm_reset_control_get_optional_exclusive() with
      devm_reset_control_array_get_optional_exclusive(). Since the number
      of reset signals has increased from one to two, we need to use the
      array API to acquire them.

  - Link to v3: https://lore.kernel.org/all/20260402091718.1608-1-dongxuyang@eswincomputing.com/

  Changes in v3:
  - YAML:
    - Added a clear justification for the optional resets property. It is
      required to support proper controller initialization when no PWM
      channel is active at boot time, while allowing the driver to skip
      reset deassertion if any channel is already enabled.
  - Driver:
    - Update the boundary value check of tmp in __dwc_pwm_configure_timer()
      for DWC_TIM_CTRL_0N100PWM_EN.
    - Replace 'sizeof(struct dwc_pwm_drvdata)' with
      'struct_size(data, chips, 1)'.
    - Drop devm_clk_get_enabled() in favor of devm_clk_get() with explicit
      clk_prepare_enable() and clk_disable_unprepare() allowing runtime PM
      to manage clock state.
    - Replace devm_reset_control_get_optional_exclusive_deasserted() with
      devm_reset_control_get_optional_exclusive() and issue a full reset via
      reset_control_reset() only when no PWM channel is active at probe time.
    - Detect bootloader-enabled PWM channels by reading the enable bit, and
      initialize runtime PM as active for those channels by calling
      pm_runtime_set_active() and pm_runtime_get_noresume().
    - Remove autosuspend as it is not required for this driver.
    - Use explicit pm_runtime_enable() and pm_runtime_disable() instead of
      the managed devm_pm_runtime_enable() variant to ensure correct cleanup.
    - On device removal, recheck the channel enable status. If any channel
      remains active, call pm_runtime_put_noidle() before disabling clocks
      via clk_disable_unprepare().
      Resume device before register access during removal if it is runtime
      suspended, and re-suspend it afterward.
    - If device is suspended, resume it before register access during system
      resume/suspend.
    - Use pm_ptr() instead of pm_sleep_ptr() for correct PM operation.

  - Link to v2: https://lore.kernel.org/all/20260306093000.2065-1-dongxuyang@eswincomputing.com/

  Changes in v2:
  - YAML:
    - Remove eswin,eic7700-pwm.yaml. Use snps,dw-apb-timers-pwm2.yaml.
      The description in snps,dw-apb-timers-pwm2.yaml is better.
    - Add the resets property as optional, as defined in the databook.
    - Remove snps,pwm-full-range-enable as no additional property is needed.
  - Driver:
    - Change the file from pwm-dwc-eic7700.c to pwm-dwc-of.c from [1].
    - Define DWC_TIM_VERSION_ID_2_11A 2.11a as the baseline version.
    - Enable the 0% and 100% duty cycle mode by setting dwc->feature if
      the version read from the TIMERS_COMP_VERSION register is later
      than or equal to DWC_TIM_VERSION_ID_2_11A.
    - Use the DIV_ROUND_UP_ULL() to calculate width in the .apply and
      .get_state.
    - Additionally, Power Management (PM) support has been added to the
      pwm-dwc-of.c driver.
    - Drop the headers that are not used.
    - Use devm_clk_get_enabled() instead of devm_clk_get().
    - Drop of_match_ptr.
    - Fix build error with 1ULL << 32.
      Reported-by: kernel test robot <lkp@intel.com>
      Closes: https://lore.kernel.org/oe-kbuild-all/202512061720.j31AsgM7-lkp@intel.com/

  - Link to v1: https://lore.kernel.org/all/20251205090411.1388-1-dongxuyang@eswincomputing.com/
  - Link to v9: https://lore.kernel.org/lkml/20230907161242.67190-1-ben.dooks@codethink.co.uk/

Xuyang Dong (5):
  dt-bindings: pwm: dwc: Document optional resets property
  dt-bindings: pwm: dwc: Add eswin compatible
  pwm: dwc: add of/platform support
  dt-bindings: timer: dwc: Update resets property items
  clocksource: dw_apb_timer: Use reset array API to handle all resets

 .../bindings/pwm/snps,dw-apb-timers-pwm2.yaml |  45 ++-
 .../bindings/timer/snps,dw-apb-timer.yaml     |   5 +-
 drivers/clocksource/dw_apb_timer_of.c         |   6 +-
 drivers/pwm/Kconfig                           |  10 +
 drivers/pwm/Makefile                          |   1 +
 drivers/pwm/pwm-dwc-core.c                    | 172 ++++++++--
 drivers/pwm/pwm-dwc-of.c                      | 299 ++++++++++++++++++
 drivers/pwm/pwm-dwc.h                         |  25 +-
 8 files changed, 517 insertions(+), 46 deletions(-)
 create mode 100644 drivers/pwm/pwm-dwc-of.c

--
2.34.1

[PATCH v13 1/5] dt-bindings: pwm: dwc: Document optional resets property

[dongxuyang]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

The DesignWare PWM IP has two active-low reset inputs: presetn resets
the register interface logic in the pclk (bus) domain, and
timer_N_resetn resets the counter/timer logic in the timer_N_clk
domain. The existing snps,dw-apb-timers-pwm2 binding does not
describe either of these lines.

Add the resets property and describe the function of each reset to
support future use of resets. Add the reset-names property to allow
independent control of the two reset signals.

Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
 .../bindings/pwm/snps,dw-apb-timers-pwm2.yaml          | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
index 7523a89a1773..1f9d72f9f359 100644
--- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
+++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
@@ -43,6 +43,16 @@ properties:
       - const: bus
       - const: timer

+  resets:
+    items:
+      - description: Interface bus (presetn) reset
+      - description: PWM timer logic (timer_N_resetn) reset
+
+  reset-names:
+    items:
+      - const: bus
+      - const: timer
+
   snps,pwm-number:
     $ref: /schemas/types.yaml#/definitions/uint32
     description: The number of PWM channels configured for this instance
--
2.34.1

Re: [PATCH v13 1/5] dt-bindings: pwm: dwc: Document optional resets property

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The timer binding for the same hardware family (`timer/snps,dw-apb-timer.yaml`) was not updated to reflect the newly documented reset lines.
--

--- Patch [1]: [PATCH v13 1/5] dt-bindings: pwm: dwc: Document optional resets property ---
commit 1c2d313919493838e6334a2a8bbd90732e217da2
Author: Xuyang Dong <dongxuyang@eswincomputing.com>

dt-bindings: pwm: dwc: Document optional resets property

This commit adds the resets and reset-names properties to the DesignWare PWM
IP binding. It documents the active-low presetn and timer_N_resetn inputs for
the bus and timer domains respectively.

> diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
> index 7523a89a17733..1f9d72f9f3590 100644
> --- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
> +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
> @@ -43,6 +43,16 @@ properties:
>        - const: bus
>        - const: timer
>  
> +  resets:
> +    items:
> +      - description: Interface bus (presetn) reset
> +      - description: PWM timer logic (timer_N_resetn) reset
> +
> +  reset-names:
> +    items:
> +      - const: bus
> +      - const: timer

[Severity: Medium]
Should the standard timer binding for this exact same hardware module also
be updated to reflect these two newly documented reset lines?

The timer binding for the same hardware family currently only specifies
a single reset:

Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml:
  resets:
    maxItems: 1

If a device tree author adds the second reset line to a timer node
representing this IP, will it incorrectly fail schema validation against
snps,dw-apb-timer.yaml since that file lacks reset-names and caps maxItems
at 1?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260724084153.1473-1-dongxuyang@eswincomputing.com?part=1

[PATCH v13 2/5] dt-bindings: pwm: dwc: Add eswin compatible

[dongxuyang]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

EIC7700 integrates the DesignWare PWM IP described by the generic
snps,dw-apb-timers-pwm2 binding. On this SoC, the presetn and
timer_N_resetn inputs are physically tied together to a single reset
line, so exactly one reset is both required and sufficient, unlike
the generic binding where up to two independent lines are optional.

Add the eswin,eic7700-pwm compatible string and constrain its resets
property to exactly one entry.

Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
 .../bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 35 ++++++++++++++++---
 1 file changed, 31 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
index 1f9d72f9f359..c65174e2045a 100644
--- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
+++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
@@ -20,12 +20,11 @@ description:
   instead of having to encode the IP version number in the device tree
   compatible.

-allOf:
-  - $ref: pwm.yaml#
-
 properties:
   compatible:
-    const: snps,dw-apb-timers-pwm2
+    enum:
+      - snps,dw-apb-timers-pwm2
+      - eswin,eic7700-pwm

   reg:
     maxItems: 1
@@ -44,11 +43,13 @@ properties:
       - const: timer

   resets:
+    minItems: 1
     items:
       - description: Interface bus (presetn) reset
       - description: PWM timer logic (timer_N_resetn) reset

   reset-names:
+    minItems: 1
     items:
       - const: bus
       - const: timer
@@ -64,6 +65,23 @@ required:
   - clocks
   - clock-names

+allOf:
+  - $ref: pwm.yaml#
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: eswin,eic7700-pwm
+    then:
+      properties:
+        resets:
+          items:
+            - description: Combined APB interface and timer logic reset
+        reset-names: false
+      required:
+        - resets
+
 additionalProperties: false

 examples:
@@ -75,3 +93,12 @@ examples:
       clocks = <&bus>, <&timer>;
       clock-names = "bus", "timer";
     };
+  - |
+    pwm@50818000 {
+      compatible = "eswin,eic7700-pwm";
+      reg = <0x50818000 0x4000>;
+      #pwm-cells = <3>;
+      clocks = <&bus>, <&timer>;
+      clock-names = "bus", "timer";
+      resets = <&reset>;
+    };
--
2.34.1

Re: [PATCH v13 2/5] dt-bindings: pwm: dwc: Add eswin compatible

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Strict positional constraint on independent optional resets prevents using only the second reset ('timer').
--

--- Patch [2]: [PATCH v13 2/5] dt-bindings: pwm: dwc: Add eswin compatible ---
commit 5ab967af16c3b9f7a1cfa80ab82369dd37f82452
Author: Xuyang Dong <dongxuyang@eswincomputing.com>

dt-bindings: pwm: dwc: Add eswin compatible

This commit adds the eswin,eic7700-pwm compatible string to the DesignWare 
PWM IP binding. It constrains the resets property for this specific hardware 
variant to exactly one combined reset line, and modifies the base reset 
properties to require at least one reset.

> diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
> index 1f9d72f9f3590..c65174e2045a7 100644
> --- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
> +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml
[ ... ]
> @@ -44,11 +43,13 @@ properties:
>        - const: timer
>  
>    resets:
> +    minItems: 1
>      items:
>        - description: Interface bus (presetn) reset
>        - description: PWM timer logic (timer_N_resetn) reset
>  
>    reset-names:
> +    minItems: 1
>      items:
>        - const: bus
>        - const: timer

[Severity: Medium]
Does this strict positional constraint on reset-names prevent a generic
device from using only the second reset?

The generic compatible allows up to two independent resets, meaning any
combination should be valid. However, if a platform wires only the
independent timer reset and provides a single element array with just
"timer", the dt-schema validates it sequentially against the items list.
Because it expects the first position to be "bus", providing just the
timer reset will result in a validation error for an otherwise valid
hardware configuration.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260724084153.1473-1-dongxuyang@eswincomputing.com?part=2

[PATCH v13 3/5] pwm: dwc: add of/platform support

[dongxuyang]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

The dwc pwm controller can be used in non-PCI systems, so allow
either platform or OF based probing.

The controller is reset only when no PWM channel is enabled.
Otherwise, clocks are enabled and the runtime PM state is updated
to reflect the active hardware configuration.

The DWC PWM controller does not provide a hardware polarity bit.
Currently, the driver only supports active-low output, which is
incompatible with devices requiring active-high waveforms (e.g.,
backlight controllers, fan speed regulators).

Implement polarity control by exploiting the timer's dual load
registers. The hardware uses:
- LD_CNT:  LOW period count
- LD_CNT2: HIGH period count

The total period is defined as (LD_CNT + LD_CNT2). By swapping the
duty cycle between these registers, we invert the polarity while
keeping the period unchanged:
- PWM_POLARITY_NORMAL:  write duty_cycle to LD_CNT2 (HIGH period)
- PWM_POLARITY_INVERSED: write duty_cycle to LD_CNT  (LOW period)

Implementation:
Update both apply() and get_state() to handle state->polarity
consistently. Since the hardware does not store polarity, get_state()
returns the last successfully applied software state, ensuring that
read-back matches what was originally set.

Co-developed-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Xiang Xu <xuxiang@eswincomputing.com>
Signed-off-by: Guosheng Wang <wangguosheng@eswincomputing.com>
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
 drivers/pwm/Kconfig        |  10 ++
 drivers/pwm/Makefile       |   1 +
 drivers/pwm/pwm-dwc-core.c | 172 +++++++++++++++++----
 drivers/pwm/pwm-dwc-of.c   | 299 +++++++++++++++++++++++++++++++++++++
 drivers/pwm/pwm-dwc.h      |  25 +++-
 5 files changed, 468 insertions(+), 39 deletions(-)
 create mode 100644 drivers/pwm/pwm-dwc-of.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index e8886a9b64d9..fd1d68beab67 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -249,6 +249,16 @@ config PWM_DWC
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-dwc.

+config PWM_DWC_OF
+	tristate "DesignWare PWM Controller (OF bus)"
+	depends on HAS_IOMEM && (OF || COMPILE_TEST)
+	select PWM_DWC_CORE
+	help
+	  PWM driver for Synopsys DWC PWM Controller on an OF bus or
+	  a platform bus.
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-dwc-of.
+
 config PWM_EP93XX
 	tristate "Cirrus Logic EP93xx PWM support"
 	depends on ARCH_EP93XX || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 5630a521a7cf..acd7dfe98dff 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_CRC)		+= pwm-crc.o
 obj-$(CONFIG_PWM_CROS_EC)	+= pwm-cros-ec.o
 obj-$(CONFIG_PWM_DWC_CORE)	+= pwm-dwc-core.o
 obj-$(CONFIG_PWM_DWC)		+= pwm-dwc.o
+obj-$(CONFIG_PWM_DWC_OF)	+= pwm-dwc-of.o
 obj-$(CONFIG_PWM_EP93XX)	+= pwm-ep93xx.o
 obj-$(CONFIG_PWM_FSL_FTM)	+= pwm-fsl-ftm.o
 obj-$(CONFIG_PWM_GPIO)		+= pwm-gpio.o
diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c
index 6dabec93a3c6..eb11dfc4dc71 100644
--- a/drivers/pwm/pwm-dwc-core.c
+++ b/drivers/pwm/pwm-dwc-core.c
@@ -12,8 +12,10 @@
 #define DEFAULT_SYMBOL_NAMESPACE "dwc_pwm"

 #include <linux/bitops.h>
+#include <linux/clk.h>
 #include <linux/export.h>
 #include <linux/kernel.h>
+#include <linux/math64.h>
 #include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/pm_runtime.h>
@@ -39,26 +41,82 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc,
 				     struct pwm_device *pwm,
 				     const struct pwm_state *state)
 {
-	u64 tmp;
+	u64 tmp, period_cyc;
 	u32 ctrl;
 	u32 high;
 	u32 low;

-	/*
-	 * Calculate width of low and high period in terms of input clock
-	 * periods and check are the result within HW limits between 1 and
-	 * 2^32 periods.
-	 */
-	tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns);
-	if (tmp < 1 || tmp > (1ULL << 32))
-		return -ERANGE;
-	low = tmp - 1;
-
-	tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle,
-				    dwc->clk_ns);
-	if (tmp < 1 || tmp > (1ULL << 32))
-		return -ERANGE;
-	high = tmp - 1;
+	if (dwc->clk)
+		dwc->clk_rate = clk_get_rate(dwc->clk);
+
+	if (dwc->features & DWC_TIM_CTRL_0N100PWM_EN) {
+		/*
+		 * Calculate the total period in clock cycles first, then the
+		 * duty cycle. Derive the complementary half as the remainder to
+		 * avoid compounding two independent floor-truncation errors:
+		 * floor(duty) + floor(period - duty) can be one cycle short of
+		 * floor(period). The PWM core requires the maximal achievable
+		 * period not exceeding the requested value.
+		 */
+		period_cyc = mul_u64_u64_div_u64(state->period, dwc->clk_rate,
+						 NSEC_PER_SEC);
+		if (!period_cyc)
+			return -ERANGE;
+
+		tmp = mul_u64_u64_div_u64(state->duty_cycle, dwc->clk_rate,
+					  NSEC_PER_SEC);
+		/*
+		 * Calculate the width of the low and high periods in terms of
+		 * input clock periods, and check whether the results are within
+		 * the hardware limits of 0 to 2^32 periods.
+		 */
+		if (tmp >= (1ULL << 32) || period_cyc - tmp >= (1ULL << 32))
+			return -ERANGE;
+
+		/*
+		 * The hardware has no polarity register. Polarity inversion is
+		 * achieved by swapping the low and high load-count registers:
+		 * NORMAL (active-high): duty_cycle ->
+		 *				HIGH period (DWC_TIM_LD_CNT2)
+		 * INVERSED (active-low): duty_cycle ->
+		 *				LOW period (DWC_TIM_LD_CNT)
+		 */
+		if (state->polarity == PWM_POLARITY_NORMAL) {
+			high = tmp;
+			low = period_cyc - tmp;
+		} else {
+			low = tmp;
+			high = period_cyc - tmp;
+		}
+	} else {
+		/*
+		 * Calculate width of low and high period in terms of input
+		 * clock periods and check are the result within HW limits
+		 * between 1 and 2^32 periods.
+		 * Polarity inversion uses the same register-swap technique as
+		 * the 0N100 path above.
+		 * Derive the complementary half from the total period to avoid
+		 * compounding two independent floor-truncation errors.
+		 */
+		tmp = mul_u64_u64_div_u64(state->duty_cycle, dwc->clk_rate,
+					  NSEC_PER_SEC);
+		if (tmp < 1 || tmp > (1ULL << 32))
+			return -ERANGE;
+
+		period_cyc = mul_u64_u64_div_u64(state->period, dwc->clk_rate,
+						 NSEC_PER_SEC);
+		/* period_cyc - tmp: complementary half; tmp <= period_cyc */
+		if (period_cyc - tmp < 1 || period_cyc - tmp > (1ULL << 32))
+			return -ERANGE;
+
+		if (state->polarity == PWM_POLARITY_NORMAL) {
+			high = tmp - 1;
+			low = period_cyc - tmp - 1;
+		} else {
+			low = tmp - 1;
+			high = period_cyc - tmp - 1;
+		}
+	}

 	/*
 	 * Specification says timer usage flow is to disable timer, then
@@ -74,6 +132,7 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc,
 	 * width of low period and latter the width of high period in terms
 	 * multiple of input clock periods:
 	 * Width = ((Count + 1) * input clock period).
+	 * Width = (Count * input clock period) : supported 0% and 100%.
 	 */
 	dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm));
 	dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm));
@@ -85,6 +144,14 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc,
 	 * periods are set by Load Count registers.
 	 */
 	ctrl = DWC_TIM_CTRL_MODE_USER | DWC_TIM_CTRL_PWM;
+	/*
+	 * Mask interrupts to prevent unmasked timer interrupts on shared IRQ
+	 * systems where no IRQ handler is installed.
+	 */
+	ctrl |= DWC_TIM_CTRL_INT_MASK;
+	if (dwc->features & DWC_TIM_CTRL_0N100PWM_EN)
+		ctrl |= DWC_TIM_CTRL_0N100PWM_EN;
+
 	dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm));

 	/*
@@ -99,14 +166,18 @@ static int dwc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 			 const struct pwm_state *state)
 {
 	struct dwc_pwm *dwc = to_dwc_pwm(chip);
-
-	if (state->polarity != PWM_POLARITY_INVERSED)
-		return -EINVAL;
+	int ret;

 	if (state->enabled) {
-		if (!pwm->state.enabled)
-			pm_runtime_get_sync(pwmchip_parent(chip));
-		return __dwc_pwm_configure_timer(dwc, pwm, state);
+		if (!pwm->state.enabled) {
+			ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
+			if (ret < 0)
+				return ret;
+		}
+		ret = __dwc_pwm_configure_timer(dwc, pwm, state);
+		if (ret && !pwm->state.enabled)
+			pm_runtime_put_sync(pwmchip_parent(chip));
+		return ret;
 	} else {
 		if (pwm->state.enabled) {
 			__dwc_pwm_set_enable(dwc, pwm->hwpwm, false);
@@ -121,10 +192,23 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 			     struct pwm_state *state)
 {
 	struct dwc_pwm *dwc = to_dwc_pwm(chip);
-	u64 duty, period;
+	unsigned long clk_rate;
 	u32 ctrl, ld, ld2;
+	u64 duty, period;
+	int ret;
+
+	ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
+	if (ret < 0)
+		return ret;
+
+	if (dwc->clk)
+		dwc->clk_rate = clk_get_rate(dwc->clk);

-	pm_runtime_get_sync(pwmchip_parent(chip));
+	clk_rate = dwc->clk_rate;
+	if (!clk_rate) {
+		pm_runtime_put_sync(pwmchip_parent(chip));
+		return -EINVAL;
+	}

 	ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm));
 	ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
@@ -132,22 +216,46 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,

 	state->enabled = !!(ctrl & DWC_TIM_CTRL_EN);

+	/*
+	 * The hardware has no polarity status register; polarity is encoded
+	 * implicitly by which of DWC_TIM_LD_CNT / DWC_TIM_LD_CNT2 holds the
+	 * duty-cycle period (see __dwc_pwm_configure_timer). Report the
+	 * polarity that was last programmed by apply(). On the initial read
+	 * (before any apply call), pwm->state.polarity defaults to
+	 * PWM_POLARITY_NORMAL, which is the natural zero-initialised value.
+	 */
+	state->polarity = pwm->state.polarity;
+
 	/*
 	 * If we're not in PWM, technically the output is a 50-50
 	 * based on the timer load-count only.
 	 */
 	if (ctrl & DWC_TIM_CTRL_PWM) {
-		duty = (ld + 1) * dwc->clk_ns;
-		period = (ld2 + 1)  * dwc->clk_ns;
-		period += duty;
+		if (ctrl & DWC_TIM_CTRL_0N100PWM_EN) {
+			/*
+			 * NORMAL: duty_cycle was written to DWC_TIM_LD_CNT2.
+			 * INVERSED: duty_cycle was written to DWC_TIM_LD_CNT.
+			 */
+			if (state->polarity == PWM_POLARITY_NORMAL)
+				duty = ld2;
+			else
+				duty = ld;
+			period = (u64)ld + ld2;
+		} else {
+			if (state->polarity == PWM_POLARITY_NORMAL)
+				duty = ld2 + 1;
+			else
+				duty = ld + 1;
+			period = (u64)ld + ld2 + 2;
+		}
 	} else {
-		duty = (ld + 1) * dwc->clk_ns;
+		duty = ld + 1;
 		period = duty * 2;
+		state->polarity = PWM_POLARITY_INVERSED;
 	}

-	state->polarity = PWM_POLARITY_INVERSED;
-	state->period = period;
-	state->duty_cycle = duty;
+	state->period = mul_u64_u64_div_u64(period, NSEC_PER_SEC, clk_rate);
+	state->duty_cycle = mul_u64_u64_div_u64(duty, NSEC_PER_SEC, clk_rate);

 	pm_runtime_put_sync(pwmchip_parent(chip));

@@ -169,7 +277,7 @@ struct pwm_chip *dwc_pwm_alloc(struct device *dev)
 		return chip;
 	dwc = to_dwc_pwm(chip);

-	dwc->clk_ns = 10;
+	dwc->clk_rate = NSEC_PER_SEC / 10;
 	chip->ops = &dwc_pwm_ops;

 	return chip;
diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c
new file mode 100644
index 000000000000..4956dd36f93a
--- /dev/null
+++ b/drivers/pwm/pwm-dwc-of.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DesignWare PWM Controller driver OF
+ *
+ * Copyright (C) 2026 SiFive, Inc.
+ */
+
+#define DEFAULT_SYMBOL_NAMESPACE "dwc_pwm_of"
+
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/pwm.h>
+#include <linux/reset.h>
+
+#include "pwm-dwc.h"
+
+static int dwc_pwm_plat_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct dwc_pwm_drvdata *data;
+	u32 ctrl[DWC_TIMERS_TOTAL];
+	struct pwm_chip *chip;
+	struct dwc_pwm *dwc;
+	bool pwm_en = false;
+	u32 nr_pwm, tim_id;
+	unsigned int i;
+	int ret;
+
+	data = devm_kzalloc(dev, struct_size(data, chips, 1), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	chip = dwc_pwm_alloc(dev);
+	if (IS_ERR(chip))
+		return dev_err_probe(dev, PTR_ERR(chip),
+				     "failed to alloc pwm\n");
+
+	dwc = to_dwc_pwm(chip);
+
+	dwc->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(dwc->base))
+		return PTR_ERR(dwc->base);
+
+	if (!device_property_read_u32(dev, "snps,pwm-number", &nr_pwm)) {
+		if (nr_pwm > DWC_TIMERS_TOTAL)
+			dev_warn(dev, "too many PWMs (%u), capping at %u\n",
+				 nr_pwm, chip->npwm);
+		else
+			chip->npwm = nr_pwm;
+	}
+
+	dwc->bus_clk = devm_clk_get(dev, "bus");
+	if (IS_ERR(dwc->bus_clk))
+		return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
+				     "failed to get bus clock\n");
+
+	dwc->clk = devm_clk_get(dev, "timer");
+	if (IS_ERR(dwc->clk))
+		return dev_err_probe(dev, PTR_ERR(dwc->clk),
+				     "failed to get timer clock\n");
+
+	ret = devm_clk_rate_exclusive_get(dev, dwc->clk);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "failed to get exclusive rate\n");
+
+	dwc->clk_rate = clk_get_rate(dwc->clk);
+	if (!dwc->clk_rate)
+		return dev_err_probe(dev, -EINVAL,
+				     "failed to get a valid clock rate\n");
+
+	dwc->rst = devm_reset_control_array_get_optional_exclusive(dev);
+
+	if (IS_ERR(dwc->rst))
+		return dev_err_probe(dev, PTR_ERR(dwc->rst),
+				     "failed to get reset control\n");
+
+	ret = clk_prepare_enable(dwc->bus_clk);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "failed to enable bus clock\n");
+
+	ret = clk_prepare_enable(dwc->clk);
+	if (ret) {
+		ret = dev_err_probe(dev, ret, "failed to enable timer clock\n");
+		goto disable_busclk;
+	}
+
+	/* Ensure the device is out of reset before accessing MMIO registers. */
+	ret = reset_control_deassert(dwc->rst);
+	if (ret) {
+		ret = dev_err_probe(dev, ret, "failed to deassert reset\n");
+		goto disable_clk;
+	}
+
+	/*
+	 * Check all channels to see if any channel is enabled.
+	 * Read the control register of each channel and extract the enable bit
+	 */
+	for (i = 0; i < chip->npwm; i++) {
+		ctrl[i] = dwc_pwm_readl(dwc, DWC_TIM_CTRL(i)) & DWC_TIM_CTRL_EN;
+		if (ctrl[i])
+			pwm_en = true;
+	}
+
+	/*
+	 * Only issue a reset pulse when all channels are disabled, so a PWM
+	 * channel already running (e.g. configured by firmware before Linux
+	 * took over) is left undisturbed.
+	 */
+	if (!pwm_en) {
+		ret = reset_control_reset(dwc->rst);
+		if (ret) {
+			ret = dev_err_probe(dev, ret, "failed to reset\n");
+			goto disable_clk;
+		}
+	}
+
+	/* init PWM feature */
+	dwc->features = 0;
+	/*
+	 * Support for 0% and 100% duty cycle mode was added in version 2.11a
+	 * and later.
+	 */
+	tim_id = dwc_pwm_readl(dwc, DWC_TIMERS_COMP_VERSION);
+	if (tim_id >= DWC_TIM_VERSION_ID_2_11A)
+		dwc->features |= DWC_TIM_CTRL_0N100PWM_EN;
+
+	data->chips[0] = chip;
+	dev_set_drvdata(dev, data);
+
+	/*
+	 * Save hardware state to PM context before first resume.
+	 * Prevents zero-initialized context from overwriting registers
+	 * and losing bootloader-preset configuration.
+	 */
+	for (i = 0; i < chip->npwm; i++) {
+		dwc->ctx[i].cnt = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i));
+		dwc->ctx[i].cnt2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i));
+		dwc->ctx[i].ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(i));
+	}
+
+	/*
+	 * If any PWM channel is enabled, mark device active and hold runtime PM
+	 * references for each enabled channel. Otherwise, gate the clocks.
+	 *
+	 * When CONFIG_PM is disabled, pm_runtime callbacks are stubs that never
+	 * re-enable clocks, so keep clocks on unconditionally in that case.
+	 */
+	if (pwm_en) {
+		pm_runtime_set_active(dev);
+		for (i = 0; i < chip->npwm; i++) {
+			if (ctrl[i])
+				pm_runtime_get_noresume(dev);
+		}
+	} else if (IS_ENABLED(CONFIG_PM)) {
+		clk_disable_unprepare(dwc->clk);
+		clk_disable_unprepare(dwc->bus_clk);
+	}
+
+	pm_runtime_enable(dev);
+
+	ret = pwmchip_add(chip);
+	if (ret) {
+		ret = dev_err_probe(dev, ret, "failed to add pwm chip\n");
+		goto pm_disable;
+	}
+
+	return 0;
+
+pm_disable:
+	pm_runtime_disable(dev);
+	if (pwm_en) {
+		for (i = 0; i < chip->npwm; i++) {
+			if (ctrl[i])
+				pm_runtime_put_noidle(dev);
+		}
+		goto disable_clk;
+	}
+	/*
+	 * When CONFIG_PM is disabled, clocks were never gated and must be
+	 * disabled here.
+	 */
+	if (!IS_ENABLED(CONFIG_PM))
+		goto disable_clk;
+
+	return ret;
+
+disable_clk:
+	clk_disable_unprepare(dwc->clk);
+disable_busclk:
+	clk_disable_unprepare(dwc->bus_clk);
+
+	return ret;
+}
+
+static void dwc_pwm_plat_remove(struct platform_device *pdev)
+{
+	struct dwc_pwm_drvdata *data = platform_get_drvdata(pdev);
+	struct pwm_chip *chip = data->chips[0];
+	struct dwc_pwm *dwc = to_dwc_pwm(chip);
+	unsigned int idx;
+	u32 ctrl;
+
+	pwmchip_remove(chip);
+	pm_runtime_disable(&pdev->dev);
+
+	if (!pm_runtime_status_suspended(&pdev->dev)) {
+		for (idx = 0; idx < chip->npwm; idx++) {
+			ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(idx));
+			if (ctrl & DWC_TIM_CTRL_EN) {
+				dwc_pwm_writel(dwc, ctrl & ~DWC_TIM_CTRL_EN,
+					       DWC_TIM_CTRL(idx));
+				pm_runtime_put_noidle(&pdev->dev);
+			}
+		}
+		clk_disable_unprepare(dwc->clk);
+		clk_disable_unprepare(dwc->bus_clk);
+	}
+}
+
+static int dwc_pwm_runtime_suspend(struct device *dev)
+{
+	struct dwc_pwm_drvdata *data = dev_get_drvdata(dev);
+	struct pwm_chip *chip = data->chips[0];
+	struct dwc_pwm *dwc = to_dwc_pwm(chip);
+	unsigned int idx;
+
+	for (idx = 0; idx < chip->npwm; idx++) {
+		dwc->ctx[idx].cnt = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(idx));
+		dwc->ctx[idx].cnt2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(idx));
+		dwc->ctx[idx].ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(idx));
+	}
+
+	clk_disable_unprepare(dwc->clk);
+	clk_disable_unprepare(dwc->bus_clk);
+
+	return 0;
+}
+
+static int dwc_pwm_runtime_resume(struct device *dev)
+{
+	struct dwc_pwm_drvdata *data = dev_get_drvdata(dev);
+	struct pwm_chip *chip = data->chips[0];
+	struct dwc_pwm *dwc = to_dwc_pwm(chip);
+	unsigned int idx;
+	int ret;
+
+	ret = clk_prepare_enable(dwc->bus_clk);
+	if (ret) {
+		dev_err(dev, "failed to enable bus clock: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(dwc->clk);
+	if (ret) {
+		dev_err(dev, "failed to enable timer clock: %d\n", ret);
+		clk_disable_unprepare(dwc->bus_clk);
+		return ret;
+	}
+
+	for (idx = 0; idx < chip->npwm; idx++) {
+		dwc_pwm_writel(dwc, dwc->ctx[idx].cnt, DWC_TIM_LD_CNT(idx));
+		dwc_pwm_writel(dwc, dwc->ctx[idx].cnt2, DWC_TIM_LD_CNT2(idx));
+		dwc_pwm_writel(dwc, dwc->ctx[idx].ctrl, DWC_TIM_CTRL(idx));
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops dwc_pwm_pm_ops = {
+	RUNTIME_PM_OPS(dwc_pwm_runtime_suspend, dwc_pwm_runtime_resume, NULL)
+	SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
+};
+
+static const struct of_device_id dwc_pwm_dt_ids[] = {
+	{ .compatible = "snps,dw-apb-timers-pwm2" },
+	{ .compatible = "eswin,eic7700-pwm" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, dwc_pwm_dt_ids);
+
+static struct platform_driver dwc_pwm_plat_driver = {
+	.driver = {
+		.name = "dwc-pwm",
+		.pm = pm_ptr(&dwc_pwm_pm_ops),
+		.of_match_table = dwc_pwm_dt_ids,
+	},
+	.probe = dwc_pwm_plat_probe,
+	.remove = dwc_pwm_plat_remove,
+};
+
+module_platform_driver(dwc_pwm_plat_driver);
+
+MODULE_ALIAS("platform:dwc-pwm-of");
+MODULE_AUTHOR("Ben Dooks <ben.dooks@codethink.co.uk>");
+MODULE_DESCRIPTION("DesignWare PWM Controller");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h
index 1562594e7f85..75f7c2d031c4 100644
--- a/drivers/pwm/pwm-dwc.h
+++ b/drivers/pwm/pwm-dwc.h
@@ -26,12 +26,19 @@ MODULE_IMPORT_NS("dwc_pwm");
 #define DWC_TIMERS_TOTAL	8

 /* Timer Control Register */
-#define DWC_TIM_CTRL_EN		BIT(0)
-#define DWC_TIM_CTRL_MODE	BIT(1)
-#define DWC_TIM_CTRL_MODE_FREE	(0 << 1)
-#define DWC_TIM_CTRL_MODE_USER	(1 << 1)
-#define DWC_TIM_CTRL_INT_MASK	BIT(2)
-#define DWC_TIM_CTRL_PWM	BIT(3)
+#define DWC_TIM_CTRL_EN			BIT(0)
+#define DWC_TIM_CTRL_MODE		BIT(1)
+#define DWC_TIM_CTRL_MODE_FREE		(0 << 1)
+#define DWC_TIM_CTRL_MODE_USER		BIT(1)
+#define DWC_TIM_CTRL_INT_MASK		BIT(2)
+#define DWC_TIM_CTRL_PWM		BIT(3)
+#define DWC_TIM_CTRL_0N100PWM_EN	BIT(4)
+
+/*
+ * The version 2.11a and later add "Pulse Width Modulation with
+ * 0% and 100% Duty Cycle".
+ */
+#define DWC_TIM_VERSION_ID_2_11A	0x3231312a

 struct dwc_pwm_info {
 	unsigned int nr;
@@ -52,8 +59,12 @@ struct dwc_pwm_ctx {

 struct dwc_pwm {
 	void __iomem *base;
-	unsigned int clk_ns;
+	struct clk *bus_clk;
+	struct clk *clk;
+	unsigned long clk_rate;
+	struct reset_control *rst;
 	struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL];
+	u32 features;
 };

 static inline struct dwc_pwm *to_dwc_pwm(struct pwm_chip *chip)
--
2.34.1

Re: [PATCH v13 3/5] pwm: dwc: add of/platform support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Module autoloading for non-OF setups will fail due to a module alias mismatch.
--

--- Patch [3]: [PATCH v13 3/5] pwm: dwc: add of/platform support ---
commit efa310f451f843a8ed2f095d6d6d3c443510ca1a
Author: Xuyang Dong <dongxuyang@eswincomputing.com>

pwm: dwc: add of/platform support

This commit adds platform and OF-based probing support for the dwc PWM
controller, allowing it to be used in non-PCI systems. It implements polarity
control using the timer's dual load registers and updates clock and runtime
PM state management.

> diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c
> new file mode 100644
> index 0000000000000..4956dd36f93ad
> --- /dev/null
> +++ b/drivers/pwm/pwm-dwc-of.c

[ ... ]

> +static struct platform_driver dwc_pwm_plat_driver = {
> +	.driver = {
> +		.name = "dwc-pwm",
> +		.pm = pm_ptr(&dwc_pwm_pm_ops),
> +		.of_match_table = dwc_pwm_dt_ids,
> +	},
> +	.probe = dwc_pwm_plat_probe,
> +	.remove = dwc_pwm_plat_remove,
> +};
> +
> +module_platform_driver(dwc_pwm_plat_driver);
> +
> +MODULE_ALIAS("platform:dwc-pwm-of");

[Severity: Medium]
Does this module alias mismatch prevent automatic module loading on non-OF
setups?

The platform driver registers its name as "dwc-pwm", which means a system
without Device Tree will emit a uevent with MODALIAS=platform:dwc-pwm. Since
the provided MODULE_ALIAS is "platform:dwc-pwm-of", udev will likely fail to
find and load this module automatically.

> +MODULE_AUTHOR("Ben Dooks <ben.dooks@codethink.co.uk>");
> +MODULE_DESCRIPTION("DesignWare PWM Controller");
> +MODULE_LICENSE("GPL");

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260724084153.1473-1-dongxuyang@eswincomputing.com?part=3

[PATCH v13 4/5] dt-bindings: timer: dwc: Update resets property items

[dongxuyang]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

The DesignWare DW_apb_timers IP has two active-low reset inputs:
presetn resets the register interface logic in the pclk (bus) domain,
and timer_N_resetn resets the counter/timer logic in the timer_N_clk
domain. The existing snps,dw-apb-timer binding only describes one.

Update snps,dw-apb-timer binding to allow up to two reset lines,
matching the hardware capabilities of the DesignWare IP family.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
 .../devicetree/bindings/timer/snps,dw-apb-timer.yaml         | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
index d33c9205a909..4d30cd01ac65 100644
--- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
@@ -25,7 +25,10 @@ properties:
     maxItems: 1

   resets:
-    maxItems: 1
+    minItems: 1
+    items:
+      - description: Timer ticks reference (timer_N_resetn) reset
+      - description: APB interface (presetn) reset

   clocks:
     minItems: 1
--
2.34.1

Re: [PATCH v13 4/5] dt-bindings: timer: dwc: Update resets property items

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [High] The timer driver is not updated to deassert the newly allowed second reset line, which can lead to system hangs.
- [Medium] Missing `reset-names` property prevents accurate hardware representation for partial reset implementations.

Pre-existing issues:
- [High] This problem wasn't introduced by this patch, but the driver asserts and deasserts the hardware reset before the corresponding clocks are enabled.
--

--- Patch [4]: [PATCH v13 4/5] dt-bindings: timer: dwc: Update resets property items ---
commit 10dcd30e56947333e8bfdc5270bc95e60b327052
Author: Xuyang Dong <dongxuyang@eswincomputing.com>

dt-bindings: timer: dwc: Update resets property items

The DesignWare DW_apb_timers IP has two active-low reset inputs:
presetn resets the register interface logic in the pclk (bus) domain,
and timer_N_resetn resets the counter/timer logic in the timer_N_clk
domain. The existing snps,dw-apb-timer binding only describes one.

Update snps,dw-apb-timer binding to allow up to two reset lines,
matching the hardware capabilities of the DesignWare IP family.

> diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> index d33c9205a9093..4d30cd01ac65f 100644
> --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> @@ -25,7 +25,10 @@ properties:
>      maxItems: 1
>  
>    resets:
> -    maxItems: 1
> +    minItems: 1
> +    items:
> +      - description: Timer ticks reference (timer_N_resetn) reset
> +      - description: APB interface (presetn) reset

[Severity: Medium]
Since the resets array was expanded to allow multiple items, should a
reset-names property be added to allow disambiguation?

Because the schema enforces additionalProperties: false, device trees cannot
currently add names. If a platform only has software control over the APB
reset (presetn) and not the timer reset, it cannot correctly represent the
hardware because array bindings without names require index 0 to be populated
first.

[Severity: High]
Does the driver need to be updated to handle this new reset line?

If a device tree is updated to specify both resets, the timer driver only
fetches and deasserts the first one (index 0):

drivers/clocksource/dw_apb_timer_of.c:timer_get_base_and_rate() {
        ...
        rstc = of_reset_control_get(np, NULL);
        if (!IS_ERR(rstc)) {
                reset_control_assert(rstc);
                reset_control_deassert(rstc);
        }
        ...
}

If a platform requires the second reset (presetn) to be deasserted by the
kernel to access the APB interface, the timer registers will remain
inaccessible. Can this lead to a bus hang or external abort?

[Severity: High]
This is a pre-existing issue, but the driver asserts and deasserts the
hardware reset before the corresponding clocks are enabled:

drivers/clocksource/dw_apb_timer_of.c:timer_get_base_and_rate() {
        ...
        rstc = of_reset_control_get(np, NULL);
        if (!IS_ERR(rstc)) {
                reset_control_assert(rstc);
                reset_control_deassert(rstc);
        }

        /* ... */
        pclk = of_clk_get_by_name(np, "pclk");
        ...
}

The DW APB timer reset signals operate in their respective clock domains.
Toggling a synchronous reset while the associated clock is disabled means
the target flip-flops never receive the clock edges necessary to process
the reset.

Could this leave the timer in an undefined state if the bootloader left
it corrupted with clocks disabled?

>  
>    clocks:
>      minItems: 1

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260724084153.1473-1-dongxuyang@eswincomputing.com?part=4

[PATCH v13 5/5] clocksource: dw_apb_timer: Use reset array API to handle all resets

[dongxuyang]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

timer_get_base_and_rate() only ever fetched a single, index-0 reset
control via of_reset_control_get(np, NULL), which does not consult
reset-names and always resolves to the first entry. With the binding
now allowing a second entry, a device tree that lists both lines would
leave the second entry permanently unasserted, since the driver never
touches it.

Replace it with devm_reset_control_array_get_optional_exclusive() to
fetch and control all reset lines listed in the device tree, ensuring
every line is properly asserted and deasserted rather than only the first.

Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
 drivers/clocksource/dw_apb_timer_of.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index 3245eb0c602d..ffe495a8416a 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -29,9 +29,11 @@ static int __init timer_get_base_and_rate(struct device_node *np,

 	/*
 	 * Reset the timer if the reset control is available, wiping
-	 * out the state the firmware may have left it
+	 * out the state the firmware may have left it.
+	 * Use array variant to handle multiple resets (e.g., timer
+	 * and APB interface resets) if specified in the device tree.
 	 */
-	rstc = of_reset_control_get(np, NULL);
+	rstc = of_reset_control_array_get_optional_exclusive(np);
 	if (!IS_ERR(rstc)) {
 		reset_control_assert(rstc);
 		reset_control_deassert(rstc);
--
2.34.1

Re: [PATCH v13 5/5] clocksource: dw_apb_timer: Use reset array API to handle all resets

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The patch dynamically allocates an exclusive reset control array using the unmanaged `of_` API but fails to free it, permanently locking shared APB resets and deadlocking other devices.
--

--- Patch [5]: [PATCH v13 5/5] clocksource: dw_apb_timer: Use reset array API to handle all resets ---
commit 015418d722b66a454000fd7a9c2606bea3f7e18b
Author: Xuyang Dong <dongxuyang@eswincomputing.com>

clocksource: dw_apb_timer: Use reset array API to handle all resets

This patch updates the timer initialization to fetch and pulse all reset lines
specified in the device tree by switching to the reset array API.

> Replace it with devm_reset_control_array_get_optional_exclusive() to
> fetch and control all reset lines listed in the device tree, ensuring
> every line is properly asserted and deasserted rather than only the first.

[Severity: Low]
This isn't a bug, but the commit message mentions using the managed
devm_reset_control_array_get_optional_exclusive function, while the code
below actually uses the unmanaged of_reset_control_array_get_optional_exclusive
function.

> diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
> --- a/drivers/clocksource/dw_apb_timer_of.c
> +++ b/drivers/clocksource/dw_apb_timer_of.c
[ ... ]
> @@ -29,9 +29,11 @@ static int __init timer_get_base_and_rate(struct device_node *np,
>  	/*
>  	 * Reset the timer if the reset control is available, wiping
> -	 * out the state the firmware may have left it
> +	 * out the state the firmware may have left it.
> +	 * Use array variant to handle multiple resets (e.g., timer
> +	 * and APB interface resets) if specified in the device tree.
>  	 */
> -	rstc = of_reset_control_get(np, NULL);
> +	rstc = of_reset_control_array_get_optional_exclusive(np);
>  	if (!IS_ERR(rstc)) {
>  		reset_control_assert(rstc);
>  		reset_control_deassert(rstc);
>  	}

[Severity: High]
Does this code leak the exclusive reset control array?

Since of_reset_control_array_get_optional_exclusive is used instead of the
managed devm variant, the returned rstc needs to be manually freed.

Because this API acquires exclusive references to the resets (which the
comment notes might include shared APB interface resets), exiting
timer_get_base_and_rate without calling reset_control_put(rstc) leaves
these resets permanently locked.

Could this prevent other devices on the bus from acquiring their shared
resets during probe by returning -EBUSY?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260724084153.1473-1-dongxuyang@eswincomputing.com?part=5