Re: [PATCH v7 08/34] pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [Low] The `AIROHA_PINCTRL_GPIO` macro is defined in the patch but is never used anywhere in the codebase.

Pre-existing issues:
- [High] The patch corrects the PCIe reset pinmux polarity for the EN7581 SoC but neglects to fix the identical issue for the AN7583 SoC, leaving its PCIe reset functionality broken.
--

--- Patch [8]: [PATCH v7 08/34] pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins ---
commit a65ef4d0c5f236d794130131b423b8c2bc834683
Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins

This commit corrects the pin numbering for PCIe reset pins on the AN7581
SoC to match the datasheet. It also fixes the pinmux configuration so that
selecting the PCIe reset function correctly enables it, rather than setting
the pins as GPIOs.

> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> index cad56ac3c0614..4bbda392625ad 100644
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
[ ... ]
> @@ -1405,6 +1413,45 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
>  	},
>  };
>  
> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val)			\
> +	{							\
> +		.name = (gpio),					\
> +		.regmap[0] = {					\
> +			AIROHA_FUNC_MUX,			\
> +			REG_GPIO_PON_MODE,			\
> +			(mux_val),				\
> +			(mux_val)				\
> +		},						\
> +		.regmap_size = 1,				\
> +	}

[Severity: Low]
Is it necessary to include AIROHA_PINCTRL_GPIO? It looks like this macro
is defined but never used anywhere in the codebase.

> +
> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)	\
> +	{							\
> +		.name = (gpio),					\
[ ... ]
> @@ -1430,7 +1477,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
>  			AIROHA_FUNC_MUX,
>  			REG_GPIO_PON_MODE,
>  			GPIO_PCIE_RESET2_MASK,
> -			GPIO_PCIE_RESET2_MASK
> +			0
>  		},
>  		.regmap_size = 1,
>  	},

[Severity: High]
This is a pre-existing issue, but by fixing the PCIe reset polarity for
the EN7581 SoC here, does the identical issue remain for the AN7583 SoC?

Looking at an7583_pcie_reset_func_group, it still configures the pins as
GPIOs rather than PCIe resets by using GPIO_PCIE_RESET0_MASK:

static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
	{
		.name = "pcie_reset0",
		.regmap[0] = {
			AIROHA_FUNC_MUX,
			REG_GPIO_PON_MODE,
			GPIO_PCIE_RESET0_MASK,
			GPIO_PCIE_RESET0_MASK
		},
		.regmap_size = 1,
	},
...

Should an7583_pcie_reset_func_group be updated similarly to ensure PCIe
reset works correctly on the AN7583 SoC?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260727074234.3761170-1-mikhail.kshevetskiy@iopsys.eu?part=8