From: sashiko-bot@kernel.org
To: "Louis-Alexis Eyraud" <louisalexis.eyraud@collabora.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v5 08/25] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets
Date: Sun, 02 Aug 2026 11:22:31 +0000 [thread overview]
Message-ID: <20260802112232.38DD81F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260801-mt8189-clocks-system-base-v5-8-ac4410697cc2@collabora.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `if` conditional block checking `compatible` strings in `mediatek,mt8186-clock.yaml` is missing the `contains:` keyword, which causes the condition to always fail.
--
--- Patch [8]: [PATCH v5 08/25] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets ---
commit 58f0ae2ed060320d3d6921afeb65e04b05e09665
Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets
This commit adds compatible strings and binding headers for the system and
base clock controllers, as well as reset controllers for the MediaTek MT8189
SoC. It also adds compatibles for frequency hopping and spread spectrum
clock functionality.
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
> index ab9f8cb7dd6ee..380dab8f4e983 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
[ ... ]
> @@ -133,6 +146,8 @@ allOf:
> - mediatek,mt8188-imgsys1-dip-nr
> - mediatek,mt8188-imgsys1-dip-top
> - mediatek,mt8188-ipesys
> + - mediatek,mt8189-ufscfg-ao
> + - mediatek,mt8189-ufscfg-pdn
[Severity: Medium]
Is the conditional block wrapping this list missing a `contains:` keyword
before the `enum:`?
Because `compatible` strings are arrays in the device tree, comparing them
directly to a scalar string list using `enum:` will always evaluate to false.
As a result, the requirement for `#reset-cells` will not be enforced for
these newly added hardware variants, allowing incomplete device tree nodes
to silently pass schema validation.
> then:
> required:
> - '#reset-cells'
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260801-mt8189-clocks-system-base-v5-0-ac4410697cc2@collabora.com?part=8
next prev parent reply other threads:[~2026-08-02 11:22 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-01 11:20 [PATCH v5 00/25] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 01/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 02/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 03/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 04/25] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 05/25] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 06/25] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 07/25] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 08/25] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot [this message]
2026-08-01 11:20 ` [PATCH v5 09/25] clk: mediatek: Harmonize mtk_pll_fenc related symbol names Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 10/25] clk: mediatek: pll: Add BAR reset register offsets Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 11/25] clk: mediatek: pll: Factorise pll power on/off sequences Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 12/25] clk: mediatek: pll: Add PLL stabilization delay definition Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 13/25] clk: mediatek: pll: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 14/25] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 15/25] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 16/25] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 17/25] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 18/25] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 19/25] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 20/25] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 21/25] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 22/25] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 23/25] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 24/25] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 25/25] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
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