From: sashiko-bot@kernel.org
To: "Louis-Alexis Eyraud" <louisalexis.eyraud@collabora.com>
Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v5 17/25] clk: mediatek: Add MT8189 topckgen clock support
Date: Sun, 02 Aug 2026 11:22:36 +0000 [thread overview]
Message-ID: <20260802112237.387A01F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260801-mt8189-clocks-system-base-v5-17-ac4410697cc2@collabora.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Use-After-Free occurs on the probe error path due to a lifecycle mismatch between manually unregistered clocks and devres-managed clock notifiers.
--
--- Patch [17]: [PATCH v5 17/25] clk: mediatek: Add MT8189 topckgen clock support ---
commit 7ad0ff152f786ba34328391087a43e6c3c80dd0b
Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
clk: mediatek: Add MT8189 topckgen clock support
Add support for the MT8189 topckgen clock controller, which provides
muxes and dividers for clock selection in other IP blocks.
> diff --git a/drivers/clk/mediatek/clk-mt8189-topckgen.c b/drivers/clk/mediatek/clk-mt8189-topckgen.c
> new file mode 100644
> index 0000000000000..f25c0711512c4
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8189-topckgen.c
[ ... ]
> +/* Register mux notifier for MFG mux */
> +static int clk_mt8189_reg_mfg_mux_notifier(struct device *dev,
> + struct clk *clk)
> +{
> + struct mtk_mux_nb *mfg_mux_nb;
> +
> + mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
> + if (!mfg_mux_nb)
> + return -ENOMEM;
> +
> + mfg_mux_nb->ops = &mtk_mux_clr_set_upd_ops;
> + mfg_mux_nb->bypass_index = 0; /* Bypass to CLK_TOP_MFG_REF_SEL */
> +
> + return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
[Severity: High]
Can this devres-managed registration cause a use-after-free if probe fails?
During probe, if a later step (like of_clk_add_hw_provider) fails in
__mtk_clk_simple_probe(), the error path manually unregisters and frees all
clocks before returning:
drivers/clk/mediatek/clk-mtk.c:__mtk_clk_simple_probe() {
...
unregister_muxes:
if (mcd->mux_clks)
mtk_clk_unregister_muxes(mcd->mux_clks,
mcd->num_mux_clks, clk_data);
...
}
After the error is returned, the driver core cleans up devres allocations,
which invokes clk_notifier_unregister() with the now-freed clk pointer. This
dereferences the freed pointer:
drivers/clk/clk.c:clk_notifier_unregister() {
...
list_for_each_entry(cn, &clk_notifier_list, node) {
if (cn->clk == clk) {
ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
clk->core->notifier_count--;
...
}
Should this notifier be manually unregistered on the error path before the
clocks are freed, instead of relying on devres?
> +}
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260801-mt8189-clocks-system-base-v5-0-ac4410697cc2@collabora.com?part=17
next prev parent reply other threads:[~2026-08-02 11:22 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-01 11:20 [PATCH v5 00/25] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 01/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 02/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 03/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 04/25] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 05/25] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 06/25] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 07/25] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 08/25] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 09/25] clk: mediatek: Harmonize mtk_pll_fenc related symbol names Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 10/25] clk: mediatek: pll: Add BAR reset register offsets Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 11/25] clk: mediatek: pll: Factorise pll power on/off sequences Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 12/25] clk: mediatek: pll: Add PLL stabilization delay definition Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 13/25] clk: mediatek: pll: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 14/25] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 15/25] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 16/25] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 17/25] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot [this message]
2026-08-01 11:21 ` [PATCH v5 18/25] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 19/25] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 20/25] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 21/25] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 22/25] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 23/25] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 24/25] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 25/25] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
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