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From: sashiko-bot@kernel.org
To: "Louis-Alexis Eyraud" <louisalexis.eyraud@collabora.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v5 06/25] dt-bindings: clock: mediatek: regroup MT8192 dt-bindings into MT8186
Date: Sun, 02 Aug 2026 11:22:33 +0000	[thread overview]
Message-ID: <20260802112234.36C721F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260801-mt8189-clocks-system-base-v5-6-ac4410697cc2@collabora.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `allOf` conditional block in `mediatek,mt8186-clock.yaml` incorrectly uses `enum` directly on the `compatible` property instead of `contains: enum:`, breaking device tree schema validation for MT8188 hardware variants.
--

--- Patch [6]: [PATCH v5 06/25] dt-bindings: clock: mediatek: regroup MT8192 dt-bindings into MT8186 ---
commit 06947e98086d9925a384efecc6b70a1f4b24045a
Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>

    dt-bindings: clock: mediatek: regroup MT8192 dt-bindings into MT8186

This commit regroups the MT8192 functional and system clock bindings into
the MT8186 binding files. It consolidates similar clock controller designs
to ease maintainability.

> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
> index 0bc2da60a6016..b5988d122e4dd 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
> @@ -58,6 +58,26 @@ properties:
>            - mediatek,mt8188-vencsys
>            - mediatek,mt8188-wpesys
>            - mediatek,mt8188-wpesys-vpp0
> +          - mediatek,mt8192-camsys
> +          - mediatek,mt8192-camsys_rawa
[ ... ]
> +          - mediatek,mt8192-vdecsys_soc
> +          - mediatek,mt8192-vdecsys
> +          - mediatek,mt8192-vencsys
>  
>    reg:
>      maxItems: 1

[Severity: Medium]
Does this file's allOf block incorrectly evaluate the compatible strings?

Looking further down in the same file:

Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml:allOf:
  allOf:
    - if:
        properties:
          compatible:
            enum:
              - mediatek,mt8188-camsys-rawa

Because the compatible property is evaluated as an array in Device Tree schemas,
does using enum directly instead of contains: enum: cause the if condition
to always evaluate to false?

If it fails to match the array, it appears validation falls through to the
else block, incorrectly enforcing '#reset-cells': false for MT8188 device nodes
that actually require resets.

Should this use contains: enum: instead to properly validate the hardware
variants?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260801-mt8189-clocks-system-base-v5-0-ac4410697cc2@collabora.com?part=6

  reply	other threads:[~2026-08-02 11:22 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-01 11:20 [PATCH v5 00/25] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 01/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 02/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 03/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 04/25] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 05/25] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-08-02 11:22   ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 06/25] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
2026-08-02 11:22   ` sashiko-bot [this message]
2026-08-01 11:20 ` [PATCH v5 07/25] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 08/25] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets Louis-Alexis Eyraud
2026-08-02 11:22   ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 09/25] clk: mediatek: Harmonize mtk_pll_fenc related symbol names Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 10/25] clk: mediatek: pll: Add BAR reset register offsets Louis-Alexis Eyraud
2026-08-02 11:22   ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 11/25] clk: mediatek: pll: Factorise pll power on/off sequences Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 12/25] clk: mediatek: pll: Add PLL stabilization delay definition Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 13/25] clk: mediatek: pll: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-08-02 11:22   ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 14/25] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 15/25] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 16/25] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
2026-08-02 11:22   ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 17/25] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
2026-08-02 11:22   ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 18/25] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 19/25] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 20/25] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 21/25] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 22/25] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 23/25] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 24/25] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-08-02 11:22   ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 25/25] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
2026-08-02 11:22   ` sashiko-bot

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