From: sashiko-bot@kernel.org
To: "Louis-Alexis Eyraud" <louisalexis.eyraud@collabora.com>
Cc: conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v5 24/25] clk: mediatek: Add MT8189 scp clock support
Date: Sun, 02 Aug 2026 11:22:37 +0000 [thread overview]
Message-ID: <20260802112238.38FD41F00A3E@smtp.kernel.org> (raw)
In-Reply-To: <20260801-mt8189-clocks-system-base-v5-24-ac4410697cc2@collabora.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] The clock provider is not unregistered when `mtk_register_reset_controller_with_dev()` fails, leading to a Use-After-Free.
--
--- Patch [24]: [PATCH v5 24/25] clk: mediatek: Add MT8189 scp clock support ---
commit cfb69aff7b6d0acebfb8964210288168aecca4f1
Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
clk: mediatek: Add MT8189 scp clock support
Add support for the MT8189 scp clock controller, which provides
clock gate control for System Control Processor.
> diff --git a/drivers/clk/mediatek/clk-mt8189-scp.c b/drivers/clk/mediatek/clk-mt8189-scp.c
> new file mode 100644
> index 0000000000000..75197cd98b521
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8189-scp.c
[ ... ]
> +static const struct of_device_id of_match_clk_mt8189_scp[] = {
> + { .compatible = "mediatek,mt8189-scp-clk", .data = &scp_mcd },
> + { .compatible = "mediatek,mt8189-scp-i2c-clk", .data = &scp_iic_mcd },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_scp);
> +
> +static struct platform_driver clk_mt8189_scp_drv = {
> + .probe = mtk_clk_simple_probe,
[Severity: High]
This is a pre-existing issue, but I noticed this driver relies on
mtk_clk_simple_probe(), which appears to have a use-after-free on its error
path.
In drivers/clk/mediatek/clk-mtk.c:__mtk_clk_simple_probe(), the clock
provider is registered via of_clk_add_hw_provider(). If the subsequent reset
controller registration fails, the code jumps to unregister_clks:
r = mtk_register_reset_controller_with_dev(&pdev->dev,
mcd->rst_desc);
if (r)
goto unregister_clks;
The cleanup path then frees clk_data without unregistering the clock provider
first:
unregister_clks:
mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
free_data:
mtk_free_clk_data(clk_data);
Because of_clk_del_provider() is never called on this error path, the OF
provider list retains a dangling pointer to the freed clk_data. Could a
subsequent clk_get() that matches this provider's device node dereference
the freed memory?
> + .remove = mtk_clk_simple_remove,
> + .driver = {
> + .name = "clk-mt8189-scp",
> + .of_match_table = of_match_clk_mt8189_scp,
> + },
> +};
> +module_platform_driver(clk_mt8189_scp_drv);
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260801-mt8189-clocks-system-base-v5-0-ac4410697cc2@collabora.com?part=24
next prev parent reply other threads:[~2026-08-02 11:22 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-01 11:20 [PATCH v5 00/25] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 01/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 02/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 03/25] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195 Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 04/25] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 05/25] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 06/25] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 07/25] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 08/25] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 09/25] clk: mediatek: Harmonize mtk_pll_fenc related symbol names Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 10/25] clk: mediatek: pll: Add BAR reset register offsets Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:20 ` [PATCH v5 11/25] clk: mediatek: pll: Factorise pll power on/off sequences Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 12/25] clk: mediatek: pll: Add PLL stabilization delay definition Louis-Alexis Eyraud
2026-08-01 11:20 ` [PATCH v5 13/25] clk: mediatek: pll: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 14/25] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 15/25] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 16/25] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 17/25] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
2026-08-01 11:21 ` [PATCH v5 18/25] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 19/25] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 20/25] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 21/25] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 22/25] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 23/25] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
2026-08-01 11:21 ` [PATCH v5 24/25] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot [this message]
2026-08-01 11:21 ` [PATCH v5 25/25] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
2026-08-02 11:22 ` sashiko-bot
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