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From: sashiko-bot@kernel.org
To: "Dmitry Baryshkov" <dmitry.baryshkov@oss.qualcomm.com>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 05/12] iommu: qcom_iommu: handle the SMMU global register space
Date: Sun, 09 Aug 2026 20:29:00 +0000	[thread overview]
Message-ID: <20260809202901.871E61F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260809-msm8974-iommu-upstream-v1-5-87f5cd492560@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:

New issues:
- [High] Context bank state is not reprogrammed upon runtime resume, leading to translation failures for instances in power domains.
- [High] Skipping the FSR clear at probe time allows a pending bootloader fault to trigger an interrupt before `ctx->domain` is set, causing a NULL pointer dereference.

Pre-existing issues:
- [High] The shared IRQ handler accesses hardware registers without checking if the device is active, and there is no IRQ synchronization in the suspend path.
- [High] Unbinding the parent IOMMU device causes a NULL pointer dereference in the child context device's remove callback.
--

--- Patch [5]: [PATCH 05/12] iommu: qcom_iommu: handle the SMMU global register space ---
commit bf26052ef6d0329129f71ba618d88c9f30a2725a
Author: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

iommu: qcom_iommu: handle the SMMU global register space

On msm8974 the OS has to access the SMMU global register space: the
non-secured instances need it fully programmed and even the TZ-managed
ones expose OS-writable implementation-defined registers in it. The
driver only knows about the msm8916-style "SMMU local" region in
resource 0, and has no accessors for the global space.

> diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> index 77c01f217d7ea..428b18697244c 100644
> --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c

[ ... ]

> @@ -213,6 +256,35 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
>  	return IRQ_HANDLED;
>  }
>  

[Severity: High]
This is a pre-existing issue, but shouldn't the shared IRQ handler check if
the device is active before accessing hardware registers?

The interrupt line is registered with IRQF_SHARED. If another device sharing
the line asserts an interrupt while the IOMMU's power domain is suspended,
qcom_iommu_fault() executes and accesses ARM_SMMU_CB_FSR without waking the
device via pm_runtime_get_if_active(). Accessing unpowered MMIO registers
can trigger an asynchronous external abort or bus stall.

Also, qcom_iommu_suspend() disables clocks without calling
synchronize_irq(), allowing race conditions if the shared handler is running
mid-flight.

> +static void qcom_iommu_program_ctx(struct qcom_iommu_dev *qcom_iommu,
> +				   struct qcom_iommu_ctx *ctx)
> +{
> +	/* Disable context bank before programming */
> +	iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);

[Severity: High]
Is it necessary to reprogram this cached state during runtime resume?

When the PM domain collapses and subsequently resumes, the non-secure context
banks remain unconfigured, breaking any further DMA translations.

Looking at qcom_iommu_resume(), it restores secure configurations but
doesn't restore the OS-managed (non-secure) context banks by looping over
them and calling qcom_iommu_program_ctx().

[ ... ]

> @@ -749,9 +773,10 @@ static int qcom_iommu_ctx_probe(struct platform_device *pdev)
>  		ctx->secured_ctx = true;
>  
>  	/* clear IRQs before registering fault handler, just in case the
> -	 * boot-loader left us a surprise:
> +	 * boot-loader left us a surprise.  Instances with a power domain
> +	 * may not be accessible yet; they are reset at first resume.
>  	 */
> -	if (!ctx->secured_ctx) {
> +	if (!ctx->secured_ctx && !qcom_iommu->cfg) {

[Severity: High]
If a bootloader fault is pending and we bypass clearing the Fault Status
Register (FSR) here, could it trigger an interrupt before ctx->domain is set?

When devm_request_irq() enables the shared IRQ line a few lines later, the
pending interrupt could fire immediately. The handler qcom_iommu_fault()
executes and calls report_iommu_fault(ctx->domain, ...).

Because ctx->domain is only assigned later during device attachment
(qcom_iommu_init_domain), it is currently NULL, which report_iommu_fault()
will dereference.

>  		ret = pm_runtime_resume_and_get(dev->parent);
>  		if (ret)
>  			return ret;

[ ... ]

[Severity: High]
This is a pre-existing issue, but can unbinding the parent IOMMU device cause
a NULL pointer dereference in the child context device's remove callback?

When the parent driver is unbound, qcom_iommu_device_remove() sets its private
data to NULL via platform_set_drvdata(pdev, NULL). Subsequently, devres tears
down the child devices, invoking qcom_iommu_ctx_remove().

This child callback calls dev_get_drvdata(pdev->dev.parent) to retrieve the
parent's data, which is now NULL, and immediately dereferences it:

drivers/iommu/arm/arm-smmu/qcom_iommu.c:qcom_iommu_ctx_remove() {
    ...
    struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent);
    ...
    qcom_iommu->ctxs[ctx->asid] = NULL;
    ...
}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260809-msm8974-iommu-upstream-v1-0-87f5cd492560@oss.qualcomm.com?part=5

  reply	other threads:[~2026-08-09 20:29 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-09 20:15 [PATCH 00/12] iommu: qcom_iommu: implement support for instances on MSM8974 Dmitry Baryshkov
2026-08-09 20:15 ` [PATCH 01/12] dt-bindings: iommu: qcom,iommu: document the MSM8974 IOMMUs Dmitry Baryshkov
2026-08-09 20:28   ` sashiko-bot
2026-08-09 20:15 ` [PATCH 02/12] iommu: arm-smmu: add global register definitions used by the QSMMU Dmitry Baryshkov
2026-08-09 20:15 ` [PATCH 03/12] iommu: qcom_iommu: extract context bank programming into a helper Dmitry Baryshkov
2026-08-09 20:27   ` sashiko-bot
2026-08-09 20:15 ` [PATCH 04/12] iommu: qcom_iommu: support the short-descriptor pagetable format Dmitry Baryshkov
2026-08-09 20:30   ` sashiko-bot
2026-08-09 20:15 ` [PATCH 05/12] iommu: qcom_iommu: handle the SMMU global register space Dmitry Baryshkov
2026-08-09 20:29   ` sashiko-bot [this message]
2026-08-09 20:15 ` [PATCH 06/12] iommu: qcom_iommu: support non-TZ-managed instances Dmitry Baryshkov
2026-08-09 20:39   ` sashiko-bot
2026-08-09 20:15 ` [PATCH 07/12] iommu: qcom_iommu: restore context bank state after power collapse Dmitry Baryshkov
2026-08-09 20:28   ` sashiko-bot
2026-08-09 20:15 ` [PATCH 08/12] iommu: qcom_iommu: halt the micro-MMU while programming context banks Dmitry Baryshkov
2026-08-09 20:33   ` sashiko-bot
2026-08-09 20:15 ` [PATCH 09/12] iommu: qcom_iommu: allow faulting transactions to terminate Dmitry Baryshkov
2026-08-09 20:28   ` sashiko-bot
2026-08-09 20:15 ` [PATCH 10/12] iommu: qcom_iommu: program BFP (prefetch) settings Dmitry Baryshkov
2026-08-09 20:28   ` sashiko-bot
2026-08-09 20:15 ` [PATCH 11/12] iommu: qcom_iommu: add the MSM8974 instances Dmitry Baryshkov
2026-08-09 20:28   ` sashiko-bot
2026-08-09 20:15 ` [PATCH 12/12] ARM: dts: qcom: msm8974: add the IOMMUs Dmitry Baryshkov
2026-08-10 10:16 ` [PATCH 00/12] iommu: qcom_iommu: implement support for instances on MSM8974 Luca Weiss

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