Re: [PATCH v5 15/17] rtc: rzn1: Add OF match data to gate SUBU register access

[Alexandre Belloni <alexandre.belloni@bootlin.com>]

On 21/08/2026 21:37:43+0100, Lad, Prabhakar wrote:
> Hi Alexandre,
> 
> On Fri, Aug 21, 2026 at 5:40 PM Alexandre Belloni
> <alexandre.belloni@bootlin.com> wrote:
> >
> > Hello,
> >
> > On 21/08/2026 14:56:06+0100, Prabhakar wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > The RZ/N1 RTC driver selects SCMP mode only when an optional xtal clock
> > > is provided at a valid rate other than 32768 Hz. Without an xtal clock,
> > > or when it runs at 32768 Hz, the driver uses SUBU mode.
> > >
> > > However, the RTCA0SUBU register used by SUBU mode is not present on all
> > > SoCs that integrate a similar variant of the RTC block. Allowing SUBU
> > > mode on those variants would expose RTC offset operations that access a
> > > non-existent register.
> > >
> > > Add OF match data to describe whether the RTC supports the SUBU register.
> > > Reject probe with -EOPNOTSUPP when SUBU mode would be selected on a
> > > variant without SUBU support.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Suggested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> > > ---
> > > v4->v5:
> > > - Renamed rzn1_data to rzn1_rtc_rzn1_data
> > > - Added a print message to indicate that SUBU mode is not supported
> > >   on the variant.
> > > - Added a comment to indicate that the xtal clock is NULL when SUBU
> > >   mode is not supported.
> > > - Added Suggested-by tag from Wolfram.
> > >
> > > v3->v4:
> > > - New patch
> > > ---
> > >  drivers/rtc/rtc-rzn1.c | 22 ++++++++++++++++++++--
> > >  1 file changed, 20 insertions(+), 2 deletions(-)
> > >
> >
> > This doesn't apply cleanly, can you rebase on rtc-next? If you do so
> > today, I'll include the series this merge window.
> >
> Oouch, I'll do that right away. Hopefully Im not late.

Not late, don't forget the other comment about the sentinel from Wolfram.


-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com