* [PATCH 1/8] ARM: tegra: Clean up AHUB on Tegra124
2026-09-02 10:17 [PATCH 0/8] arm64: tegra: Clean up AHUB device tree nodes Thierry Reding
@ 2026-09-02 10:17 ` Thierry Reding
2026-09-02 10:23 ` sashiko-bot
2026-09-02 10:17 ` [PATCH 2/8] arm64: tegra: Clean up AHUB on Tegra132 Thierry Reding
` (7 subsequent siblings)
8 siblings, 1 reply; 14+ messages in thread
From: Thierry Reding @ 2026-09-02 10:17 UTC (permalink / raw)
To: Thierry Reding, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jonathan Hunter
Cc: Charan Pedumuru, devicetree, linux-tegra, linux-kernel,
Thierry Reding
From: Thierry Reding <treding@nvidia.com>
Use #address-cells = <1> and #size-cells = <1> because we don't need
64-bit register addressing for this hardware. While at it, also adjust
the ranges property to encompass the entire AHUB range as per the TRM.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm/boot/dts/nvidia/tegra124.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi
index ce4efa1de509..7a71dba42dc0 100644
--- a/arch/arm/boot/dts/nvidia/tegra124.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi
@@ -1114,13 +1114,13 @@ ahub@70300000 {
"rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
"rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
"rx9", "tx9";
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
+ ranges = <0x7030000 0x0 0x70300000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
tegra_i2s0: i2s@70301000 {
compatible = "nvidia,tegra124-i2s";
- reg = <0x0 0x70301000 0x0 0x100>;
+ reg = <0x70301000 0x100>;
nvidia,ahub-cif-ids = <4 4>;
clocks = <&tegra_car TEGRA124_CLK_I2S0>;
resets = <&tegra_car 30>;
@@ -1130,7 +1130,7 @@ tegra_i2s0: i2s@70301000 {
tegra_i2s1: i2s@70301100 {
compatible = "nvidia,tegra124-i2s";
- reg = <0x0 0x70301100 0x0 0x100>;
+ reg = <0x70301100 0x100>;
nvidia,ahub-cif-ids = <5 5>;
clocks = <&tegra_car TEGRA124_CLK_I2S1>;
resets = <&tegra_car 11>;
@@ -1140,7 +1140,7 @@ tegra_i2s1: i2s@70301100 {
tegra_i2s2: i2s@70301200 {
compatible = "nvidia,tegra124-i2s";
- reg = <0x0 0x70301200 0x0 0x100>;
+ reg = <0x70301200 0x100>;
nvidia,ahub-cif-ids = <6 6>;
clocks = <&tegra_car TEGRA124_CLK_I2S2>;
resets = <&tegra_car 18>;
@@ -1150,7 +1150,7 @@ tegra_i2s2: i2s@70301200 {
tegra_i2s3: i2s@70301300 {
compatible = "nvidia,tegra124-i2s";
- reg = <0x0 0x70301300 0x0 0x100>;
+ reg = <0x70301300 0x100>;
nvidia,ahub-cif-ids = <7 7>;
clocks = <&tegra_car TEGRA124_CLK_I2S3>;
resets = <&tegra_car 101>;
@@ -1160,7 +1160,7 @@ tegra_i2s3: i2s@70301300 {
tegra_i2s4: i2s@70301400 {
compatible = "nvidia,tegra124-i2s";
- reg = <0x0 0x70301400 0x0 0x100>;
+ reg = <0x70301400 0x100>;
nvidia,ahub-cif-ids = <8 8>;
clocks = <&tegra_car TEGRA124_CLK_I2S4>;
resets = <&tegra_car 102>;
--
2.55.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 1/8] ARM: tegra: Clean up AHUB on Tegra124
2026-09-02 10:17 ` [PATCH 1/8] ARM: tegra: Clean up AHUB on Tegra124 Thierry Reding
@ 2026-09-02 10:23 ` sashiko-bot
0 siblings, 0 replies; 14+ messages in thread
From: sashiko-bot @ 2026-09-02 10:23 UTC (permalink / raw)
To: Thierry Reding; +Cc: robh, conor+dt, devicetree
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The child bus address in the 'ranges' property of the ahub node is missing a trailing zero, breaking address translation for all I2S/AHUB child nodes.
--
commit 801981d1969d9fdac375d63ff0a71f218d782d11
Author: Thierry Reding <treding@nvidia.com>
ARM: tegra: Clean up AHUB on Tegra124
This commit updates the #address-cells and #size-cells properties to <1>
for the AHUB on Tegra124, since 64-bit addressing is unnecessary for this
hardware. It also adjusts the ranges property to encompass the entire AHUB
range according to the TRM.
> diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi
> index ce4efa1de509b..7a71dba42dc0c 100644
> --- a/arch/arm/boot/dts/nvidia/tegra124.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi
> @@ -1114,13 +1114,13 @@ ahub@70300000 {
[ ... ]
> - ranges;
> - #address-cells = <2>;
> - #size-cells = <2>;
> + ranges = <0x7030000 0x0 0x70300000 0x10000>;
[Severity: High]
Does this child bus address miss a trailing zero? The ranges property here
specifies a child base address of 0x7030000, but it looks like it should
be 0x70300000 to match the ahub node address and the subsequent child
device addresses.
If the child base address is set to 0x7030000, wouldn't the translation map
fail to cover child nodes starting at 0x70301000 (such as tegra_i2s0)? This
appears to cause all I2S and other audio devices under the AHUB to fail to
probe unconditionally on boot, since the OF core cannot translate their
memory addresses properly.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com?part=1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/8] arm64: tegra: Clean up AHUB on Tegra132
2026-09-02 10:17 [PATCH 0/8] arm64: tegra: Clean up AHUB device tree nodes Thierry Reding
2026-09-02 10:17 ` [PATCH 1/8] ARM: tegra: Clean up AHUB on Tegra124 Thierry Reding
@ 2026-09-02 10:17 ` Thierry Reding
2026-09-02 10:17 ` [PATCH 3/8] arm64: tegra: Adjust AHUB range on Tegra210 Thierry Reding
` (6 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Thierry Reding @ 2026-09-02 10:17 UTC (permalink / raw)
To: Thierry Reding, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jonathan Hunter
Cc: Charan Pedumuru, devicetree, linux-tegra, linux-kernel,
Thierry Reding
From: Thierry Reding <treding@nvidia.com>
Use #address-cells = <1> and #size-cells = <1> because we don't need
64-bit register addressing for this hardware. While at it, also adjust
the ranges property to encompass the entire AHUB range as per the TRM.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra132.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
index 26cd11a8a4a1..3463fa637b37 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
@@ -936,13 +936,13 @@ ahub@70300000 {
"rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
"rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
"rx9", "tx9";
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
+ ranges = <0x70300000 0x0 0x70300000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
tegra_i2s0: i2s@70301000 {
compatible = "nvidia,tegra124-i2s";
- reg = <0x0 0x70301000 0x0 0x100>;
+ reg = <0x70301000 0x100>;
nvidia,ahub-cif-ids = <4 4>;
clocks = <&tegra_car TEGRA124_CLK_I2S0>;
clock-names = "i2s";
@@ -953,7 +953,7 @@ tegra_i2s0: i2s@70301000 {
tegra_i2s1: i2s@70301100 {
compatible = "nvidia,tegra124-i2s";
- reg = <0x0 0x70301100 0x0 0x100>;
+ reg = <0x70301100 0x100>;
nvidia,ahub-cif-ids = <5 5>;
clocks = <&tegra_car TEGRA124_CLK_I2S1>;
clock-names = "i2s";
@@ -964,7 +964,7 @@ tegra_i2s1: i2s@70301100 {
tegra_i2s2: i2s@70301200 {
compatible = "nvidia,tegra124-i2s";
- reg = <0x0 0x70301200 0x0 0x100>;
+ reg = <0x70301200 0x100>;
nvidia,ahub-cif-ids = <6 6>;
clocks = <&tegra_car TEGRA124_CLK_I2S2>;
clock-names = "i2s";
@@ -975,7 +975,7 @@ tegra_i2s2: i2s@70301200 {
tegra_i2s3: i2s@70301300 {
compatible = "nvidia,tegra124-i2s";
- reg = <0x0 0x70301300 0x0 0x100>;
+ reg = <0x70301300 0x100>;
nvidia,ahub-cif-ids = <7 7>;
clocks = <&tegra_car TEGRA124_CLK_I2S3>;
clock-names = "i2s";
@@ -986,7 +986,7 @@ tegra_i2s3: i2s@70301300 {
tegra_i2s4: i2s@70301400 {
compatible = "nvidia,tegra124-i2s";
- reg = <0x0 0x70301400 0x0 0x100>;
+ reg = <0x70301400 0x100>;
nvidia,ahub-cif-ids = <8 8>;
clocks = <&tegra_car TEGRA124_CLK_I2S4>;
clock-names = "i2s";
--
2.55.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 3/8] arm64: tegra: Adjust AHUB range on Tegra210
2026-09-02 10:17 [PATCH 0/8] arm64: tegra: Clean up AHUB device tree nodes Thierry Reding
2026-09-02 10:17 ` [PATCH 1/8] ARM: tegra: Clean up AHUB on Tegra124 Thierry Reding
2026-09-02 10:17 ` [PATCH 2/8] arm64: tegra: Clean up AHUB on Tegra132 Thierry Reding
@ 2026-09-02 10:17 ` Thierry Reding
2026-09-02 10:17 ` [PATCH 4/8] arm64: tegra: Clean up AHUB on Tegra186 Thierry Reding
` (5 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Thierry Reding @ 2026-09-02 10:17 UTC (permalink / raw)
To: Thierry Reding, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jonathan Hunter
Cc: Charan Pedumuru, devicetree, linux-tegra, linux-kernel,
Thierry Reding
From: Thierry Reding <treding@nvidia.com>
The AHUB range is a full 64 KiB according to the TRM, so update the
ranges property accordingly. This is merely cosmetic.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 5f5e5370d709..9cc4c89dd1d6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1461,7 +1461,7 @@ tegra_ahub: ahub@702d0800 {
assigned-clock-rates = <81600000>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x702d0000 0x702d0000 0x0000e400>;
+ ranges = <0x702d0000 0x702d0000 0x00010000>;
status = "disabled";
tegra_admaif: admaif@702d0000 {
--
2.55.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 4/8] arm64: tegra: Clean up AHUB on Tegra186
2026-09-02 10:17 [PATCH 0/8] arm64: tegra: Clean up AHUB device tree nodes Thierry Reding
` (2 preceding siblings ...)
2026-09-02 10:17 ` [PATCH 3/8] arm64: tegra: Adjust AHUB range on Tegra210 Thierry Reding
@ 2026-09-02 10:17 ` Thierry Reding
2026-09-02 10:17 ` [PATCH 5/8] arm64: tegra: Clean up AHUB on Tegra194 Thierry Reding
` (4 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Thierry Reding @ 2026-09-02 10:17 UTC (permalink / raw)
To: Thierry Reding, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jonathan Hunter
Cc: Charan Pedumuru, devicetree, linux-tegra, linux-kernel,
Thierry Reding
From: Thierry Reding <treding@nvidia.com>
Use #address-cells = <1> and #size-cells = <1> because we don't need
64-bit register addressing for this hardware. While at it, also adjust
the ranges property to encompass the entire AHUB range as per the TRM.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 ++++++++++++++++----------------
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 705af0373a09..623d5e654323 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -142,15 +142,15 @@ tegra_ahub: ahub@2900800 {
assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
assigned-clock-rates = <81600000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x02900000 0x0 0x02900000 0x20000>;
status = "disabled";
tegra_i2s1: i2s@2901000 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901000 0x0 0x100>;
+ reg = <0x2901000 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S1>,
<&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -164,7 +164,7 @@ tegra_i2s1: i2s@2901000 {
tegra_i2s2: i2s@2901100 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901100 0x0 0x100>;
+ reg = <0x2901100 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S2>,
<&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -178,7 +178,7 @@ tegra_i2s2: i2s@2901100 {
tegra_i2s3: i2s@2901200 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901200 0x0 0x100>;
+ reg = <0x2901200 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S3>,
<&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -192,7 +192,7 @@ tegra_i2s3: i2s@2901200 {
tegra_i2s4: i2s@2901300 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901300 0x0 0x100>;
+ reg = <0x2901300 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S4>,
<&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -206,7 +206,7 @@ tegra_i2s4: i2s@2901300 {
tegra_i2s5: i2s@2901400 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901400 0x0 0x100>;
+ reg = <0x2901400 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S5>,
<&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -220,7 +220,7 @@ tegra_i2s5: i2s@2901400 {
tegra_i2s6: i2s@2901500 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901500 0x0 0x100>;
+ reg = <0x2901500 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S6>,
<&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -234,7 +234,7 @@ tegra_i2s6: i2s@2901500 {
tegra_sfc1: sfc@2902000 {
compatible = "nvidia,tegra186-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x2902000 0x0 0x200>;
+ reg = <0x2902000 0x200>;
sound-name-prefix = "SFC1";
status = "disabled";
};
@@ -242,7 +242,7 @@ tegra_sfc1: sfc@2902000 {
tegra_sfc2: sfc@2902200 {
compatible = "nvidia,tegra186-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x2902200 0x0 0x200>;
+ reg = <0x2902200 0x200>;
sound-name-prefix = "SFC2";
status = "disabled";
};
@@ -250,7 +250,7 @@ tegra_sfc2: sfc@2902200 {
tegra_sfc3: sfc@2902400 {
compatible = "nvidia,tegra186-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x2902400 0x0 0x200>;
+ reg = <0x2902400 0x200>;
sound-name-prefix = "SFC3";
status = "disabled";
};
@@ -258,7 +258,7 @@ tegra_sfc3: sfc@2902400 {
tegra_sfc4: sfc@2902600 {
compatible = "nvidia,tegra186-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x2902600 0x0 0x200>;
+ reg = <0x2902600 0x200>;
sound-name-prefix = "SFC4";
status = "disabled";
};
@@ -266,7 +266,7 @@ tegra_sfc4: sfc@2902600 {
tegra_amx1: amx@2903000 {
compatible = "nvidia,tegra186-amx",
"nvidia,tegra210-amx";
- reg = <0x0 0x2903000 0x0 0x100>;
+ reg = <0x2903000 0x100>;
sound-name-prefix = "AMX1";
status = "disabled";
};
@@ -274,7 +274,7 @@ tegra_amx1: amx@2903000 {
tegra_amx2: amx@2903100 {
compatible = "nvidia,tegra186-amx",
"nvidia,tegra210-amx";
- reg = <0x0 0x2903100 0x0 0x100>;
+ reg = <0x2903100 0x100>;
sound-name-prefix = "AMX2";
status = "disabled";
};
@@ -282,7 +282,7 @@ tegra_amx2: amx@2903100 {
tegra_amx3: amx@2903200 {
compatible = "nvidia,tegra186-amx",
"nvidia,tegra210-amx";
- reg = <0x0 0x2903200 0x0 0x100>;
+ reg = <0x2903200 0x100>;
sound-name-prefix = "AMX3";
status = "disabled";
};
@@ -290,7 +290,7 @@ tegra_amx3: amx@2903200 {
tegra_amx4: amx@2903300 {
compatible = "nvidia,tegra186-amx",
"nvidia,tegra210-amx";
- reg = <0x0 0x2903300 0x0 0x100>;
+ reg = <0x2903300 0x100>;
sound-name-prefix = "AMX4";
status = "disabled";
};
@@ -298,7 +298,7 @@ tegra_amx4: amx@2903300 {
tegra_adx1: adx@2903800 {
compatible = "nvidia,tegra186-adx",
"nvidia,tegra210-adx";
- reg = <0x0 0x2903800 0x0 0x100>;
+ reg = <0x2903800 0x100>;
sound-name-prefix = "ADX1";
status = "disabled";
};
@@ -306,7 +306,7 @@ tegra_adx1: adx@2903800 {
tegra_adx2: adx@2903900 {
compatible = "nvidia,tegra186-adx",
"nvidia,tegra210-adx";
- reg = <0x0 0x2903900 0x0 0x100>;
+ reg = <0x2903900 0x100>;
sound-name-prefix = "ADX2";
status = "disabled";
};
@@ -314,7 +314,7 @@ tegra_adx2: adx@2903900 {
tegra_adx3: adx@2903a00 {
compatible = "nvidia,tegra186-adx",
"nvidia,tegra210-adx";
- reg = <0x0 0x2903a00 0x0 0x100>;
+ reg = <0x2903a00 0x100>;
sound-name-prefix = "ADX3";
status = "disabled";
};
@@ -322,14 +322,14 @@ tegra_adx3: adx@2903a00 {
tegra_adx4: adx@2903b00 {
compatible = "nvidia,tegra186-adx",
"nvidia,tegra210-adx";
- reg = <0x0 0x2903b00 0x0 0x100>;
+ reg = <0x2903b00 0x100>;
sound-name-prefix = "ADX4";
status = "disabled";
};
tegra_dmic1: dmic@2904000 {
compatible = "nvidia,tegra210-dmic";
- reg = <0x0 0x2904000 0x0 0x100>;
+ reg = <0x2904000 0x100>;
clocks = <&bpmp TEGRA186_CLK_DMIC1>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
@@ -341,7 +341,7 @@ tegra_dmic1: dmic@2904000 {
tegra_dmic2: dmic@2904100 {
compatible = "nvidia,tegra210-dmic";
- reg = <0x0 0x2904100 0x0 0x100>;
+ reg = <0x2904100 0x100>;
clocks = <&bpmp TEGRA186_CLK_DMIC2>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
@@ -353,7 +353,7 @@ tegra_dmic2: dmic@2904100 {
tegra_dmic3: dmic@2904200 {
compatible = "nvidia,tegra210-dmic";
- reg = <0x0 0x2904200 0x0 0x100>;
+ reg = <0x2904200 0x100>;
clocks = <&bpmp TEGRA186_CLK_DMIC3>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
@@ -365,7 +365,7 @@ tegra_dmic3: dmic@2904200 {
tegra_dmic4: dmic@2904300 {
compatible = "nvidia,tegra210-dmic";
- reg = <0x0 0x2904300 0x0 0x100>;
+ reg = <0x2904300 0x100>;
clocks = <&bpmp TEGRA186_CLK_DMIC4>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
@@ -377,7 +377,7 @@ tegra_dmic4: dmic@2904300 {
tegra_dspk1: dspk@2905000 {
compatible = "nvidia,tegra186-dspk";
- reg = <0x0 0x2905000 0x0 0x100>;
+ reg = <0x2905000 0x100>;
clocks = <&bpmp TEGRA186_CLK_DSPK1>;
clock-names = "dspk";
assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
@@ -389,7 +389,7 @@ tegra_dspk1: dspk@2905000 {
tegra_dspk2: dspk@2905100 {
compatible = "nvidia,tegra186-dspk";
- reg = <0x0 0x2905100 0x0 0x100>;
+ reg = <0x2905100 0x100>;
clocks = <&bpmp TEGRA186_CLK_DSPK2>;
clock-names = "dspk";
assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
@@ -402,9 +402,9 @@ tegra_dspk2: dspk@2905100 {
tegra_ope1: processing-engine@2908000 {
compatible = "nvidia,tegra186-ope",
"nvidia,tegra210-ope";
- reg = <0x0 0x2908000 0x0 0x100>;
- #address-cells = <2>;
- #size-cells = <2>;
+ reg = <0x2908000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
ranges;
sound-name-prefix = "OPE1";
status = "disabled";
@@ -412,20 +412,20 @@ tegra_ope1: processing-engine@2908000 {
equalizer@2908100 {
compatible = "nvidia,tegra186-peq",
"nvidia,tegra210-peq";
- reg = <0x0 0x2908100 0x0 0x100>;
+ reg = <0x2908100 0x100>;
};
dynamic-range-compressor@2908200 {
compatible = "nvidia,tegra186-mbdrc",
"nvidia,tegra210-mbdrc";
- reg = <0x0 0x2908200 0x0 0x200>;
+ reg = <0x2908200 0x200>;
};
};
tegra_mvc1: mvc@290a000 {
compatible = "nvidia,tegra186-mvc",
"nvidia,tegra210-mvc";
- reg = <0x0 0x290a000 0x0 0x200>;
+ reg = <0x290a000 0x200>;
sound-name-prefix = "MVC1";
status = "disabled";
};
@@ -433,7 +433,7 @@ tegra_mvc1: mvc@290a000 {
tegra_mvc2: mvc@290a200 {
compatible = "nvidia,tegra186-mvc",
"nvidia,tegra210-mvc";
- reg = <0x0 0x290a200 0x0 0x200>;
+ reg = <0x290a200 0x200>;
sound-name-prefix = "MVC2";
status = "disabled";
};
@@ -441,14 +441,14 @@ tegra_mvc2: mvc@290a200 {
tegra_amixer: amixer@290bb00 {
compatible = "nvidia,tegra186-amixer",
"nvidia,tegra210-amixer";
- reg = <0x0 0x290bb00 0x0 0x800>;
+ reg = <0x290bb00 0x800>;
sound-name-prefix = "MIXER1";
status = "disabled";
};
tegra_admaif: admaif@290f000 {
compatible = "nvidia,tegra186-admaif";
- reg = <0x0 0x0290f000 0x0 0x1000>;
+ reg = <0x0290f000 0x1000>;
dmas = <&adma 1>, <&adma 1>,
<&adma 2>, <&adma 2>,
<&adma 3>, <&adma 3>,
@@ -494,7 +494,7 @@ tegra_admaif: admaif@290f000 {
tegra_asrc: asrc@2910000 {
compatible = "nvidia,tegra186-asrc";
- reg = <0x0 0x2910000 0x0 0x2000>;
+ reg = <0x2910000 0x2000>;
sound-name-prefix = "ASRC1";
status = "disabled";
};
--
2.55.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 5/8] arm64: tegra: Clean up AHUB on Tegra194
2026-09-02 10:17 [PATCH 0/8] arm64: tegra: Clean up AHUB device tree nodes Thierry Reding
` (3 preceding siblings ...)
2026-09-02 10:17 ` [PATCH 4/8] arm64: tegra: Clean up AHUB on Tegra186 Thierry Reding
@ 2026-09-02 10:17 ` Thierry Reding
2026-09-02 10:17 ` [PATCH 6/8] arm64: tegra: Clean up AHUB on Tegra234 Thierry Reding
` (3 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Thierry Reding @ 2026-09-02 10:17 UTC (permalink / raw)
To: Thierry Reding, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jonathan Hunter
Cc: Charan Pedumuru, devicetree, linux-tegra, linux-kernel,
Thierry Reding
From: Thierry Reding <treding@nvidia.com>
Use #address-cells = <1> and #size-cells = <1> because we don't need
64-bit register addressing for this hardware. While at it, also adjust
the ranges property to encompass the entire AHUB range as per the TRM.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 74 ++++++++++++++++----------------
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 2b5001d2c3ab..13a95008c186 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -231,14 +231,14 @@ tegra_ahub: ahub@2900800 {
assigned-clock-rates = <81600000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x02900000 0x0 0x02900000 0x20000>;
tegra_i2s1: i2s@2901000 {
compatible = "nvidia,tegra194-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901000 0x0 0x100>;
+ reg = <0x2901000 0x100>;
clocks = <&bpmp TEGRA194_CLK_I2S1>,
<&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -252,7 +252,7 @@ tegra_i2s1: i2s@2901000 {
tegra_i2s2: i2s@2901100 {
compatible = "nvidia,tegra194-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901100 0x0 0x100>;
+ reg = <0x2901100 0x100>;
clocks = <&bpmp TEGRA194_CLK_I2S2>,
<&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -266,7 +266,7 @@ tegra_i2s2: i2s@2901100 {
tegra_i2s3: i2s@2901200 {
compatible = "nvidia,tegra194-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901200 0x0 0x100>;
+ reg = <0x2901200 0x100>;
clocks = <&bpmp TEGRA194_CLK_I2S3>,
<&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -280,7 +280,7 @@ tegra_i2s3: i2s@2901200 {
tegra_i2s4: i2s@2901300 {
compatible = "nvidia,tegra194-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901300 0x0 0x100>;
+ reg = <0x2901300 0x100>;
clocks = <&bpmp TEGRA194_CLK_I2S4>,
<&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -294,7 +294,7 @@ tegra_i2s4: i2s@2901300 {
tegra_i2s5: i2s@2901400 {
compatible = "nvidia,tegra194-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901400 0x0 0x100>;
+ reg = <0x2901400 0x100>;
clocks = <&bpmp TEGRA194_CLK_I2S5>,
<&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -308,7 +308,7 @@ tegra_i2s5: i2s@2901400 {
tegra_i2s6: i2s@2901500 {
compatible = "nvidia,tegra194-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901500 0x0 0x100>;
+ reg = <0x2901500 0x100>;
clocks = <&bpmp TEGRA194_CLK_I2S6>,
<&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -322,7 +322,7 @@ tegra_i2s6: i2s@2901500 {
tegra_sfc1: sfc@2902000 {
compatible = "nvidia,tegra194-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x2902000 0x0 0x200>;
+ reg = <0x2902000 0x200>;
sound-name-prefix = "SFC1";
status = "disabled";
};
@@ -330,7 +330,7 @@ tegra_sfc1: sfc@2902000 {
tegra_sfc2: sfc@2902200 {
compatible = "nvidia,tegra194-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x2902200 0x0 0x200>;
+ reg = <0x2902200 0x200>;
sound-name-prefix = "SFC2";
status = "disabled";
};
@@ -338,7 +338,7 @@ tegra_sfc2: sfc@2902200 {
tegra_sfc3: sfc@2902400 {
compatible = "nvidia,tegra194-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x2902400 0x0 0x200>;
+ reg = <0x2902400 0x200>;
sound-name-prefix = "SFC3";
status = "disabled";
};
@@ -346,35 +346,35 @@ tegra_sfc3: sfc@2902400 {
tegra_sfc4: sfc@2902600 {
compatible = "nvidia,tegra194-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x2902600 0x0 0x200>;
+ reg = <0x2902600 0x200>;
sound-name-prefix = "SFC4";
status = "disabled";
};
tegra_amx1: amx@2903000 {
compatible = "nvidia,tegra194-amx";
- reg = <0x0 0x2903000 0x0 0x100>;
+ reg = <0x2903000 0x100>;
sound-name-prefix = "AMX1";
status = "disabled";
};
tegra_amx2: amx@2903100 {
compatible = "nvidia,tegra194-amx";
- reg = <0x0 0x2903100 0x0 0x100>;
+ reg = <0x2903100 0x100>;
sound-name-prefix = "AMX2";
status = "disabled";
};
tegra_amx3: amx@2903200 {
compatible = "nvidia,tegra194-amx";
- reg = <0x0 0x2903200 0x0 0x100>;
+ reg = <0x2903200 0x100>;
sound-name-prefix = "AMX3";
status = "disabled";
};
tegra_amx4: amx@2903300 {
compatible = "nvidia,tegra194-amx";
- reg = <0x0 0x2903300 0x0 0x100>;
+ reg = <0x2903300 0x100>;
sound-name-prefix = "AMX4";
status = "disabled";
};
@@ -382,7 +382,7 @@ tegra_amx4: amx@2903300 {
tegra_adx1: adx@2903800 {
compatible = "nvidia,tegra194-adx",
"nvidia,tegra210-adx";
- reg = <0x0 0x2903800 0x0 0x100>;
+ reg = <0x2903800 0x100>;
sound-name-prefix = "ADX1";
status = "disabled";
};
@@ -390,7 +390,7 @@ tegra_adx1: adx@2903800 {
tegra_adx2: adx@2903900 {
compatible = "nvidia,tegra194-adx",
"nvidia,tegra210-adx";
- reg = <0x0 0x2903900 0x0 0x100>;
+ reg = <0x2903900 0x100>;
sound-name-prefix = "ADX2";
status = "disabled";
};
@@ -398,7 +398,7 @@ tegra_adx2: adx@2903900 {
tegra_adx3: adx@2903a00 {
compatible = "nvidia,tegra194-adx",
"nvidia,tegra210-adx";
- reg = <0x0 0x2903a00 0x0 0x100>;
+ reg = <0x2903a00 0x100>;
sound-name-prefix = "ADX3";
status = "disabled";
};
@@ -406,7 +406,7 @@ tegra_adx3: adx@2903a00 {
tegra_adx4: adx@2903b00 {
compatible = "nvidia,tegra194-adx",
"nvidia,tegra210-adx";
- reg = <0x0 0x2903b00 0x0 0x100>;
+ reg = <0x2903b00 0x100>;
sound-name-prefix = "ADX4";
status = "disabled";
};
@@ -414,7 +414,7 @@ tegra_adx4: adx@2903b00 {
tegra_dmic1: dmic@2904000 {
compatible = "nvidia,tegra194-dmic",
"nvidia,tegra210-dmic";
- reg = <0x0 0x2904000 0x0 0x100>;
+ reg = <0x2904000 0x100>;
clocks = <&bpmp TEGRA194_CLK_DMIC1>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
@@ -427,7 +427,7 @@ tegra_dmic1: dmic@2904000 {
tegra_dmic2: dmic@2904100 {
compatible = "nvidia,tegra194-dmic",
"nvidia,tegra210-dmic";
- reg = <0x0 0x2904100 0x0 0x100>;
+ reg = <0x2904100 0x100>;
clocks = <&bpmp TEGRA194_CLK_DMIC2>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
@@ -440,7 +440,7 @@ tegra_dmic2: dmic@2904100 {
tegra_dmic3: dmic@2904200 {
compatible = "nvidia,tegra194-dmic",
"nvidia,tegra210-dmic";
- reg = <0x0 0x2904200 0x0 0x100>;
+ reg = <0x2904200 0x100>;
clocks = <&bpmp TEGRA194_CLK_DMIC3>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
@@ -453,7 +453,7 @@ tegra_dmic3: dmic@2904200 {
tegra_dmic4: dmic@2904300 {
compatible = "nvidia,tegra194-dmic",
"nvidia,tegra210-dmic";
- reg = <0x0 0x2904300 0x0 0x100>;
+ reg = <0x2904300 0x100>;
clocks = <&bpmp TEGRA194_CLK_DMIC4>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
@@ -466,7 +466,7 @@ tegra_dmic4: dmic@2904300 {
tegra_dspk1: dspk@2905000 {
compatible = "nvidia,tegra194-dspk",
"nvidia,tegra186-dspk";
- reg = <0x0 0x2905000 0x0 0x100>;
+ reg = <0x2905000 0x100>;
clocks = <&bpmp TEGRA194_CLK_DSPK1>;
clock-names = "dspk";
assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
@@ -479,7 +479,7 @@ tegra_dspk1: dspk@2905000 {
tegra_dspk2: dspk@2905100 {
compatible = "nvidia,tegra194-dspk",
"nvidia,tegra186-dspk";
- reg = <0x0 0x2905100 0x0 0x100>;
+ reg = <0x2905100 0x100>;
clocks = <&bpmp TEGRA194_CLK_DSPK2>;
clock-names = "dspk";
assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
@@ -492,31 +492,31 @@ tegra_dspk2: dspk@2905100 {
tegra_ope1: processing-engine@2908000 {
compatible = "nvidia,tegra194-ope",
"nvidia,tegra210-ope";
- reg = <0x0 0x2908000 0x0 0x100>;
+ reg = <0x2908000 0x100>;
sound-name-prefix = "OPE1";
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
ranges;
equalizer@2908100 {
compatible = "nvidia,tegra194-peq",
"nvidia,tegra210-peq";
- reg = <0x0 0x2908100 0x0 0x100>;
+ reg = <0x2908100 0x100>;
};
dynamic-range-compressor@2908200 {
compatible = "nvidia,tegra194-mbdrc",
"nvidia,tegra210-mbdrc";
- reg = <0x0 0x2908200 0x0 0x200>;
+ reg = <0x2908200 0x200>;
};
};
tegra_mvc1: mvc@290a000 {
compatible = "nvidia,tegra194-mvc",
"nvidia,tegra210-mvc";
- reg = <0x0 0x290a000 0x0 0x200>;
+ reg = <0x290a000 0x200>;
sound-name-prefix = "MVC1";
status = "disabled";
};
@@ -524,7 +524,7 @@ tegra_mvc1: mvc@290a000 {
tegra_mvc2: mvc@290a200 {
compatible = "nvidia,tegra194-mvc",
"nvidia,tegra210-mvc";
- reg = <0x0 0x290a200 0x0 0x200>;
+ reg = <0x290a200 0x200>;
sound-name-prefix = "MVC2";
status = "disabled";
};
@@ -532,7 +532,7 @@ tegra_mvc2: mvc@290a200 {
tegra_amixer: amixer@290bb00 {
compatible = "nvidia,tegra194-amixer",
"nvidia,tegra210-amixer";
- reg = <0x0 0x290bb00 0x0 0x800>;
+ reg = <0x290bb00 0x800>;
sound-name-prefix = "MIXER1";
status = "disabled";
};
@@ -540,7 +540,7 @@ tegra_amixer: amixer@290bb00 {
tegra_admaif: admaif@290f000 {
compatible = "nvidia,tegra194-admaif",
"nvidia,tegra186-admaif";
- reg = <0x0 0x0290f000 0x0 0x1000>;
+ reg = <0x0290f000 0x1000>;
dmas = <&adma 1>, <&adma 1>,
<&adma 2>, <&adma 2>,
<&adma 3>, <&adma 3>,
@@ -591,7 +591,7 @@ tegra_admaif: admaif@290f000 {
tegra_asrc: asrc@2910000 {
compatible = "nvidia,tegra194-asrc",
"nvidia,tegra186-asrc";
- reg = <0x0 0x2910000 0x0 0x2000>;
+ reg = <0x2910000 0x2000>;
sound-name-prefix = "ASRC1";
status = "disabled";
};
--
2.55.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 6/8] arm64: tegra: Clean up AHUB on Tegra234
2026-09-02 10:17 [PATCH 0/8] arm64: tegra: Clean up AHUB device tree nodes Thierry Reding
` (4 preceding siblings ...)
2026-09-02 10:17 ` [PATCH 5/8] arm64: tegra: Clean up AHUB on Tegra194 Thierry Reding
@ 2026-09-02 10:17 ` Thierry Reding
2026-09-02 10:17 ` [PATCH 7/8] arm64: tegra: Clean up AHUB on Tegra264 Thierry Reding
` (2 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Thierry Reding @ 2026-09-02 10:17 UTC (permalink / raw)
To: Thierry Reding, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jonathan Hunter
Cc: Charan Pedumuru, devicetree, linux-tegra, linux-kernel,
Thierry Reding
From: Thierry Reding <treding@nvidia.com>
Use #address-cells = <1> and #size-cells = <1> because we don't need
64-bit register addressing for this hardware. While at it, also adjust
the ranges property to encompass the entire AHUB range as per the TRM.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 74 ++++++++++++++++----------------
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 5e29316a4d75..5311245334de 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -245,14 +245,14 @@ tegra_ahub: ahub@2900800 {
assigned-clock-rates = <81600000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x02900000 0x0 0x02900000 0x20000>;
tegra_i2s1: i2s@2901000 {
compatible = "nvidia,tegra234-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901000 0x0 0x100>;
+ reg = <0x2901000 0x100>;
clocks = <&bpmp TEGRA234_CLK_I2S1>,
<&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -288,7 +288,7 @@ i2s1_dap: endpoint {
tegra_i2s2: i2s@2901100 {
compatible = "nvidia,tegra234-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901100 0x0 0x100>;
+ reg = <0x2901100 0x100>;
clocks = <&bpmp TEGRA234_CLK_I2S2>,
<&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -324,7 +324,7 @@ i2s2_dap: endpoint {
tegra_i2s3: i2s@2901200 {
compatible = "nvidia,tegra234-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901200 0x0 0x100>;
+ reg = <0x2901200 0x100>;
clocks = <&bpmp TEGRA234_CLK_I2S3>,
<&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -360,7 +360,7 @@ i2s3_dap: endpoint {
tegra_i2s4: i2s@2901300 {
compatible = "nvidia,tegra234-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901300 0x0 0x100>;
+ reg = <0x2901300 0x100>;
clocks = <&bpmp TEGRA234_CLK_I2S4>,
<&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -396,7 +396,7 @@ i2s4_dap: endpoint {
tegra_i2s5: i2s@2901400 {
compatible = "nvidia,tegra234-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901400 0x0 0x100>;
+ reg = <0x2901400 0x100>;
clocks = <&bpmp TEGRA234_CLK_I2S5>,
<&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -432,7 +432,7 @@ i2s5_dap: endpoint {
tegra_i2s6: i2s@2901500 {
compatible = "nvidia,tegra234-i2s",
"nvidia,tegra210-i2s";
- reg = <0x0 0x2901500 0x0 0x100>;
+ reg = <0x2901500 0x100>;
clocks = <&bpmp TEGRA234_CLK_I2S6>,
<&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
@@ -468,7 +468,7 @@ i2s6_dap: endpoint {
tegra_sfc1: sfc@2902000 {
compatible = "nvidia,tegra234-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x2902000 0x0 0x200>;
+ reg = <0x2902000 0x200>;
sound-name-prefix = "SFC1";
ports {
@@ -496,7 +496,7 @@ sfc1_cif_out: endpoint {
tegra_sfc2: sfc@2902200 {
compatible = "nvidia,tegra234-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x2902200 0x0 0x200>;
+ reg = <0x2902200 0x200>;
sound-name-prefix = "SFC2";
ports {
@@ -524,7 +524,7 @@ sfc2_cif_out: endpoint {
tegra_sfc3: sfc@2902400 {
compatible = "nvidia,tegra234-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x2902400 0x0 0x200>;
+ reg = <0x2902400 0x200>;
sound-name-prefix = "SFC3";
ports {
@@ -552,7 +552,7 @@ sfc3_cif_out: endpoint {
tegra_sfc4: sfc@2902600 {
compatible = "nvidia,tegra234-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x2902600 0x0 0x200>;
+ reg = <0x2902600 0x200>;
sound-name-prefix = "SFC4";
ports {
@@ -580,7 +580,7 @@ sfc4_cif_out: endpoint {
tegra_amx1: amx@2903000 {
compatible = "nvidia,tegra234-amx",
"nvidia,tegra194-amx";
- reg = <0x0 0x2903000 0x0 0x100>;
+ reg = <0x2903000 0x100>;
sound-name-prefix = "AMX1";
ports {
@@ -632,7 +632,7 @@ amx1_out: endpoint {
tegra_amx2: amx@2903100 {
compatible = "nvidia,tegra234-amx",
"nvidia,tegra194-amx";
- reg = <0x0 0x2903100 0x0 0x100>;
+ reg = <0x2903100 0x100>;
sound-name-prefix = "AMX2";
ports {
@@ -684,7 +684,7 @@ amx2_out: endpoint {
tegra_amx3: amx@2903200 {
compatible = "nvidia,tegra234-amx",
"nvidia,tegra194-amx";
- reg = <0x0 0x2903200 0x0 0x100>;
+ reg = <0x2903200 0x100>;
sound-name-prefix = "AMX3";
ports {
@@ -736,7 +736,7 @@ amx3_out: endpoint {
tegra_amx4: amx@2903300 {
compatible = "nvidia,tegra234-amx",
"nvidia,tegra194-amx";
- reg = <0x0 0x2903300 0x0 0x100>;
+ reg = <0x2903300 0x100>;
sound-name-prefix = "AMX4";
ports {
@@ -788,7 +788,7 @@ amx4_out: endpoint {
tegra_adx1: adx@2903800 {
compatible = "nvidia,tegra234-adx",
"nvidia,tegra210-adx";
- reg = <0x0 0x2903800 0x0 0x100>;
+ reg = <0x2903800 0x100>;
sound-name-prefix = "ADX1";
ports {
@@ -840,7 +840,7 @@ adx1_out4: endpoint {
tegra_adx2: adx@2903900 {
compatible = "nvidia,tegra234-adx",
"nvidia,tegra210-adx";
- reg = <0x0 0x2903900 0x0 0x100>;
+ reg = <0x2903900 0x100>;
sound-name-prefix = "ADX2";
ports {
@@ -892,7 +892,7 @@ adx2_out4: endpoint {
tegra_adx3: adx@2903a00 {
compatible = "nvidia,tegra234-adx",
"nvidia,tegra210-adx";
- reg = <0x0 0x2903a00 0x0 0x100>;
+ reg = <0x2903a00 0x100>;
sound-name-prefix = "ADX3";
ports {
@@ -944,7 +944,7 @@ adx3_out4: endpoint {
tegra_adx4: adx@2903b00 {
compatible = "nvidia,tegra234-adx",
"nvidia,tegra210-adx";
- reg = <0x0 0x2903b00 0x0 0x100>;
+ reg = <0x2903b00 0x100>;
sound-name-prefix = "ADX4";
ports {
@@ -997,7 +997,7 @@ adx4_out4: endpoint {
tegra_dmic1: dmic@2904000 {
compatible = "nvidia,tegra234-dmic",
"nvidia,tegra210-dmic";
- reg = <0x0 0x2904000 0x0 0x100>;
+ reg = <0x2904000 0x100>;
clocks = <&bpmp TEGRA234_CLK_DMIC1>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
@@ -1031,7 +1031,7 @@ dmic1_dap: endpoint {
tegra_dmic2: dmic@2904100 {
compatible = "nvidia,tegra234-dmic",
"nvidia,tegra210-dmic";
- reg = <0x0 0x2904100 0x0 0x100>;
+ reg = <0x2904100 0x100>;
clocks = <&bpmp TEGRA234_CLK_DMIC2>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
@@ -1065,7 +1065,7 @@ dmic2_dap: endpoint {
tegra_dmic3: dmic@2904200 {
compatible = "nvidia,tegra234-dmic",
"nvidia,tegra210-dmic";
- reg = <0x0 0x2904200 0x0 0x100>;
+ reg = <0x2904200 0x100>;
clocks = <&bpmp TEGRA234_CLK_DMIC3>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
@@ -1099,7 +1099,7 @@ dmic3_dap: endpoint {
tegra_dmic4: dmic@2904300 {
compatible = "nvidia,tegra234-dmic",
"nvidia,tegra210-dmic";
- reg = <0x0 0x2904300 0x0 0x100>;
+ reg = <0x2904300 0x100>;
clocks = <&bpmp TEGRA234_CLK_DMIC4>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
@@ -1133,7 +1133,7 @@ dmic4_dap: endpoint {
tegra_dspk1: dspk@2905000 {
compatible = "nvidia,tegra234-dspk",
"nvidia,tegra186-dspk";
- reg = <0x0 0x2905000 0x0 0x100>;
+ reg = <0x2905000 0x100>;
clocks = <&bpmp TEGRA234_CLK_DSPK1>;
clock-names = "dspk";
assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
@@ -1167,7 +1167,7 @@ dspk1_dap: endpoint {
tegra_dspk2: dspk@2905100 {
compatible = "nvidia,tegra234-dspk",
"nvidia,tegra186-dspk";
- reg = <0x0 0x2905100 0x0 0x100>;
+ reg = <0x2905100 0x100>;
clocks = <&bpmp TEGRA234_CLK_DSPK2>;
clock-names = "dspk";
assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
@@ -1201,23 +1201,23 @@ dspk2_dap: endpoint {
tegra_ope1: processing-engine@2908000 {
compatible = "nvidia,tegra234-ope",
"nvidia,tegra210-ope";
- reg = <0x0 0x2908000 0x0 0x100>;
+ reg = <0x2908000 0x100>;
sound-name-prefix = "OPE1";
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
ranges;
equalizer@2908100 {
compatible = "nvidia,tegra234-peq",
"nvidia,tegra210-peq";
- reg = <0x0 0x2908100 0x0 0x100>;
+ reg = <0x2908100 0x100>;
};
dynamic-range-compressor@2908200 {
compatible = "nvidia,tegra234-mbdrc",
"nvidia,tegra210-mbdrc";
- reg = <0x0 0x2908200 0x0 0x200>;
+ reg = <0x2908200 0x200>;
};
ports {
@@ -1247,7 +1247,7 @@ ope1_cif_out_ep: endpoint {
tegra_mvc1: mvc@290a000 {
compatible = "nvidia,tegra234-mvc",
"nvidia,tegra210-mvc";
- reg = <0x0 0x290a000 0x0 0x200>;
+ reg = <0x290a000 0x200>;
sound-name-prefix = "MVC1";
ports {
@@ -1275,7 +1275,7 @@ mvc1_cif_out: endpoint {
tegra_mvc2: mvc@290a200 {
compatible = "nvidia,tegra234-mvc",
"nvidia,tegra210-mvc";
- reg = <0x0 0x290a200 0x0 0x200>;
+ reg = <0x290a200 0x200>;
sound-name-prefix = "MVC2";
ports {
@@ -1303,7 +1303,7 @@ mvc2_cif_out: endpoint {
tegra_amixer: amixer@290bb00 {
compatible = "nvidia,tegra234-amixer",
"nvidia,tegra210-amixer";
- reg = <0x0 0x290bb00 0x0 0x800>;
+ reg = <0x290bb00 0x800>;
sound-name-prefix = "MIXER1";
ports {
@@ -1435,7 +1435,7 @@ mix_out5: endpoint {
tegra_admaif: admaif@290f000 {
compatible = "nvidia,tegra234-admaif",
"nvidia,tegra186-admaif";
- reg = <0x0 0x0290f000 0x0 0x1000>;
+ reg = <0x0290f000 0x1000>;
dmas = <&adma 1>, <&adma 1>,
<&adma 2>, <&adma 2>,
<&adma 3>, <&adma 3>,
@@ -1650,7 +1650,7 @@ admaif19: endpoint {
tegra_asrc: asrc@2910000 {
compatible = "nvidia,tegra234-asrc",
"nvidia,tegra186-asrc";
- reg = <0x0 0x2910000 0x0 0x2000>;
+ reg = <0x2910000 0x2000>;
sound-name-prefix = "ASRC1";
ports {
--
2.55.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 7/8] arm64: tegra: Clean up AHUB on Tegra264
2026-09-02 10:17 [PATCH 0/8] arm64: tegra: Clean up AHUB device tree nodes Thierry Reding
` (5 preceding siblings ...)
2026-09-02 10:17 ` [PATCH 6/8] arm64: tegra: Clean up AHUB on Tegra234 Thierry Reding
@ 2026-09-02 10:17 ` Thierry Reding
2026-09-02 10:31 ` sashiko-bot
2026-09-10 16:36 ` Jon Hunter
2026-09-02 10:17 ` [PATCH 8/8] arm64: tegra: Clean up some whitespace issues " Thierry Reding
2026-09-10 13:31 ` (subset) [PATCH 0/8] arm64: tegra: Clean up AHUB device tree nodes Thierry Reding
8 siblings, 2 replies; 14+ messages in thread
From: Thierry Reding @ 2026-09-02 10:17 UTC (permalink / raw)
To: Thierry Reding, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jonathan Hunter
Cc: Charan Pedumuru, devicetree, linux-tegra, linux-kernel,
Thierry Reding
From: Thierry Reding <treding@nvidia.com>
Use #address-cells = <1> and #size-cells = <1> because we don't need
64-bit register addressing for this hardware. While at it, also adjust
the ranges property to encompass the entire AHUB range as per the TRM.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 118 +++++++++++++++----------------
1 file changed, 59 insertions(+), 59 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 6b2e3a6ab810..4ed7dabafee5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -129,13 +129,13 @@ aconnect@9000000 {
power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x9000000 0x0 0x9000000 0x0 0x2000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x9000000 0x0 0x9000000 0x2000000>;
adma: dma-controller@9440000 {
compatible = "nvidia,tegra264-adma";
- reg = <0x0 0x9440000 0x0 0xb0000>;
+ reg = <0x9440000 0xb0000>;
interrupt-parent = <&agic_page0>;
interrupts = <GIC_SPI 0x90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 0x91 IRQ_TYPE_LEVEL_HIGH>,
@@ -209,22 +209,22 @@ adma: dma-controller@9440000 {
tegra_ahub: ahub@9630000 {
compatible = "nvidia,tegra264-ahub";
- reg = <0x0 0x9630000 0x0 0x10000>;
+ reg = <0x9630000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_AHUB>;
clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA264_CLK_AHUB>;
assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON_APE>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
/* ADMA is under AHUB range, its excluded in the defined range */
- ranges = <0x0 0x9280000 0x0 0x9280000 0x0 0x1c0000>,
- <0x0 0x9510000 0x0 0x9510000 0x0 0x370000>;
+ ranges = <0x9280000 0x0 0x9280000 0x1c0000>,
+ <0x9510000 0x0 0x9510000 0x370000>;
tegra_i2s1: i2s@9280000 {
compatible = "nvidia,tegra264-i2s";
- reg = <0x0 0x9280000 0x0 0x10000>;
+ reg = <0x9280000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S1>,
<&bpmp TEGRA264_CLK_I2S1_SCLK_IN>;
clock-names = "i2s", "sync_input";
@@ -259,7 +259,7 @@ i2s1_dap: endpoint {
tegra_i2s2: i2s@9290000 {
compatible = "nvidia,tegra264-i2s";
- reg = <0x0 0x9290000 0x0 0x10000>;
+ reg = <0x9290000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S2>,
<&bpmp TEGRA264_CLK_I2S2_SCLK_IN>;
clock-names = "i2s", "sync_input";
@@ -294,7 +294,7 @@ i2s2_dap: endpoint {
tegra_i2s3: i2s@92a0000 {
compatible = "nvidia,tegra264-i2s";
- reg = <0x0 0x92a0000 0x0 0x10000>;
+ reg = <0x92a0000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S3>,
<&bpmp TEGRA264_CLK_I2S3_SCLK_IN>;
clock-names = "i2s", "sync_input";
@@ -329,7 +329,7 @@ i2s3_dap: endpoint {
tegra_i2s4: i2s@92b0000 {
compatible = "nvidia,tegra264-i2s";
- reg = <0x0 0x92b0000 0x0 0x10000>;
+ reg = <0x92b0000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S4>,
<&bpmp TEGRA264_CLK_I2S4_SCLK_IN>;
clock-names = "i2s", "sync_input";
@@ -364,7 +364,7 @@ i2s4_dap: endpoint {
tegra_i2s5: i2s@92c0000 {
compatible = "nvidia,tegra264-i2s";
- reg = <0x0 0x92c0000 0x0 0x10000>;
+ reg = <0x92c0000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S5>,
<&bpmp TEGRA264_CLK_I2S5_SCLK_IN>;
clock-names = "i2s", "sync_input";
@@ -399,7 +399,7 @@ i2s5_dap: endpoint {
tegra_i2s6: i2s@92d0000 {
compatible = "nvidia,tegra264-i2s";
- reg = <0x0 0x92d0000 0x0 0x10000>;
+ reg = <0x92d0000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S6>,
<&bpmp TEGRA264_CLK_I2S6_SCLK_IN>;
clock-names = "i2s", "sync_input";
@@ -434,7 +434,7 @@ i2s6_dap: endpoint {
tegra_i2s7: i2s@92e0000 {
compatible = "nvidia,tegra264-i2s";
- reg = <0x0 0x92e0000 0x0 0x10000>;
+ reg = <0x92e0000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S7>,
<&bpmp TEGRA264_CLK_I2S7_SCLK_IN>;
clock-names = "i2s", "sync_input";
@@ -469,7 +469,7 @@ i2s7_dap: endpoint {
tegra_i2s8: i2s@92f0000 {
compatible = "nvidia,tegra264-i2s";
- reg = <0x0 0x92f0000 0x0 0x10000>;
+ reg = <0x92f0000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S8>,
<&bpmp TEGRA264_CLK_I2S8_SCLK_IN>;
clock-names = "i2s", "sync_input";
@@ -505,7 +505,7 @@ i2s8_dap: endpoint {
tegra_dmic1: dmic@9300000 {
compatible = "nvidia,tegra264-dmic",
"nvidia,tegra210-dmic";
- reg = <0x0 0x9300000 0x0 0x10000>;
+ reg = <0x9300000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_DMIC1>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>;
@@ -539,7 +539,7 @@ dmic1_dap: endpoint {
tegra_dmic2: dmic@9310000 {
compatible = "nvidia,tegra264-dmic",
"nvidia,tegra210-dmic";
- reg = <0x0 0x9310000 0x0 0x10000>;
+ reg = <0x9310000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_DMIC1>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>;
@@ -573,7 +573,7 @@ dmic2_dap: endpoint {
tegra_dspk1: dspk@9380000 {
compatible = "nvidia,tegra264-dspk",
"nvidia,tegra186-dspk";
- reg = <0x0 0x9380000 0x0 0x10000>;
+ reg = <0x9380000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_DSPK1>;
clock-names = "dspk";
assigned-clocks = <&bpmp TEGRA264_CLK_DSPK1>;
@@ -606,7 +606,7 @@ dspk1_dap: endpoint {
tegra_amx1: amx@9510000 {
compatible = "nvidia,tegra264-amx";
- reg = <0x0 0x9510000 0x0 0x10000>;
+ reg = <0x9510000 0x10000>;
sound-name-prefix = "AMX1";
ports {
@@ -657,7 +657,7 @@ amx1_out: endpoint {
tegra_amx2: amx@9520000 {
compatible = "nvidia,tegra264-amx";
- reg = <0x0 0x9520000 0x0 0x10000>;
+ reg = <0x9520000 0x10000>;
sound-name-prefix = "AMX2";
ports {
@@ -708,7 +708,7 @@ amx2_out: endpoint {
tegra_amx3: amx@9530000 {
compatible = "nvidia,tegra264-amx";
- reg = <0x0 0x9530000 0x0 0x10000>;
+ reg = <0x9530000 0x10000>;
sound-name-prefix = "AMX3";
ports {
@@ -759,7 +759,7 @@ amx3_out: endpoint {
tegra_amx4: amx@9540000 {
compatible = "nvidia,tegra264-amx";
- reg = <0x0 0x9540000 0x0 0x10000>;
+ reg = <0x9540000 0x10000>;
sound-name-prefix = "AMX4";
ports {
@@ -810,7 +810,7 @@ amx4_out: endpoint {
tegra_amx5: amx@9550000 {
compatible = "nvidia,tegra264-amx";
- reg = <0x0 0x9550000 0x0 0x10000>;
+ reg = <0x9550000 0x10000>;
sound-name-prefix = "AMX5";
ports {
@@ -861,7 +861,7 @@ amx5_out: endpoint {
tegra_amx6: amx@9560000 {
compatible = "nvidia,tegra264-amx";
- reg = <0x0 0x9560000 0x0 0x10000>;
+ reg = <0x9560000 0x10000>;
sound-name-prefix = "AMX6";
ports {
@@ -912,7 +912,7 @@ amx6_out: endpoint {
tegra_adx1: adx@9590000 {
compatible = "nvidia,tegra264-adx";
- reg = <0x0 0x9590000 0x0 0x10000>;
+ reg = <0x9590000 0x10000>;
sound-name-prefix = "ADX1";
ports {
@@ -963,7 +963,7 @@ adx1_out4: endpoint {
tegra_adx2: adx@95a0000 {
compatible = "nvidia,tegra264-adx";
- reg = <0x0 0x95a0000 0x0 0x10000>;
+ reg = <0x95a0000 0x10000>;
sound-name-prefix = "ADX2";
ports {
@@ -1014,7 +1014,7 @@ adx2_out4: endpoint {
tegra_adx3: adx@95b0000 {
compatible = "nvidia,tegra264-adx";
- reg = <0x0 0x95b0000 0x0 0x10000>;
+ reg = <0x95b0000 0x10000>;
sound-name-prefix = "ADX3";
ports {
@@ -1065,7 +1065,7 @@ adx3_out4: endpoint {
tegra_adx4: adx@95c0000 {
compatible = "nvidia,tegra264-adx";
- reg = <0x0 0x95c0000 0x0 0x10000>;
+ reg = <0x95c0000 0x10000>;
sound-name-prefix = "ADX4";
ports {
@@ -1116,7 +1116,7 @@ adx4_out4: endpoint {
tegra_adx5: adx@95d0000 {
compatible = "nvidia,tegra264-adx";
- reg = <0x0 0x95d0000 0x0 0x10000>;
+ reg = <0x95d0000 0x10000>;
sound-name-prefix = "ADX5";
ports {
@@ -1167,7 +1167,7 @@ adx5_out4: endpoint {
tegra_adx6: adx@95e0000 {
compatible = "nvidia,tegra264-adx";
- reg = <0x0 0x95e0000 0x0 0x10000>;
+ reg = <0x95e0000 0x10000>;
sound-name-prefix = "ADX6";
ports {
@@ -1218,7 +1218,7 @@ adx6_out4: endpoint {
tegra_admaif: admaif@9610000 {
compatible = "nvidia,tegra264-admaif";
- reg = <0x0 0x9610000 0x0 0x10000>;
+ reg = <0x9610000 0x10000>;
dmas = <&adma 1>, <&adma 1>,
<&adma 2>, <&adma 2>,
<&adma 3>, <&adma 3>,
@@ -1556,7 +1556,7 @@ admaif31: endpoint {
tegra_sfc1: sfc@9700000 {
compatible = "nvidia,tegra264-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x9700000 0x0 0x10000>;
+ reg = <0x9700000 0x10000>;
sound-name-prefix = "SFC1";
ports {
@@ -1584,7 +1584,7 @@ sfc1_cif_out: endpoint {
tegra_sfc2: sfc@9710000 {
compatible = "nvidia,tegra264-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x9710000 0x0 0x10000>;
+ reg = <0x9710000 x0 0x10000>;
sound-name-prefix = "SFC2";
ports {
@@ -1612,7 +1612,7 @@ sfc2_cif_out: endpoint {
tegra_sfc3: sfc@9720000 {
compatible = "nvidia,tegra264-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x9720000 0x0 0x10000>;
+ reg = <0x9720000 0x10000>;
sound-name-prefix = "SFC3";
ports {
@@ -1640,7 +1640,7 @@ sfc3_cif_out: endpoint {
tegra_sfc4: sfc@9730000 {
compatible = "nvidia,tegra264-sfc",
"nvidia,tegra210-sfc";
- reg = <0x0 0x9730000 0x0 0x10000>;
+ reg = <0x9730000 0x10000>;
sound-name-prefix = "SFC4";
ports {
@@ -1668,22 +1668,22 @@ sfc4_cif_out: endpoint {
tegra_ope1: processing-engine@9780000 {
compatible = "nvidia,tegra264-ope",
"nvidia,tegra210-ope";
- reg = <0x0 0x9780000 0x0 0x10000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x9780000 0x0 0x9780000 0x0 0x30000>;
+ reg = <0x9780000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x9780000 0x9780000 0x30000>;
sound-name-prefix = "OPE1";
equalizer@9790000 {
compatible = "nvidia,tegra264-peq",
"nvidia,tegra210-peq";
- reg = <0x0 0x9790000 0x0 0x10000>;
+ reg = <0x9790000 0x10000>;
};
dynamic-range-compressor@97a0000 {
compatible = "nvidia,tegra264-mbdrc",
"nvidia,tegra210-mbdrc";
- reg = <0x0 0x97a0000 0x0 0x10000>;
+ reg = <0x97a0000 0x10000>;
};
ports {
@@ -1713,7 +1713,7 @@ ope1_cif_out_ep: endpoint {
tegra_mvc1: mvc@9800000 {
compatible = "nvidia,tegra264-mvc",
"nvidia,tegra210-mvc";
- reg = <0x0 0x9800000 0x0 0x10000>;
+ reg = <0x9800000 0x10000>;
sound-name-prefix = "MVC1";
ports {
@@ -1741,7 +1741,7 @@ mvc1_cif_out: endpoint {
tegra_mvc2: mvc@9810000 {
compatible = "nvidia,tegra264-mvc",
"nvidia,tegra210-mvc";
- reg = <0x0 0x9810000 0x0 0x10000>;
+ reg = <0x9810000 0x10000>;
sound-name-prefix = "MVC2";
ports {
@@ -1769,7 +1769,7 @@ mvc2_cif_out: endpoint {
tegra_amixer: amixer@9820000 {
compatible = "nvidia,tegra264-amixer",
"nvidia,tegra210-amixer";
- reg = <0x0 0x9820000 0x0 0x10000>;
+ reg = <0x9820000 0x10000>;
sound-name-prefix = "MIXER1";
ports {
@@ -1900,7 +1900,7 @@ mix_out5: endpoint {
tegra_asrc: asrc@9850000 {
compatible = "nvidia,tegra264-asrc";
- reg = <0x0 0x9850000 0x0 0x10000>;
+ reg = <0x9850000 0x10000>;
sound-name-prefix = "ASRC1";
ports {
@@ -3197,8 +3197,8 @@ agic_page0: interrupt-controller@9960000 {
"nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x0 0x9961000 0x0 0x1000>,
- <0x0 0x9962000 0x0 0x1000>;
+ reg = <0x9961000 0x1000>,
+ <0x9962000 0x1000>;
interrupts = <GIC_SPI 0x230
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA264_CLK_ADSP>;
@@ -3211,8 +3211,8 @@ agic_page1: interrupt-controller@9970000 {
"nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x0 0x9971000 0x0 0x1000>,
- <0x0 0x9972000 0x0 0x1000>;
+ reg = <0x9971000 0x1000>,
+ <0x9972000 0x1000>;
interrupts = <GIC_SPI 0x231
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA264_CLK_ADSP>;
@@ -3225,8 +3225,8 @@ agic_page2: interrupt-controller@9980000 {
"nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x0 0x9981000 0x0 0x1000>,
- <0x0 0x9982000 0x0 0x1000>;
+ reg = <0x9981000 0x1000>,
+ <0x9982000 0x1000>;
interrupts = <GIC_SPI 0x232
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA264_CLK_ADSP>;
@@ -3239,8 +3239,8 @@ agic_page3: interrupt-controller@9990000 {
"nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x0 0x9991000 0x0 0x1000>,
- <0x0 0x9992000 0x0 0x1000>;
+ reg = <0x9991000 0x1000>,
+ <0x9992000 0x1000>;
interrupts = <GIC_SPI 0x233
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA264_CLK_ADSP>;
@@ -3253,8 +3253,8 @@ agic_page4: interrupt-controller@99a0000 {
"nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x0 0x99a1000 0x0 0x1000>,
- <0x0 0x99a2000 0x0 0x1000>;
+ reg = <0x99a1000 0x1000>,
+ <0x99a2000 0x1000>;
interrupts = <GIC_SPI 0x234
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA264_CLK_ADSP>;
@@ -3267,8 +3267,8 @@ agic_page5: interrupt-controller@99b0000 {
"nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x0 0x99b1000 0x0 0x1000>,
- <0x0 0x99b2000 0x0 0x1000>;
+ reg = <0x99b1000 0x1000>,
+ <0x99b2000 0x1000>;
interrupts = <GIC_SPI 0x235
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA264_CLK_ADSP>;
--
2.55.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 7/8] arm64: tegra: Clean up AHUB on Tegra264
2026-09-02 10:17 ` [PATCH 7/8] arm64: tegra: Clean up AHUB on Tegra264 Thierry Reding
@ 2026-09-02 10:31 ` sashiko-bot
2026-09-10 16:36 ` Jon Hunter
1 sibling, 0 replies; 14+ messages in thread
From: sashiko-bot @ 2026-09-02 10:31 UTC (permalink / raw)
To: Thierry Reding; +Cc: conor+dt, devicetree, robh
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The `ranges` property in `tegra_ahub` has an incorrect number of cells, causing device tree translation failure.
- [High] Syntax error and malformed cell count in the `reg` property of `tegra_sfc2`.
--
commit e1dacd52fef2161b800fe722394a96baeac1b62f
Author: Thierry Reding <treding@nvidia.com>
arm64: tegra: Clean up AHUB on Tegra264
This commit updates the device tree properties for the AHUB and related
components on Tegra264, changing #address-cells and #size-cells to 1.
It also adjusts the ranges property and simplifies the register offsets
throughout the audio subsystem.
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index 6b2e3a6ab810f..4ed7dabafee5d 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
[ ... ]
> @@ -209,22 +209,22 @@ adma: dma-controller@9440000 {
>
> tegra_ahub: ahub@9630000 {
> compatible = "nvidia,tegra264-ahub";
> - reg = <0x0 0x9630000 0x0 0x10000>;
> + reg = <0x9630000 0x10000>;
> clocks = <&bpmp TEGRA264_CLK_AHUB>;
> clock-names = "ahub";
> assigned-clocks = <&bpmp TEGRA264_CLK_AHUB>;
> assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON_APE>;
> status = "disabled";
>
> - #address-cells = <2>;
> - #size-cells = <2>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> /* ADMA is under AHUB range, its excluded in the defined range */
> - ranges = <0x0 0x9280000 0x0 0x9280000 0x0 0x1c0000>,
> - <0x0 0x9510000 0x0 0x9510000 0x0 0x370000>;
> + ranges = <0x9280000 0x0 0x9280000 0x1c0000>,
> + <0x9510000 0x0 0x9510000 0x370000>;
[Severity: High]
Since tegra_ahub and its parent aconnect both define #address-cells = <1>
and #size-cells = <1>, shouldn't the ranges property have exactly 3 cells
per entry (child-address, parent-address, length)?
The updated values still contain 4 cells per entry, which looks like it
failed to remove the stale 32-bit 0x0 from the previous 64-bit parent
address layout. Will this malformed cell count cause dtc to fail validation
and prevent MMIO address mapping for audio peripherals on the AHUB?
>
> tegra_i2s1: i2s@9280000 {
[ ... ]
> @@ -1584,7 +1584,7 @@ sfc1_cif_out: endpoint {
> tegra_sfc2: sfc@9710000 {
> compatible = "nvidia,tegra264-sfc",
> "nvidia,tegra210-sfc";
> - reg = <0x0 0x9710000 0x0 0x10000>;
> + reg = <0x9710000 x0 0x10000>;
[Severity: High]
Does this introduce a syntax error in the device tree? The x0 token appears
to be a typo, which would cause dtc compilation to abort.
Additionally, even if parsed as zero, wouldn't this result in 3 cells
instead of the 2 cells expected by the #address-cells = <1> and
#size-cells = <1> configuration?
> sound-name-prefix = "SFC2";
>
> ports {
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260902-tegra-ahub-dt-cleanup-v1-0-028f3c5e72f6@nvidia.com?part=7
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 7/8] arm64: tegra: Clean up AHUB on Tegra264
2026-09-02 10:17 ` [PATCH 7/8] arm64: tegra: Clean up AHUB on Tegra264 Thierry Reding
2026-09-02 10:31 ` sashiko-bot
@ 2026-09-10 16:36 ` Jon Hunter
2026-09-11 10:32 ` Thierry Reding
1 sibling, 1 reply; 14+ messages in thread
From: Jon Hunter @ 2026-09-10 16:36 UTC (permalink / raw)
To: Thierry Reding, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Charan Pedumuru, devicetree, linux-tegra, linux-kernel,
Thierry Reding
On 02/09/2026 11:17, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Use #address-cells = <1> and #size-cells = <1> because we don't need
> 64-bit register addressing for this hardware. While at it, also adjust
> the ranges property to encompass the entire AHUB range as per the TRM.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra264.dtsi | 118 +++++++++++++++----------------
> 1 file changed, 59 insertions(+), 59 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index 6b2e3a6ab810..4ed7dabafee5 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> @@ -129,13 +129,13 @@ aconnect@9000000 {
> power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>;
> status = "disabled";
...
> ports {
> @@ -1584,7 +1584,7 @@ sfc1_cif_out: endpoint {
> tegra_sfc2: sfc@9710000 {
> compatible = "nvidia,tegra264-sfc",
> "nvidia,tegra210-sfc";
> - reg = <0x0 0x9710000 0x0 0x10000>;
> + reg = <0x9710000 x0 0x10000>;
Looks like a typo crept in here 'x0' which is what kernelci is
complaining about [0].
Jon
[0] https://lore.kernel.org/linux-tegra/178905234343.3919.16985173968804561026@kernelci.org/T/#u
--
nvpublic
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 7/8] arm64: tegra: Clean up AHUB on Tegra264
2026-09-10 16:36 ` Jon Hunter
@ 2026-09-11 10:32 ` Thierry Reding
0 siblings, 0 replies; 14+ messages in thread
From: Thierry Reding @ 2026-09-11 10:32 UTC (permalink / raw)
To: Jon Hunter
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Charan Pedumuru,
devicetree, linux-tegra, linux-kernel, Thierry Reding
[-- Attachment #1: Type: text/plain, Size: 1524 bytes --]
On Thu, Sep 10, 2026 at 05:36:41PM +0100, Jon Hunter wrote:
>
>
> On 02/09/2026 11:17, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > Use #address-cells = <1> and #size-cells = <1> because we don't need
> > 64-bit register addressing for this hardware. While at it, also adjust
> > the ranges property to encompass the entire AHUB range as per the TRM.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > arch/arm64/boot/dts/nvidia/tegra264.dtsi | 118 +++++++++++++++----------------
> > 1 file changed, 59 insertions(+), 59 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> > index 6b2e3a6ab810..4ed7dabafee5 100644
> > --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> > +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> > @@ -129,13 +129,13 @@ aconnect@9000000 {
> > power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>;
> > status = "disabled";
>
> ...
>
> > ports {
> > @@ -1584,7 +1584,7 @@ sfc1_cif_out: endpoint {
> > tegra_sfc2: sfc@9710000 {
> > compatible = "nvidia,tegra264-sfc",
> > "nvidia,tegra210-sfc";
> > - reg = <0x0 0x9710000 0x0 0x10000>;
> > + reg = <0x9710000 x0 0x10000>;
>
>
> Looks like a typo crept in here 'x0' which is what kernelci is
> complaining about [0].
Ugh... I had fixed this up in a local branch but then applied the
patches from the list instead... fixed now.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 8/8] arm64: tegra: Clean up some whitespace issues on Tegra264
2026-09-02 10:17 [PATCH 0/8] arm64: tegra: Clean up AHUB device tree nodes Thierry Reding
` (6 preceding siblings ...)
2026-09-02 10:17 ` [PATCH 7/8] arm64: tegra: Clean up AHUB on Tegra264 Thierry Reding
@ 2026-09-02 10:17 ` Thierry Reding
2026-09-10 13:31 ` (subset) [PATCH 0/8] arm64: tegra: Clean up AHUB device tree nodes Thierry Reding
8 siblings, 0 replies; 14+ messages in thread
From: Thierry Reding @ 2026-09-02 10:17 UTC (permalink / raw)
To: Thierry Reding, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jonathan Hunter
Cc: Charan Pedumuru, devicetree, linux-tegra, linux-kernel,
Thierry Reding
From: Thierry Reding <treding@nvidia.com>
Properly align property names and values, and remove gratuitous
wrapping.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 376 +++++++++++++++----------------
1 file changed, 177 insertions(+), 199 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 4ed7dabafee5..f011cd6e56e0 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -122,9 +122,9 @@ hsp_top: hsp@8800000 {
aconnect@9000000 {
compatible = "nvidia,tegra264-aconnect",
- "nvidia,tegra210-aconnect";
+ "nvidia,tegra210-aconnect";
clocks = <&bpmp TEGRA264_CLK_APE>,
- <&bpmp TEGRA264_CLK_ADSP>;
+ <&bpmp TEGRA264_CLK_ADSP>;
clock-names = "ape", "apb2ape";
power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>;
status = "disabled";
@@ -138,69 +138,69 @@ adma: dma-controller@9440000 {
reg = <0x9440000 0xb0000>;
interrupt-parent = <&agic_page0>;
interrupts = <GIC_SPI 0x90 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x91 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x92 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x93 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x94 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x95 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x96 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x97 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x98 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x99 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x9a IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x9b IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x9c IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x9d IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x9e IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0x9f IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xa0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xa1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xa2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xa3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xa4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xa5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xa6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xa7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xa8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xa9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xaa IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xab IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xac IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xad IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xae IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xaf IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xb0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xb1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xb2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xb3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xb4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xb5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xb6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xb7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xb8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xb9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xba IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xbb IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xbc IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xbd IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xbe IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xbf IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xc0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xc1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xc2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xc3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xc4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xc5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xc6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xc7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xc8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xc9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xca IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xcb IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xcc IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xcd IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xce IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 0xcf IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 0x91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x9a IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x9b IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x9c IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x9d IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x9e IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0x9f IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xa0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xa1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xa2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xa3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xa4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xa5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xa6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xa7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xa8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xa9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xaa IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xab IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xac IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xad IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xae IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xaf IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xb0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xb1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xb2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xb3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xb4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xb5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xb6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xb7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xb8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xb9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xba IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xbb IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xbc IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xbd IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xbe IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xbf IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xc0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xc1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xc2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xc3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xc4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xc5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xc6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xc7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xc8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xc9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xca IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xcb IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xcc IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xcd IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xce IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0xcf IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&bpmp TEGRA264_CLK_AHUB>;
clock-names = "d_audio";
@@ -226,7 +226,7 @@ tegra_i2s1: i2s@9280000 {
compatible = "nvidia,tegra264-i2s";
reg = <0x9280000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S1>,
- <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>;
+ <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA264_CLK_I2S1>;
assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
@@ -296,7 +296,7 @@ tegra_i2s3: i2s@92a0000 {
compatible = "nvidia,tegra264-i2s";
reg = <0x92a0000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S3>,
- <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>;
+ <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA264_CLK_I2S3>;
assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
@@ -331,7 +331,7 @@ tegra_i2s4: i2s@92b0000 {
compatible = "nvidia,tegra264-i2s";
reg = <0x92b0000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S4>,
- <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>;
+ <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA264_CLK_I2S4>;
assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
@@ -366,7 +366,7 @@ tegra_i2s5: i2s@92c0000 {
compatible = "nvidia,tegra264-i2s";
reg = <0x92c0000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S5>,
- <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>;
+ <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA264_CLK_I2S5>;
assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
@@ -401,7 +401,7 @@ tegra_i2s6: i2s@92d0000 {
compatible = "nvidia,tegra264-i2s";
reg = <0x92d0000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S6>,
- <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>;
+ <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA264_CLK_I2S6>;
assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
@@ -436,7 +436,7 @@ tegra_i2s7: i2s@92e0000 {
compatible = "nvidia,tegra264-i2s";
reg = <0x92e0000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S7>,
- <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>;
+ <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA264_CLK_I2S7>;
assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
@@ -471,7 +471,7 @@ tegra_i2s8: i2s@92f0000 {
compatible = "nvidia,tegra264-i2s";
reg = <0x92f0000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_I2S8>,
- <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>;
+ <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA264_CLK_I2S8>;
assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>;
@@ -504,7 +504,7 @@ i2s8_dap: endpoint {
tegra_dmic1: dmic@9300000 {
compatible = "nvidia,tegra264-dmic",
- "nvidia,tegra210-dmic";
+ "nvidia,tegra210-dmic";
reg = <0x9300000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_DMIC1>;
clock-names = "dmic";
@@ -538,7 +538,7 @@ dmic1_dap: endpoint {
tegra_dmic2: dmic@9310000 {
compatible = "nvidia,tegra264-dmic",
- "nvidia,tegra210-dmic";
+ "nvidia,tegra210-dmic";
reg = <0x9310000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_DMIC1>;
clock-names = "dmic";
@@ -572,7 +572,7 @@ dmic2_dap: endpoint {
tegra_dspk1: dspk@9380000 {
compatible = "nvidia,tegra264-dspk",
- "nvidia,tegra186-dspk";
+ "nvidia,tegra186-dspk";
reg = <0x9380000 0x10000>;
clocks = <&bpmp TEGRA264_CLK_DSPK1>;
clock-names = "dspk";
@@ -1220,74 +1220,73 @@ tegra_admaif: admaif@9610000 {
compatible = "nvidia,tegra264-admaif";
reg = <0x9610000 0x10000>;
dmas = <&adma 1>, <&adma 1>,
- <&adma 2>, <&adma 2>,
- <&adma 3>, <&adma 3>,
- <&adma 4>, <&adma 4>,
- <&adma 5>, <&adma 5>,
- <&adma 6>, <&adma 6>,
- <&adma 7>, <&adma 7>,
- <&adma 8>, <&adma 8>,
- <&adma 9>, <&adma 9>,
- <&adma 10>, <&adma 10>,
- <&adma 11>, <&adma 11>,
- <&adma 12>, <&adma 12>,
- <&adma 13>, <&adma 13>,
- <&adma 14>, <&adma 14>,
- <&adma 15>, <&adma 15>,
- <&adma 16>, <&adma 16>,
- <&adma 17>, <&adma 17>,
- <&adma 18>, <&adma 18>,
- <&adma 19>, <&adma 19>,
- <&adma 20>, <&adma 20>,
- <&adma 21>, <&adma 21>,
- <&adma 22>, <&adma 22>,
- <&adma 23>, <&adma 23>,
- <&adma 24>, <&adma 24>,
- <&adma 25>, <&adma 25>,
- <&adma 26>, <&adma 26>,
- <&adma 27>, <&adma 27>,
- <&adma 28>, <&adma 28>,
- <&adma 29>, <&adma 29>,
- <&adma 30>, <&adma 30>,
- <&adma 31>, <&adma 31>,
- <&adma 32>, <&adma 32>;
+ <&adma 2>, <&adma 2>,
+ <&adma 3>, <&adma 3>,
+ <&adma 4>, <&adma 4>,
+ <&adma 5>, <&adma 5>,
+ <&adma 6>, <&adma 6>,
+ <&adma 7>, <&adma 7>,
+ <&adma 8>, <&adma 8>,
+ <&adma 9>, <&adma 9>,
+ <&adma 10>, <&adma 10>,
+ <&adma 11>, <&adma 11>,
+ <&adma 12>, <&adma 12>,
+ <&adma 13>, <&adma 13>,
+ <&adma 14>, <&adma 14>,
+ <&adma 15>, <&adma 15>,
+ <&adma 16>, <&adma 16>,
+ <&adma 17>, <&adma 17>,
+ <&adma 18>, <&adma 18>,
+ <&adma 19>, <&adma 19>,
+ <&adma 20>, <&adma 20>,
+ <&adma 21>, <&adma 21>,
+ <&adma 22>, <&adma 22>,
+ <&adma 23>, <&adma 23>,
+ <&adma 24>, <&adma 24>,
+ <&adma 25>, <&adma 25>,
+ <&adma 26>, <&adma 26>,
+ <&adma 27>, <&adma 27>,
+ <&adma 28>, <&adma 28>,
+ <&adma 29>, <&adma 29>,
+ <&adma 30>, <&adma 30>,
+ <&adma 31>, <&adma 31>,
+ <&adma 32>, <&adma 32>;
dma-names = "rx1", "tx1",
- "rx2", "tx2",
- "rx3", "tx3",
- "rx4", "tx4",
- "rx5", "tx5",
- "rx6", "tx6",
- "rx7", "tx7",
- "rx8", "tx8",
- "rx9", "tx9",
- "rx10", "tx10",
- "rx11", "tx11",
- "rx12", "tx12",
- "rx13", "tx13",
- "rx14", "tx14",
- "rx15", "tx15",
- "rx16", "tx16",
- "rx17", "tx17",
- "rx18", "tx18",
- "rx19", "tx19",
- "rx20", "tx20",
- "rx21", "tx21",
- "rx22", "tx22",
- "rx23", "tx23",
- "rx24", "tx24",
- "rx25", "tx25",
- "rx26", "tx26",
- "rx27", "tx27",
- "rx28", "tx28",
- "rx29", "tx29",
- "rx30", "tx30",
- "rx31", "tx31",
- "rx32", "tx32";
+ "rx2", "tx2",
+ "rx3", "tx3",
+ "rx4", "tx4",
+ "rx5", "tx5",
+ "rx6", "tx6",
+ "rx7", "tx7",
+ "rx8", "tx8",
+ "rx9", "tx9",
+ "rx10", "tx10",
+ "rx11", "tx11",
+ "rx12", "tx12",
+ "rx13", "tx13",
+ "rx14", "tx14",
+ "rx15", "tx15",
+ "rx16", "tx16",
+ "rx17", "tx17",
+ "rx18", "tx18",
+ "rx19", "tx19",
+ "rx20", "tx20",
+ "rx21", "tx21",
+ "rx22", "tx22",
+ "rx23", "tx23",
+ "rx24", "tx24",
+ "rx25", "tx25",
+ "rx26", "tx26",
+ "rx27", "tx27",
+ "rx28", "tx28",
+ "rx29", "tx29",
+ "rx30", "tx30",
+ "rx31", "tx31",
+ "rx32", "tx32";
- interconnects =
- <&mc TEGRA264_MEMORY_CLIENT_APEDMAR &emc>,
- <&mc TEGRA264_MEMORY_CLIENT_APEDMAW &emc>;
- interconnect-names = "dma-mem", "write";
+ interconnects = <&mc TEGRA264_MEMORY_CLIENT_APEDMAR &emc>,
+ <&mc TEGRA264_MEMORY_CLIENT_APEDMAW &emc>;
+ interconnect-names = "dma-mem", "write";
iommus = <&smmu1 TEGRA264_SID_APE>;
@@ -1555,7 +1554,7 @@ admaif31: endpoint {
tegra_sfc1: sfc@9700000 {
compatible = "nvidia,tegra264-sfc",
- "nvidia,tegra210-sfc";
+ "nvidia,tegra210-sfc";
reg = <0x9700000 0x10000>;
sound-name-prefix = "SFC1";
@@ -1583,7 +1582,7 @@ sfc1_cif_out: endpoint {
tegra_sfc2: sfc@9710000 {
compatible = "nvidia,tegra264-sfc",
- "nvidia,tegra210-sfc";
+ "nvidia,tegra210-sfc";
reg = <0x9710000 x0 0x10000>;
sound-name-prefix = "SFC2";
@@ -1611,7 +1610,7 @@ sfc2_cif_out: endpoint {
tegra_sfc3: sfc@9720000 {
compatible = "nvidia,tegra264-sfc",
- "nvidia,tegra210-sfc";
+ "nvidia,tegra210-sfc";
reg = <0x9720000 0x10000>;
sound-name-prefix = "SFC3";
@@ -1639,7 +1638,7 @@ sfc3_cif_out: endpoint {
tegra_sfc4: sfc@9730000 {
compatible = "nvidia,tegra264-sfc",
- "nvidia,tegra210-sfc";
+ "nvidia,tegra210-sfc";
reg = <0x9730000 0x10000>;
sound-name-prefix = "SFC4";
@@ -1667,7 +1666,7 @@ sfc4_cif_out: endpoint {
tegra_ope1: processing-engine@9780000 {
compatible = "nvidia,tegra264-ope",
- "nvidia,tegra210-ope";
+ "nvidia,tegra210-ope";
reg = <0x9780000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1676,13 +1675,13 @@ tegra_ope1: processing-engine@9780000 {
equalizer@9790000 {
compatible = "nvidia,tegra264-peq",
- "nvidia,tegra210-peq";
+ "nvidia,tegra210-peq";
reg = <0x9790000 0x10000>;
};
dynamic-range-compressor@97a0000 {
compatible = "nvidia,tegra264-mbdrc",
- "nvidia,tegra210-mbdrc";
+ "nvidia,tegra210-mbdrc";
reg = <0x97a0000 0x10000>;
};
@@ -1694,8 +1693,7 @@ port@0 {
reg = <0x0>;
ope1_cif_in_ep: endpoint {
- remote-endpoint =
- <&xbar_ope1_in_ep>;
+ remote-endpoint = <&xbar_ope1_in_ep>;
};
};
@@ -1703,8 +1701,7 @@ ope1_out_port: port@1 {
reg = <0x1>;
ope1_cif_out_ep: endpoint {
- remote-endpoint =
- <&xbar_ope1_out_ep>;
+ remote-endpoint = <&xbar_ope1_out_ep>;
};
};
};
@@ -1712,7 +1709,7 @@ ope1_cif_out_ep: endpoint {
tegra_mvc1: mvc@9800000 {
compatible = "nvidia,tegra264-mvc",
- "nvidia,tegra210-mvc";
+ "nvidia,tegra210-mvc";
reg = <0x9800000 0x10000>;
sound-name-prefix = "MVC1";
@@ -1740,7 +1737,7 @@ mvc1_cif_out: endpoint {
tegra_mvc2: mvc@9810000 {
compatible = "nvidia,tegra264-mvc",
- "nvidia,tegra210-mvc";
+ "nvidia,tegra210-mvc";
reg = <0x9810000 0x10000>;
sound-name-prefix = "MVC2";
@@ -1768,7 +1765,7 @@ mvc2_cif_out: endpoint {
tegra_amixer: amixer@9820000 {
compatible = "nvidia,tegra264-amixer",
- "nvidia,tegra210-amixer";
+ "nvidia,tegra210-amixer";
reg = <0x9820000 0x10000>;
sound-name-prefix = "MIXER1";
@@ -1911,8 +1908,7 @@ port@0 {
reg = <0x0>;
asrc_in1_ep: endpoint {
- remote-endpoint =
- <&xbar_asrc_in1_ep>;
+ remote-endpoint = <&xbar_asrc_in1_ep>;
};
};
@@ -1920,8 +1916,7 @@ port@1 {
reg = <0x1>;
asrc_in2_ep: endpoint {
- remote-endpoint =
- <&xbar_asrc_in2_ep>;
+ remote-endpoint = <&xbar_asrc_in2_ep>;
};
};
@@ -1929,8 +1924,7 @@ port@2 {
reg = <0x2>;
asrc_in3_ep: endpoint {
- remote-endpoint =
- <&xbar_asrc_in3_ep>;
+ remote-endpoint = <&xbar_asrc_in3_ep>;
};
};
@@ -1938,8 +1932,7 @@ port@3 {
reg = <0x3>;
asrc_in4_ep: endpoint {
- remote-endpoint =
- <&xbar_asrc_in4_ep>;
+ remote-endpoint = <&xbar_asrc_in4_ep>;
};
};
@@ -1947,8 +1940,7 @@ port@4 {
reg = <0x4>;
asrc_in5_ep: endpoint {
- remote-endpoint =
- <&xbar_asrc_in5_ep>;
+ remote-endpoint = <&xbar_asrc_in5_ep>;
};
};
@@ -1956,8 +1948,7 @@ port@5 {
reg = <0x5>;
asrc_in6_ep: endpoint {
- remote-endpoint =
- <&xbar_asrc_in6_ep>;
+ remote-endpoint = <&xbar_asrc_in6_ep>;
};
};
@@ -1965,8 +1956,7 @@ port@6 {
reg = <0x6>;
asrc_in7_ep: endpoint {
- remote-endpoint =
- <&xbar_asrc_in7_ep>;
+ remote-endpoint = <&xbar_asrc_in7_ep>;
};
};
@@ -1974,8 +1964,7 @@ asrc_out1_port: port@7 {
reg = <0x7>;
asrc_out1_ep: endpoint {
- remote-endpoint =
- <&xbar_asrc_out1_ep>;
+ remote-endpoint = <&xbar_asrc_out1_ep>;
};
};
@@ -1983,8 +1972,7 @@ asrc_out2_port: port@8 {
reg = <0x8>;
asrc_out2_ep: endpoint {
- remote-endpoint =
- <&xbar_asrc_out2_ep>;
+ remote-endpoint = <&xbar_asrc_out2_ep>;
};
};
@@ -1992,8 +1980,7 @@ asrc_out3_port: port@9 {
reg = <0x9>;
asrc_out3_ep: endpoint {
- remote-endpoint =
- <&xbar_asrc_out3_ep>;
+ remote-endpoint = <&xbar_asrc_out3_ep>;
};
};
@@ -2001,8 +1988,7 @@ asrc_out4_port: port@a {
reg = <0xa>;
asrc_out4_ep: endpoint {
- remote-endpoint =
- <&xbar_asrc_out4_ep>;
+ remote-endpoint = <&xbar_asrc_out4_ep>;
};
};
@@ -2010,8 +1996,7 @@ asrc_out5_port: port@b {
reg = <0xb>;
asrc_out5_ep: endpoint {
- remote-endpoint =
- <&xbar_asrc_out5_ep>;
+ remote-endpoint = <&xbar_asrc_out5_ep>;
};
};
@@ -2019,8 +2004,7 @@ asrc_out6_port: port@c {
reg = <0xc>;
asrc_out6_ep: endpoint {
- remote-endpoint =
- <&xbar_asrc_out6_ep>;
+ remote-endpoint = <&xbar_asrc_out6_ep>;
};
};
};
@@ -3194,13 +3178,12 @@ xbar_ope1_out_ep: endpoint {
agic_page0: interrupt-controller@9960000 {
compatible = "nvidia,tegra264-agic",
- "nvidia,tegra210-agic";
+ "nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x9961000 0x1000>,
<0x9962000 0x1000>;
- interrupts = <GIC_SPI 0x230
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_SPI 0x230 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA264_CLK_ADSP>;
clock-names = "clk";
status = "disabled";
@@ -3208,13 +3191,12 @@ agic_page0: interrupt-controller@9960000 {
agic_page1: interrupt-controller@9970000 {
compatible = "nvidia,tegra264-agic",
- "nvidia,tegra210-agic";
+ "nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x9971000 0x1000>,
<0x9972000 0x1000>;
- interrupts = <GIC_SPI 0x231
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_SPI 0x231 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA264_CLK_ADSP>;
clock-names = "clk";
status = "disabled";
@@ -3222,13 +3204,12 @@ agic_page1: interrupt-controller@9970000 {
agic_page2: interrupt-controller@9980000 {
compatible = "nvidia,tegra264-agic",
- "nvidia,tegra210-agic";
+ "nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x9981000 0x1000>,
<0x9982000 0x1000>;
- interrupts = <GIC_SPI 0x232
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_SPI 0x232 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA264_CLK_ADSP>;
clock-names = "clk";
status = "disabled";
@@ -3236,13 +3217,12 @@ agic_page2: interrupt-controller@9980000 {
agic_page3: interrupt-controller@9990000 {
compatible = "nvidia,tegra264-agic",
- "nvidia,tegra210-agic";
+ "nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x9991000 0x1000>,
<0x9992000 0x1000>;
- interrupts = <GIC_SPI 0x233
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_SPI 0x233 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA264_CLK_ADSP>;
clock-names = "clk";
status = "disabled";
@@ -3250,13 +3230,12 @@ agic_page3: interrupt-controller@9990000 {
agic_page4: interrupt-controller@99a0000 {
compatible = "nvidia,tegra264-agic",
- "nvidia,tegra210-agic";
+ "nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x99a1000 0x1000>,
<0x99a2000 0x1000>;
- interrupts = <GIC_SPI 0x234
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_SPI 0x234 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA264_CLK_ADSP>;
clock-names = "clk";
status = "disabled";
@@ -3264,13 +3243,12 @@ agic_page4: interrupt-controller@99a0000 {
agic_page5: interrupt-controller@99b0000 {
compatible = "nvidia,tegra264-agic",
- "nvidia,tegra210-agic";
+ "nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x99b1000 0x1000>,
<0x99b2000 0x1000>;
- interrupts = <GIC_SPI 0x235
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_SPI 0x235 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA264_CLK_ADSP>;
clock-names = "clk";
status = "disabled";
--
2.55.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: (subset) [PATCH 0/8] arm64: tegra: Clean up AHUB device tree nodes
2026-09-02 10:17 [PATCH 0/8] arm64: tegra: Clean up AHUB device tree nodes Thierry Reding
` (7 preceding siblings ...)
2026-09-02 10:17 ` [PATCH 8/8] arm64: tegra: Clean up some whitespace issues " Thierry Reding
@ 2026-09-10 13:31 ` Thierry Reding
8 siblings, 0 replies; 14+ messages in thread
From: Thierry Reding @ 2026-09-10 13:31 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jonathan Hunter,
Thierry Reding
Cc: Charan Pedumuru, devicetree, linux-tegra, linux-kernel
From: Thierry Reding <treding@nvidia.com>
On Wed, 02 Sep 2026 12:17:36 +0200, Thierry Reding wrote:
> This series was prompted by some discussion on this thread:
>
> https://lore.kernel.org/linux-tegra/20260705-nvidia-ahub-v3-1-bacb7e05bf68@gmail.com/
>
> In a nutshell, yes, the AHUB can do with #address-cells = <1> and the
> corresponding #size-cells = <1> since all of the children are in a
> fairly small register region. I suspect the primary reason we stuck to
> the #address-cells = <2> was so that the ranges property wasn't
> required.
>
> [...]
Applied, thanks!
[1/8] ARM: tegra: Clean up AHUB on Tegra124
(no commit info)
Best regards,
--
Thierry Reding <treding@nvidia.com>
^ permalink raw reply [flat|nested] 14+ messages in thread