Re: [PATCH v1 04/11] ARM: dts: imx6ul: Add Variscite audio codec files

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] ASoC: dt-bindings: missing DAPM routing for Microphone Jack on SOM WM8904
- [High] ASoC: simple-audio-card: fixed 12.288MHz clock on WM8731 breaks 44.1kHz playback
- [High] dt-bindings: wm8904: DCVDD and CPVDD supplies incorrectly set to 3.3V
- [Low] dt-bindings: wm8731: 100% file duplication between DART and SOM variants
--

commit 85c31b80442521c0f29d03e856f06165c8f204fc
Author: Stefano Radaelli <stefano.r@variscite.com>

ARM: dts: imx6ul: Add Variscite audio codec files

Add separate DTSI files for the WM8904 and WM8731 audio options on
VAR-SOM-6UL and DART-6UL modules. Put each codec node, the SAI2 setup and
its pinctrl in the selected audio DTSI.

> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-dart-wm8731.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-dart-wm8731.dtsi
> new file mode 100644
> index 0000000000000..7d74fc3b7014c
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-dart-wm8731.dtsi
> @@ -0,0 +1,71 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com
> + */

[ ... ]

> +		sound_master: simple-audio-card,cpu {
> +			sound-dai = <&sai2>;
> +		};
> +
> +		simple-audio-card,codec {
> +			sound-dai = <&codec>;
> +			system-clock-frequency = <12288000>;

[Severity: High]
Does this fixed clock frequency break 44.1kHz audio playback?

Using a static 12.288MHz system-clock-frequency without
simple-audio-card,mclk-fs prevents dynamic ALSA reclocking. The wm8731 driver
needs 11.2896MHz for 44.1kHz playback, so setting a fixed 12.288MHz might
cause 44.1kHz streams to be rejected.

> +		};
> +	};
> +};

[ ... ]

> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-dart-wm8904.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-dart-wm8904.dtsi
> new file mode 100644
> index 0000000000000..1e1ff8c6d7b56
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-dart-wm8904.dtsi
> @@ -0,0 +1,88 @@

[ ... ]

> +&i2c2 {
> +	codec: audio-codec@1a {
> +		compatible = "wlf,wm8904";
> +		reg = <0x1a>;
> +		#sound-dai-cells = <0>;
> +		clocks = <&clks IMX6UL_CLK_SAI2>;
> +		clock-names = "mclk";
> +		AVDD-supply = <&reg_3p3v>;
> +		CPVDD-supply = <&reg_3p3v>;
> +		DBVDD-supply = <&reg_3p3v>;
> +		DCVDD-supply = <&reg_3p3v>;

[Severity: High]
Is it safe to assign a 3.3V supply to CPVDD and DCVDD?

These pins on the WM8904 have a 2.0V absolute maximum rating. Assigning
reg_3p3v to CPVDD-supply and DCVDD-supply misrepresents the hardware and
could be dangerous if the regulator is dynamically controllable or used as
a reference.

> +		MICVDD-supply = <&reg_3p3v>;

[ ... ]

> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-som-wm8731.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-som-wm8731.dtsi
> new file mode 100644
> index 0000000000000..7d74fc3b7014c
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-som-wm8731.dtsi
> @@ -0,0 +1,71 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com
> + */

[Severity: Low]
Could this file be consolidated with the DART variant?

This entire file appears to be a 100% byte-for-byte duplicate of
imx6ul-imx6ull-var-dart-wm8731.dtsi, which might create a maintenance burden
when making future updates.

[ ... ]

> +		sound_master: simple-audio-card,cpu {
> +			sound-dai = <&sai2>;
> +		};
> +
> +		simple-audio-card,codec {
> +			sound-dai = <&codec>;
> +			system-clock-frequency = <12288000>;

[Severity: High]
Does this fixed clock frequency break 44.1kHz audio playback?

Using a static 12.288MHz system-clock-frequency without
simple-audio-card,mclk-fs prevents dynamic ALSA reclocking. The wm8731 driver
needs 11.2896MHz for 44.1kHz playback, so setting a fixed 12.288MHz might
cause 44.1kHz streams to be rejected.

> +		};
> +	};
> +};

[ ... ]

> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-som-wm8904.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-som-wm8904.dtsi
> new file mode 100644
> index 0000000000000..72a73011af6f7
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-som-wm8904.dtsi
> @@ -0,0 +1,85 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com
> + */
> +
> +/ {
> +	sound {
> +		compatible = "simple-audio-card";
> +		simple-audio-card,bitclock-master = <&sound_master>;
> +		simple-audio-card,format = "i2s";
> +		simple-audio-card,frame-master = <&sound_master>;
> +		simple-audio-card,name = "wm8904audio";
> +		simple-audio-card,routing =
> +			"Headphone Jack", "HPOUTL",
> +			"Headphone Jack", "HPOUTR",
> +			"IN1L", "Line In Jack",
> +			"IN1R", "Line In Jack";
> +		simple-audio-card,widgets =
> +			"Microphone", "Microphone Jack",

[Severity: High]
Is the microphone input path broken here due to missing DAPM routing?

The Microphone Jack widget is declared in simple-audio-card,widgets but
it is completely omitted from the simple-audio-card,routing map. Without this
routing, the DAPM framework will consider the microphone path inactive and
won't power on the mic bias or ADC paths when recording.

> +			"Headphone", "Headphone Jack",
> +			"Line", "Line In Jack";

[ ... ]

> +&i2c2 {
> +	codec: audio-codec@1a {
> +		compatible = "wlf,wm8904";
> +		reg = <0x1a>;
> +		#sound-dai-cells = <0>;
> +		clocks = <&clks IMX6UL_CLK_SAI2>;
> +		clock-names = "mclk";
> +		AVDD-supply = <&reg_3p3v>;
> +		CPVDD-supply = <&reg_3p3v>;
> +		DBVDD-supply = <&reg_3p3v>;
> +		DCVDD-supply = <&reg_3p3v>;

[Severity: High]
Is it safe to assign a 3.3V supply to CPVDD and DCVDD?

These pins on the WM8904 have a 2.0V absolute maximum rating. Assigning
reg_3p3v to CPVDD-supply and DCVDD-supply misrepresents the hardware and
could be dangerous if the regulator is dynamically controllable or used as
a reference.

> +		MICVDD-supply = <&reg_3p3v>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1790344389.git.stefano.r@variscite.com?part=4