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From: sashiko-bot@kernel.org
To: "Mayuresh Chitale" <mayuresh.chitale@oss.qualcomm.com>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org
Subject: Re: [PATCH v6 01/14] dt-bindings: Add RISC-V trace component bindings
Date: Thu, 01 Oct 2026 05:33:58 +0000	[thread overview]
Message-ID: <20261001053358.C93561F0089B@smtp.kernel.org> (raw)
In-Reply-To: <20261001052243.3042627-2-mayuresh.chitale@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] dt-bindings: riscv: arbitrary 8-port limitation in trace component schema
- [Low] dt-bindings: riscv: missing reciprocal remote-endpoint in trace example
--

commit cd6c17f8ffc8a03ed1ca9c2518f088b9871f8ccc
Author: Anup Patel <anup.patel@oss.qualcomm.com>

dt-bindings: Add RISC-V trace component bindings

This adds device tree bindings for the memory mapped RISC-V trace components
which support both the RISC-V efficient trace (E-trace) and Nexus-based
trace (N-trace) protocols.

> diff --git a/Documentation/devicetree/bindings/riscv/riscv,trace-component.yaml b/Documentation/devicetree/bindings/riscv/riscv,trace-component.yaml
> new file mode 100644
> index 0000000000000..bb519bc4a163e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/riscv,trace-component.yaml

[ ... ]

> +  in-ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +    patternProperties:
> +      '^port(@[0-7])?$':

[Severity: Low]
Does this unintentionally restrict the trace component schema to a maximum of 8
input ports? The commit message mentions that RISC-V trace components have an
implementation-specific directed acyclic graph style interdependency. Since the
RISC-V specification does not enforce an 8-port limit, any future or existing
SoC implementation featuring a funnel with 9 or more ports (e.g., port@8 or
port@f) will artificially fail dt-schema validation.

Could the pattern be updated to use standard hexadecimal device tree unit
addresses, such as '^port(@[0-9a-f]+)?$'?

> +        description: Input connections from RISC-V trace component
> +        $ref: /schemas/graph.yaml#/properties/port
> +
> +  out-ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +    patternProperties:
> +      '^port(@[0-7])?$':

[Severity: Low]
Similar to the in-ports property above, does this pattern artificially limit
the output connections to 8? Updating the regex to support standard hex unit
addresses would prevent validation failures for components with more than 8
output ports.

> +        description: Output connections from RISC-V trace component
> +        $ref: /schemas/graph.yaml#/properties/port

[ ... ]

> +    trace@c001000 {
> +      compatible = "qemu,trace-component", "riscv,trace-component";
> +      reg = <0xc001000 0x1000>;
> +      cpus = <&CPU0>;
> +
> +      in-ports {
> +        port {
> +          CPU0_RAMSINK_INPUT: endpoint {
> +          };

[Severity: Low]
Is there a missing reciprocal remote-endpoint property in this example node?
Standard device tree graph bindings specify that links between components must
be bidirectional when both nodes are present in the device tree.

In the example above, the encoder (trace@c000000) correctly points to the sink
by defining remote-endpoint = <&CPU0_RAMSINK_INPUT>;. However, the
corresponding ramsink endpoint (CPU0_RAMSINK_INPUT) is completely empty and
omits remote-endpoint = <&CPU0_ENCODER_OUTPUT>;. 

The kernel's of_graph API and dtc parsing tools rely on bidirectional
references to traverse the trace topology. Omitting the back-reference breaks
backward traversal and causes dtc compiler warnings for missing bidirectional
links.

> +        };
> +      };
> +    };

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261001052243.3042627-1-mayuresh.chitale@oss.qualcomm.com?part=1

  reply	other threads:[~2026-10-01  5:33 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-01  5:22 [PATCH v6 00/14] Linux RISC-V trace framework and drivers Mayuresh Chitale
2026-10-01  5:22 ` [PATCH v6 01/14] dt-bindings: Add RISC-V trace component bindings Mayuresh Chitale
2026-10-01  5:33   ` sashiko-bot [this message]
2026-10-01  5:22 ` [PATCH v6 02/14] hwtracing: gtrace: Initial implementation of gtrace framework Mayuresh Chitale
2026-10-01  5:37   ` sashiko-bot
2026-10-01  5:22 ` [PATCH v6 03/14] gtrace: Add RISC-V platform driver for the " Mayuresh Chitale
2026-10-01  5:36   ` sashiko-bot
2026-10-01  5:22 ` [PATCH v6 04/14] gtrace: Add functions to create/destroy a trace component path Mayuresh Chitale
2026-10-01  5:36   ` sashiko-bot
2026-10-01  5:22 ` [PATCH v6 05/14] gtrace: Add functions to start/stop tracing on a " Mayuresh Chitale
2026-10-01  5:36   ` sashiko-bot
2026-10-01  5:22 ` [PATCH v6 06/14] gtrace: Add RISC-V Trace encoder driver Mayuresh Chitale
2026-10-01  5:34   ` sashiko-bot
2026-10-01  5:22 ` [PATCH v6 07/14] gtrace: Add function to copy into perf AUX buffer Mayuresh Chitale
2026-10-01  5:40   ` sashiko-bot
2026-10-01  5:22 ` [PATCH v6 08/14] perf: Add gtrace AUX buffer trace format type Mayuresh Chitale
2026-10-01  5:22 ` [PATCH v6 09/14] gtrace: Add RISC-V Trace ramsink driver Mayuresh Chitale
2026-10-01  5:42   ` sashiko-bot
2026-10-01  5:22 ` [PATCH v6 10/14] riscv: Enable DMA_RESTRICTED_POOL in defconfig Mayuresh Chitale
2026-10-01  5:22 ` [PATCH v6 11/14] gtrace: Add perf driver for tracing using perf tool Mayuresh Chitale
2026-10-01  5:44   ` sashiko-bot
2026-10-01  5:22 ` [PATCH v6 12/14] perf tools: Add RISC-V trace PMU record capabilities Mayuresh Chitale
2026-10-01  5:22 ` [PATCH v6 13/14] perf tools: Initial support for gtrace decoder Mayuresh Chitale
2026-10-01  5:35   ` sashiko-bot
2026-10-01  5:22 ` [PATCH v6 14/14] MAINTAINERS: Add entry for RISC-V trace framework Mayuresh Chitale

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