* [PATCH v2 01/10] dt-bindings: ptp: Document the TSCSS on Qualcomm SA8775P and QCS8300 SoCs
2026-11-08 13:18 [PATCH v2 00/10] Add support for Qualcomm TSCSS hardware Imran Shaik
@ 2026-11-08 13:18 ` Imran Shaik
2026-11-09 12:48 ` Krzysztof Kozlowski
2026-11-09 13:19 ` sashiko-bot
2026-11-08 13:18 ` [PATCH v2 02/10] dt-bindings: ptp: Document TSCSS hardware on Qualcomm QDU1000 SoC Imran Shaik
` (8 subsequent siblings)
9 siblings, 2 replies; 24+ messages in thread
From: Imran Shaik @ 2026-11-08 13:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Eric Dumazet
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev, Imran Shaik
Add Devicetree bindings for the Timestamp Counter Subsystem (TSCSS) found
on Qualcomm SA8775P and QCS8300 SoCs.
TSCSS is a time synchronization subsystem composed of two main blocks:
Timestamp Counter (TSC) and Event Timestamp Unit (ETU). The TSC block
provides a continuously running counter used for timekeeping, while the
ETU captures timestamps for external hardware event triggers.
Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
.../bindings/ptp/qcom,sa8775p-tscss.yaml | 169 +++++++++++++++++++++
1 file changed, 169 insertions(+)
diff --git a/Documentation/devicetree/bindings/ptp/qcom,sa8775p-tscss.yaml b/Documentation/devicetree/bindings/ptp/qcom,sa8775p-tscss.yaml
new file mode 100644
index 000000000000..b3e3a7cd7166
--- /dev/null
+++ b/Documentation/devicetree/bindings/ptp/qcom,sa8775p-tscss.yaml
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ptp/qcom,sa8775p-tscss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Timestamp Counter Subsystem (TSCSS) on Qualcomm SA8775P and QCS8300
+
+maintainers:
+ - Imran Shaik <imran.shaik@oss.qualcomm.com>
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm TSCSS is a time synchronization subsystem composed of two main
+ blocks - the Timestamp Counter (TSC) and the Event Timestamp Unit (ETU).
+
+ The TSC block is a timestamp generator that maintains a running counter used
+ for system timekeeping, and is functional with just the AHB and counter
+ clocks.
+ The ETU block captures TSC timestamps for external hardware events. Each
+ ETU slice binds a slice number to an external event selector, and a
+ single summary interrupt is raised for any ETU slice event.
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,sa8775p-tscss
+ - items:
+ - const: qcom,qcs8300-tscss
+ - const: qcom,sa8775p-tscss
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: tsc
+ - const: etu
+
+ clocks:
+ items:
+ - description: TSC AHB configuration clock.
+ - description: TSC global counter clock.
+ - description: TSC ETU clock.
+
+ clock-names:
+ items:
+ - const: ahb
+ - const: cntr
+ - const: etu
+
+ interrupts:
+ items:
+ - description:
+ Summary interrupt raised based on an external event for any
+ of the ETU slices.
+
+ interrupt-names:
+ items:
+ - const: etu_summary
+
+ pinctrl-names:
+ minItems: 1
+ maxItems: 16
+ items:
+ pattern: "^slice[0-9]+$"
+
+ qcom,etu-slice:
+ description:
+ ETU slice number for each entry in pinctrl-<n>, pinctrl-names and
+ qcom,etu-event-sel.
+ minItems: 1
+ maxItems: 16
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ qcom,etu-event-sel:
+ description:
+ External event selection value for each ETU slice listed in
+ qcom,etu-slice.
+ minItems: 1
+ maxItems: 16
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ reg-names:
+ contains:
+ const: etu
+ then:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 2
+ required:
+ - interrupts
+ - interrupt-names
+ - pinctrl-names
+ - qcom,etu-slice
+ - qcom,etu-event-sel
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ptp@1c80000 {
+ compatible = "qcom,sa8775p-tscss";
+ reg = <0x0 0x01c80000 0x0 0x2000>;
+ reg-names = "tsc";
+
+ clocks = <&gcc GCC_TSCSS_AHB_CLK>,
+ <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>,
+ <&gcc GCC_TSCSS_ETU_CLK>;
+ clock-names = "ahb", "cntr", "etu";
+
+ assigned-clocks = <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>;
+ assigned-clock-rates = <15625000>;
+ };
+ };
+
+ - |
+ #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ptp@1c80000 {
+ compatible = "qcom,sa8775p-tscss";
+ reg = <0x0 0x01c80000 0x0 0x2000>,
+ <0x0 0x01c90000 0x0 0x10000>;
+ reg-names = "tsc", "etu";
+
+ clocks = <&gcc GCC_TSCSS_AHB_CLK>,
+ <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>,
+ <&gcc GCC_TSCSS_ETU_CLK>;
+ clock-names = "ahb", "cntr", "etu";
+
+ assigned-clocks = <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>;
+ assigned-clock-rates = <15625000>;
+
+ interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "etu_summary";
+
+ pinctrl-0 = <&cci_timer0>;
+ pinctrl-1 = <&cci_timer1>;
+ pinctrl-names = "slice1", "slice2";
+
+ qcom,etu-slice = <1 2>;
+ qcom,etu-event-sel = <1 2>;
+ };
+ };
+...
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 01/10] dt-bindings: ptp: Document the TSCSS on Qualcomm SA8775P and QCS8300 SoCs
2026-11-08 13:18 ` [PATCH v2 01/10] dt-bindings: ptp: Document the TSCSS on Qualcomm SA8775P and QCS8300 SoCs Imran Shaik
@ 2026-11-09 12:48 ` Krzysztof Kozlowski
2026-11-12 9:31 ` Imran Shaik
2026-11-09 13:19 ` sashiko-bot
1 sibling, 1 reply; 24+ messages in thread
From: Krzysztof Kozlowski @ 2026-11-09 12:48 UTC (permalink / raw)
To: Imran Shaik
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev
On Sun, Nov 08, 2026 at 06:48:22PM +0530, Imran Shaik wrote:
> +properties:
> + compatible:
> + oneOf:
> + - const: qcom,sa8775p-tscss
> + - items:
> + - const: qcom,qcs8300-tscss
> + - const: qcom,sa8775p-tscss
> +
> + reg:
> + minItems: 1
> + maxItems: 2
> +
> + reg-names:
> + minItems: 1
> + items:
> + - const: tsc
> + - const: etu
...
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> +
> +allOf:
> + - if:
> + properties:
> + reg-names:
> + contains:
> + const: etu
Reason for same devices with different address space details should be
provided somewhere, preferrably in description. Assuming in the first
place, that this stays because how two devices can be basically
identical (same compatible) if they have different programming
interface?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 01/10] dt-bindings: ptp: Document the TSCSS on Qualcomm SA8775P and QCS8300 SoCs
2026-11-09 12:48 ` Krzysztof Kozlowski
@ 2026-11-12 9:31 ` Imran Shaik
0 siblings, 0 replies; 24+ messages in thread
From: Imran Shaik @ 2026-11-12 9:31 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev
On 09-11-2026 06:18 pm, Krzysztof Kozlowski wrote:
> On Sun, Nov 08, 2026 at 06:48:22PM +0530, Imran Shaik wrote:
>> +properties:
>> + compatible:
>> + oneOf:
>> + - const: qcom,sa8775p-tscss
>> + - items:
>> + - const: qcom,qcs8300-tscss
>> + - const: qcom,sa8775p-tscss
>> +
>> + reg:
>> + minItems: 1
>> + maxItems: 2
>> +
>> + reg-names:
>> + minItems: 1
>> + items:
>> + - const: tsc
>> + - const: etu
>
> ...
>
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - clocks
>> + - clock-names
>> +
>> +allOf:
>> + - if:
>> + properties:
>> + reg-names:
>> + contains:
>> + const: etu
>
> Reason for same devices with different address space details should be
> provided somewhere, preferrably in description. Assuming in the first
> place, that this stays because how two devices can be basically
> identical (same compatible) if they have different programming
> interface?
>
TSCSS is a single hardware device, split into two sub-blocks - TSC and
ETU, each with its own register address. Every SoC with this compatible
has both blocks in hardware.
What changes is whether the vendor/board actually wires up the ETU's
external event. The ETU block captures a timestamp from the TSC block
when an external event fires one of the ETU slices, which are driven
through board-level GPIO/IRQs. If a board doesn't wire any slice,
there's nothing in the ETU region for Linux to use.
So interrupts/pinctrl/qcom,etu-* only matter once a slice is actually
connected. Because of this, only the tsc reg space is described in the
DTS patches today.
Instead, I'll use the "qcom,etu-slice" property to drive the required
constraints, and add reg/reg-names support in DTS by default for both
TSC and ETU, and update the description with the above details in the
next series. I hope that works.
Thanks,
Imran
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 01/10] dt-bindings: ptp: Document the TSCSS on Qualcomm SA8775P and QCS8300 SoCs
2026-11-08 13:18 ` [PATCH v2 01/10] dt-bindings: ptp: Document the TSCSS on Qualcomm SA8775P and QCS8300 SoCs Imran Shaik
2026-11-09 12:48 ` Krzysztof Kozlowski
@ 2026-11-09 13:19 ` sashiko-bot
1 sibling, 0 replies; 24+ messages in thread
From: sashiko-bot @ 2026-11-09 13:19 UTC (permalink / raw)
To: Imran Shaik; +Cc: devicetree, robh, conor+dt
Thank you for your contribution! Sashiko AI review found 3 potential
issues to consider:
- [Medium] dt-bindings: ptp: qcom,sa8775p-tscss: misuse of pinctrl
states for ETU slices
- [Medium] dt-bindings: ptp: qcom,sa8775p-tscss: coupling SoC etu reg to
board properties
- [Low] dt-bindings: ptp: qcom,sa8775p-tscss: missing bounds on slice
and event arrays
--
commit b07780b80d655036ec2e7df24ec2f89f821cf257
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>
dt-bindings: ptp: Document the TSCSS on Qualcomm SA8775P and QCS8300 SoCs
This commit adds the Devicetree binding schema for the Timestamp Counter
Subsystem (TSCSS) on Qualcomm SA8775P and QCS8300 SoCs.
> diff --git a/Documentation/devicetree/bindings/ptp/qcom,sa8775p-tscss.yaml b/Documentation/devicetree/bindings/ptp/qcom,sa8775p-tscss.yaml
> new file mode 100644
> index 0000000000000..b3e3a7cd71664
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ptp/qcom,sa8775p-tscss.yaml
[ ... ]
> + reg:
> + minItems: 1
> + maxItems: 2
> +
> + reg-names:
> + minItems: 1
> + items:
> + - const: tsc
> + - const: etu
> +
> + clocks:
> + items:
> + - description: TSC AHB configuration clock.
> + - description: TSC global counter clock.
> + - description: TSC ETU clock.
> +
> + clock-names:
> + items:
> + - const: ahb
> + - const: cntr
> + - const: etu
> +
> + interrupts:
> + items:
> + - description:
> + Summary interrupt raised based on an external event for any
> + of the ETU slices.
> +
> + interrupt-names:
> + items:
> + - const: etu_summary
> +
> + pinctrl-names:
> + minItems: 1
> + maxItems: 16
> + items:
> + pattern: "^slice[0-9]+$"
[Severity: Medium]
Does defining pinctrl-names as per-slice entries ("slice1", "slice2", ...)
and placing each slice's pin into a separate pinctrl-<n> property (as shown
in the second example with pinctrl-0 and pinctrl-1) misuse pinctrl states?
In the Devicetree pinctrl binding and drivers/pinctrl/core.c, pinctrl-0
through pinctrl-N represent mutually exclusive device-wide states such as
"default" and "sleep", not concurrent channels. When pinctrl_commit_state()
switches to a new state on the device, it calls
pinctrl_cond_disable_mux_setting(old_state, NULL), which disables the pinmux
settings of the previously active slice state so multiple slices cannot be
active at the same time. Restricting pinctrl-names to "^slice[0-9]+$" also
prevents standard "default" and "sleep" pin states from being used; all
concurrently active ETU slice pins belong in a single state such as
pinctrl-0 with pinctrl-names = "default".
> + qcom,etu-slice:
> + description:
> + ETU slice number for each entry in pinctrl-<n>, pinctrl-names and
> + qcom,etu-event-sel.
> + minItems: 1
> + maxItems: 16
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> +
> + qcom,etu-event-sel:
> + description:
> + External event selection value for each ETU slice listed in
> + qcom,etu-slice.
> + minItems: 1
> + maxItems: 16
> + $ref: /schemas/types.yaml#/definitions/uint32-array
[Severity: Low]
Should qcom,etu-slice and qcom,etu-event-sel define per-item minimum/maximum
bounds (and uniqueItems: true on qcom,etu-slice)?
Without item bounds, out-of-range slice indices or event selector values and
duplicate slice entries will not be caught by dtbs_check. Also, encoding the
slice index in both pinctrl-names ("^slice[0-9]+$") and qcom,etu-slice
duplicates the slice number across two properties without ensuring they match.
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> +
> +allOf:
> + - if:
> + properties:
> + reg-names:
> + contains:
> + const: etu
> + then:
> + properties:
> + reg:
> + minItems: 2
> + maxItems: 2
> + required:
> + - interrupts
> + - interrupt-names
> + - pinctrl-names
> + - qcom,etu-slice
> + - qcom,etu-event-sel
[Severity: Medium]
Should the SoC-level etu register region and interrupt be decoupled from the
board-specific ETU slice properties?
The tsc and etu register blocks, clocks, and etu_summary interrupt are fixed
SoC resources, whereas pinctrl-names, qcom,etu-slice, and qcom,etu-event-sel
depend on board pin wiring. Requiring the board slice properties whenever
reg-names contains "etu" prevents an SoC dtsi from describing the full TSCSS
register map and interrupt unless every board also configures ETU slices.
In addition, this if/then block has no else branch when "etu" is absent,
which allows reg to have 2 entries when reg-names only lists "tsc" and leaves
the ETU properties allowed without the etu register region. Finally, the
description notes that the TSC block is functional with just the AHB and
counter clocks, yet clocks and clock-names unconditionally require all three
clocks including "etu".
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261108-tscss-v2-0-d5f575010427@oss.qualcomm.com?part=1
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 02/10] dt-bindings: ptp: Document TSCSS hardware on Qualcomm QDU1000 SoC
2026-11-08 13:18 [PATCH v2 00/10] Add support for Qualcomm TSCSS hardware Imran Shaik
2026-11-08 13:18 ` [PATCH v2 01/10] dt-bindings: ptp: Document the TSCSS on Qualcomm SA8775P and QCS8300 SoCs Imran Shaik
@ 2026-11-08 13:18 ` Imran Shaik
2026-11-09 12:49 ` Krzysztof Kozlowski
2026-11-08 13:18 ` [PATCH v2 03/10] dt-bindings: ptp: Document TSCSS hardware on Qualcomm Nord and Shikra SoCs Imran Shaik
` (7 subsequent siblings)
9 siblings, 1 reply; 24+ messages in thread
From: Imran Shaik @ 2026-11-08 13:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Eric Dumazet
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev, Imran Shaik
Add Devicetree bindings for the Timestamp Counter Subsystem (TSCSS) found
on Qualcomm QDU1000 SoC.
TSCSS is a time synchronization subsystem composed of two main blocks:
Timestamp Counter (TSC) and Event Timestamp Unit (ETU). The TSC block
provides a continuously running counter used for timekeeping, while the
ETU captures timestamps for external hardware event triggers.
Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
.../bindings/ptp/qcom,qdu1000-tscss.yaml | 170 +++++++++++++++++++++
1 file changed, 170 insertions(+)
diff --git a/Documentation/devicetree/bindings/ptp/qcom,qdu1000-tscss.yaml b/Documentation/devicetree/bindings/ptp/qcom,qdu1000-tscss.yaml
new file mode 100644
index 000000000000..52a063ec4b78
--- /dev/null
+++ b/Documentation/devicetree/bindings/ptp/qcom,qdu1000-tscss.yaml
@@ -0,0 +1,170 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ptp/qcom,qdu1000-tscss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Timestamp Counter Subsystem (TSCSS) on Qualcomm QDU1000 SoC
+
+maintainers:
+ - Imran Shaik <imran.shaik@oss.qualcomm.com>
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm TSCSS is a time synchronization subsystem composed of two main
+ blocks - the Timestamp Counter (TSC) and the Event Timestamp Unit (ETU).
+
+ The TSC block is a timestamp generator that maintains a running counter used
+ for system timekeeping, and is functional with just the AHB and counter
+ clocks.
+ The ETU block captures TSC timestamps for external hardware events. Each
+ ETU slice binds a slice number to an external event selector, and
+ generates its own interrupt when that event is triggered.
+
+properties:
+ compatible:
+ const: qcom,qdu1000-tscss
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: tsc
+ - const: etu
+
+ clocks:
+ items:
+ - description: TSC AHB configuration clock.
+ - description: TSC global counter clock.
+ - description: TSC ETU clock.
+
+ clock-names:
+ items:
+ - const: ahb
+ - const: cntr
+ - const: etu
+
+ interrupts:
+ minItems: 1
+ maxItems: 16
+ description:
+ Per slice interrupt raised based on an external event mapped to
+ that ETU slice.
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 16
+ items:
+ pattern: "^slice[0-9]+$"
+
+ pinctrl-names:
+ minItems: 1
+ maxItems: 16
+ items:
+ pattern: "^slice[0-9]+$"
+
+ qcom,etu-slice:
+ description:
+ ETU slice number for each entry in interrupts, interrupt-names,
+ pinctrl-<n>, pinctrl-names and qcom,etu-event-sel.
+ minItems: 1
+ maxItems: 16
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ qcom,etu-event-sel:
+ description:
+ External event selection value for each ETU slice listed in
+ qcom,etu-slice.
+ minItems: 1
+ maxItems: 16
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ reg-names:
+ contains:
+ const: etu
+ then:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 2
+ required:
+ - interrupts
+ - interrupt-names
+ - pinctrl-names
+ - qcom,etu-slice
+ - qcom,etu-event-sel
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ptp@1da0000 {
+ compatible = "qcom,qdu1000-tscss";
+ reg = <0x0 0x01da0000 0x0 0x2000>;
+ reg-names = "tsc";
+
+ clocks = <&gcc GCC_TSC_CFG_AHB_CLK>,
+ <&gcc GCC_TSC_CNTR_CLK>,
+ <&gcc GCC_TSC_ETU_CLK>;
+ clock-names = "ahb", "cntr", "etu";
+ assigned-clocks = <&gcc GCC_TSC_CNTR_CLK>;
+ assigned-clock-rates = <500000000>;
+ };
+ };
+
+ - |
+ #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ptp@1da0000 {
+ compatible = "qcom,qdu1000-tscss";
+ reg = <0x0 0x01da0000 0x0 0x2000>,
+ <0x0 0x01db0000 0x0 0x10000>;
+ reg-names = "tsc", "etu";
+
+ clocks = <&gcc GCC_TSC_CFG_AHB_CLK>,
+ <&gcc GCC_TSC_CNTR_CLK>,
+ <&gcc GCC_TSC_ETU_CLK>;
+ clock-names = "ahb", "cntr", "etu";
+
+ assigned-clocks = <&gcc GCC_TSC_CNTR_CLK>;
+ assigned-clock-rates = <500000000>;
+
+ interrupts = <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "slice1", "slice5", "slice6";
+
+ pinctrl-0 = <&tod_pps>;
+ pinctrl-1 = <&gps_pps>;
+ pinctrl-2 = <&hardsync_pps>;
+ pinctrl-names = "slice1", "slice5", "slice6";
+
+ qcom,etu-slice = <1 5 6>;
+ qcom,etu-event-sel = <1 3 2>;
+ };
+ };
+...
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 02/10] dt-bindings: ptp: Document TSCSS hardware on Qualcomm QDU1000 SoC
2026-11-08 13:18 ` [PATCH v2 02/10] dt-bindings: ptp: Document TSCSS hardware on Qualcomm QDU1000 SoC Imran Shaik
@ 2026-11-09 12:49 ` Krzysztof Kozlowski
2026-11-12 9:32 ` Imran Shaik
0 siblings, 1 reply; 24+ messages in thread
From: Krzysztof Kozlowski @ 2026-11-09 12:49 UTC (permalink / raw)
To: Imran Shaik
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev
On Sun, Nov 08, 2026 at 06:48:23PM +0530, Imran Shaik wrote:
> Add Devicetree bindings for the Timestamp Counter Subsystem (TSCSS) found
> on Qualcomm QDU1000 SoC.
>
> TSCSS is a time synchronization subsystem composed of two main blocks:
> Timestamp Counter (TSC) and Event Timestamp Unit (ETU). The TSC block
> provides a continuously running counter used for timekeeping, while the
> ETU captures timestamps for external hardware event triggers.
>
> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
> ---
> .../bindings/ptp/qcom,qdu1000-tscss.yaml | 170 +++++++++++++++++++++
> 1 file changed, 170 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/ptp/qcom,qdu1000-tscss.yaml b/Documentation/devicetree/bindings/ptp/qcom,qdu1000-tscss.yaml
> new file mode 100644
> index 000000000000..52a063ec4b78
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ptp/qcom,qdu1000-tscss.yaml
> @@ -0,0 +1,170 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/ptp/qcom,qdu1000-tscss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Timestamp Counter Subsystem (TSCSS) on Qualcomm QDU1000 SoC
> +
> +maintainers:
> + - Imran Shaik <imran.shaik@oss.qualcomm.com>
> + - Taniya Das <taniya.das@oss.qualcomm.com>
> +
> +description: |
> + Qualcomm TSCSS is a time synchronization subsystem composed of two main
> + blocks - the Timestamp Counter (TSC) and the Event Timestamp Unit (ETU).
> +
> + The TSC block is a timestamp generator that maintains a running counter used
> + for system timekeeping, and is functional with just the AHB and counter
> + clocks.
> + The ETU block captures TSC timestamps for external hardware events. Each
> + ETU slice binds a slice number to an external event selector, and
> + generates its own interrupt when that event is triggered.
> +
> +properties:
> + compatible:
> + const: qcom,qdu1000-tscss
I failed to spot the difference against your binding at patch #1. How do
they differ?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 02/10] dt-bindings: ptp: Document TSCSS hardware on Qualcomm QDU1000 SoC
2026-11-09 12:49 ` Krzysztof Kozlowski
@ 2026-11-12 9:32 ` Imran Shaik
0 siblings, 0 replies; 24+ messages in thread
From: Imran Shaik @ 2026-11-12 9:32 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev
On 09-11-2026 06:19 pm, Krzysztof Kozlowski wrote:
> On Sun, Nov 08, 2026 at 06:48:23PM +0530, Imran Shaik wrote:
>> Add Devicetree bindings for the Timestamp Counter Subsystem (TSCSS) found
>> on Qualcomm QDU1000 SoC.
>>
>> TSCSS is a time synchronization subsystem composed of two main blocks:
>> Timestamp Counter (TSC) and Event Timestamp Unit (ETU). The TSC block
>> provides a continuously running counter used for timekeeping, while the
>> ETU captures timestamps for external hardware event triggers.
>>
>> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
>> ---
>> .../bindings/ptp/qcom,qdu1000-tscss.yaml | 170 +++++++++++++++++++++
>> 1 file changed, 170 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/ptp/qcom,qdu1000-tscss.yaml b/Documentation/devicetree/bindings/ptp/qcom,qdu1000-tscss.yaml
>> new file mode 100644
>> index 000000000000..52a063ec4b78
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/ptp/qcom,qdu1000-tscss.yaml
>> @@ -0,0 +1,170 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/ptp/qcom,qdu1000-tscss.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Timestamp Counter Subsystem (TSCSS) on Qualcomm QDU1000 SoC
>> +
>> +maintainers:
>> + - Imran Shaik <imran.shaik@oss.qualcomm.com>
>> + - Taniya Das <taniya.das@oss.qualcomm.com>
>> +
>> +description: |
>> + Qualcomm TSCSS is a time synchronization subsystem composed of two main
>> + blocks - the Timestamp Counter (TSC) and the Event Timestamp Unit (ETU).
>> +
>> + The TSC block is a timestamp generator that maintains a running counter used
>> + for system timekeeping, and is functional with just the AHB and counter
>> + clocks.
>> + The ETU block captures TSC timestamps for external hardware events. Each
>> + ETU slice binds a slice number to an external event selector, and
>> + generates its own interrupt when that event is triggered.
>> +
>> +properties:
>> + compatible:
>> + const: qcom,qdu1000-tscss
>
> I failed to spot the difference against your binding at patch #1. How do
> they differ?
>
The ETU interrupt wiring between the QDU1000 and SA8775P/QCS8300 is
different.
The SA8775P/QCS8300 share one summary interrupt across all ETU slices,
and the QDU1000 has each slice with its own interrupt line. Due to this,
kept them as separate bindings.
Can add them into one file with an if/then on compatible if you'd
prefer. Please let me know.
Thanks,
Imran
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 03/10] dt-bindings: ptp: Document TSCSS hardware on Qualcomm Nord and Shikra SoCs
2026-11-08 13:18 [PATCH v2 00/10] Add support for Qualcomm TSCSS hardware Imran Shaik
2026-11-08 13:18 ` [PATCH v2 01/10] dt-bindings: ptp: Document the TSCSS on Qualcomm SA8775P and QCS8300 SoCs Imran Shaik
2026-11-08 13:18 ` [PATCH v2 02/10] dt-bindings: ptp: Document TSCSS hardware on Qualcomm QDU1000 SoC Imran Shaik
@ 2026-11-08 13:18 ` Imran Shaik
2026-11-09 12:51 ` Krzysztof Kozlowski
2026-11-09 13:19 ` sashiko-bot
2026-11-08 13:18 ` [PATCH v2 04/10] ptp: qcom: Add PTP driver for the Qualcomm TSC hardware Imran Shaik
` (6 subsequent siblings)
9 siblings, 2 replies; 24+ messages in thread
From: Imran Shaik @ 2026-11-08 13:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Eric Dumazet
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev, Imran Shaik
Add Devicetree bindings for the Timestamp Counter Subsystem (TSCSS) found
on Qualcomm Nord and Shikra SoCs.
TSCSS is a time synchronization subsystem composed of two main blocks:
Timestamp Counter (TSC) and Event Timestamp Unit (ETU). The TSC block
provides a continuously running counter used for timekeeping, while the
ETU captures timestamps for external hardware event triggers.
Nord additionally has a timer register region used to generate a
periodic pulse in sync with the TSC counter.
Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
.../devicetree/bindings/ptp/qcom,nord-tscss.yaml | 186 +++++++++++++++++++++
1 file changed, 186 insertions(+)
diff --git a/Documentation/devicetree/bindings/ptp/qcom,nord-tscss.yaml b/Documentation/devicetree/bindings/ptp/qcom,nord-tscss.yaml
new file mode 100644
index 000000000000..9d49e66a35c9
--- /dev/null
+++ b/Documentation/devicetree/bindings/ptp/qcom,nord-tscss.yaml
@@ -0,0 +1,186 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ptp/qcom,nord-tscss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Timestamp Counter Subsystem (TSCSS) on Qualcomm Nord and Shikra
+
+maintainers:
+ - Imran Shaik <imran.shaik@oss.qualcomm.com>
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm TSCSS is a time synchronization subsystem composed of two main
+ blocks - the Timestamp Counter (TSC) and the Event Timestamp Unit (ETU).
+
+ The TSC block is a timestamp generator that maintains a running counter used
+ for system timekeeping, and is functional with just the AHB and counter
+ clocks.
+ The ETU block captures TSC timestamps for external hardware events. Each
+ ETU slice binds a slice number to an external event selector, and a
+ single summary interrupt is raised for any ETU slice event.
+
+ Nord additionally has a timer register region used to generate a
+ periodic pulse in sync with the TSC counter.
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,nord-tscss
+ - items:
+ - const: qcom,shikra-tscss
+ - const: qcom,nord-tscss
+
+ reg:
+ minItems: 1
+ maxItems: 3
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: tsc
+ - const: etu
+ - const: timer
+
+ clocks:
+ items:
+ - description: TSC AHB configuration clock.
+ - description: TSC global counter clock.
+ - description: TSC ETU clock.
+
+ clock-names:
+ items:
+ - const: ahb
+ - const: cntr
+ - const: etu
+
+ interrupts:
+ items:
+ - description:
+ Summary interrupt raised based on an external event for any
+ of the ETU slices.
+
+ interrupt-names:
+ items:
+ - const: etu_summary
+
+ pinctrl-names:
+ minItems: 1
+ maxItems: 32
+ items:
+ pattern: "^slice[0-9]+$"
+
+ qcom,etu-slice:
+ description:
+ ETU slice number for each entry in pinctrl-<n>, pinctrl-names and
+ qcom,etu-event-sel.
+ minItems: 1
+ maxItems: 32
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ qcom,etu-event-sel:
+ description:
+ External event selection value for each ETU slice listed in
+ qcom,etu-slice.
+ minItems: 1
+ maxItems: 32
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ reg-names:
+ contains:
+ const: etu
+ then:
+ required:
+ - interrupts
+ - interrupt-names
+ - pinctrl-names
+ - qcom,etu-slice
+ - qcom,etu-event-sel
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,shikra-tscss
+ then:
+ properties:
+ reg-names:
+ minItems: 1
+ items:
+ - const: tsc
+ - const: etu
+ pinctrl-names:
+ maxItems: 8
+ qcom,etu-slice:
+ maxItems: 8
+ qcom,etu-event-sel:
+ maxItems: 8
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ptp@1c80000 {
+ compatible = "qcom,nord-tscss";
+ reg = <0x0 0x01c80000 0x0 0x2000>;
+ reg-names = "tsc";
+
+ clocks = <&gcc_tscss_ahb_clk>,
+ <&gcc_tscss_cntr_clk>,
+ <&gcc_tscss_etu_clk>;
+ clock-names = "ahb", "cntr", "etu";
+
+ assigned-clocks = <&gcc_tscss_cntr_clk>;
+ assigned-clock-rates = <250000000>;
+ };
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ptp@1c80000 {
+ compatible = "qcom,nord-tscss";
+ reg = <0x0 0x01c80000 0x0 0x2000>,
+ <0x0 0x01ca0000 0x0 0x20000>,
+ <0x0 0x01c87000 0x0 0x1000>;
+ reg-names = "tsc", "etu", "timer";
+
+ clocks = <&gcc_tscss_ahb_clk>,
+ <&gcc_tscss_cntr_clk>,
+ <&gcc_tscss_etu_clk>;
+ clock-names = "ahb", "cntr", "etu";
+
+ assigned-clocks = <&gcc_tscss_cntr_clk>;
+ assigned-clock-rates = <250000000>;
+
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "etu_summary";
+
+ pinctrl-0 = <&cci_timer0>;
+ pinctrl-1 = <&cci_timer1>;
+ pinctrl-names = "slice1", "slice2";
+
+ qcom,etu-slice = <1 2>;
+ qcom,etu-event-sel = <1 2>;
+ };
+ };
+...
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 03/10] dt-bindings: ptp: Document TSCSS hardware on Qualcomm Nord and Shikra SoCs
2026-11-08 13:18 ` [PATCH v2 03/10] dt-bindings: ptp: Document TSCSS hardware on Qualcomm Nord and Shikra SoCs Imran Shaik
@ 2026-11-09 12:51 ` Krzysztof Kozlowski
2026-11-09 13:19 ` sashiko-bot
1 sibling, 0 replies; 24+ messages in thread
From: Krzysztof Kozlowski @ 2026-11-09 12:51 UTC (permalink / raw)
To: Imran Shaik
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev
On Sun, Nov 08, 2026 at 06:48:24PM +0530, Imran Shaik wrote:
> + interrupt-names:
> + items:
> + - const: etu_summary
> +
> + pinctrl-names:
> + minItems: 1
> + maxItems: 32
So here there is difference, that justifies different binding file.
> + items:
> + pattern: "^slice[0-9]+$"
> +
> + qcom,etu-slice:
> + description:
> + ETU slice number for each entry in pinctrl-<n>, pinctrl-names and
> + qcom,etu-event-sel.
> + minItems: 1
> + maxItems: 32
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> +
> + qcom,etu-event-sel:
Anyway, you need common schema defining qcom,etu-slice and
qcom,etu-event-sel properties. Maybe also pinctrl-names and other common
properties. The individual device schemas should only override/narrow
constraints
> + description:
> + External event selection value for each ETU slice listed in
> + qcom,etu-slice.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 03/10] dt-bindings: ptp: Document TSCSS hardware on Qualcomm Nord and Shikra SoCs
2026-11-08 13:18 ` [PATCH v2 03/10] dt-bindings: ptp: Document TSCSS hardware on Qualcomm Nord and Shikra SoCs Imran Shaik
2026-11-09 12:51 ` Krzysztof Kozlowski
@ 2026-11-09 13:19 ` sashiko-bot
1 sibling, 0 replies; 24+ messages in thread
From: sashiko-bot @ 2026-11-09 13:19 UTC (permalink / raw)
To: Imran Shaik; +Cc: devicetree, robh, conor+dt
Thank you for your contribution! Sashiko AI review found 2 potential
issues to consider:
- [Low] dt-bindings: ptp: qcom,nord-tscss: missing reg constraints in
allOf
- [Low] dt-bindings: ptp: qcom,nord-tscss: invalid fallback and variant
split
--
commit cdeb0d9b5fccebd2b2b765c9fc60dd95752de832
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>
dt-bindings: ptp: Document TSCSS hardware on Qualcomm Nord and Shikra SoCs
This commit adds the devicetree binding schema for the Timestamp Counter
Subsystem (TSCSS) on Qualcomm Nord and Shikra SoCs.
> diff --git a/Documentation/devicetree/bindings/ptp/qcom,nord-tscss.yaml b/Documentation/devicetree/bindings/ptp/qcom,nord-tscss.yaml
> new file mode 100644
> index 0000000000000..9d49e66a35c98
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ptp/qcom,nord-tscss.yaml
[ ... ]
> +properties:
> + compatible:
> + oneOf:
> + - const: qcom,nord-tscss
> + - items:
> + - const: qcom,shikra-tscss
> + - const: qcom,nord-tscss
> +
> + reg:
> + minItems: 1
> + maxItems: 3
> +
> + reg-names:
> + minItems: 1
> + items:
> + - const: tsc
> + - const: etu
> + - const: timer
[ ... ]
> +allOf:
> + - if:
> + properties:
> + reg-names:
> + contains:
> + const: etu
> + then:
> + required:
> + - interrupts
> + - interrupt-names
> + - pinctrl-names
> + - qcom,etu-slice
> + - qcom,etu-event-sel
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: qcom,shikra-tscss
> + then:
> + properties:
> + reg-names:
> + minItems: 1
> + items:
> + - const: tsc
> + - const: etu
> + pinctrl-names:
> + maxItems: 8
> + qcom,etu-slice:
> + maxItems: 8
> + qcom,etu-event-sel:
> + maxItems: 8
[Severity: Low]
Should these allOf conditionals also constrain reg to match reg-names?
When reg-names contains etu, reg is not given minItems: 2, so a node with
a single reg entry still passes validation. Similarly, the
qcom,shikra-tscss branch restricts reg-names to tsc and etu without
setting maxItems: 2 on reg (and redefines the items list instead of setting
maxItems: 2 on reg-names), allowing 3 reg entries on Shikra.
[Severity: Low]
Is qcom,nord-tscss a valid fallback compatible for qcom,shikra-tscss?
Nord has a timer register region and up to 32 ETU slices, whereas Shikra
lacks the timer region and only supports 8 slices, so a Shikra device is a
subset rather than backwards-compatible with Nord. Combining them also
requires per-compatible overrides for reg-names, pinctrl-names,
qcom,etu-slice, and qcom,etu-event-sel; should qcom,shikra-tscss be split
or grouped with a matching 2-region TSCSS schema instead of falling back to
qcom,nord-tscss?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261108-tscss-v2-0-d5f575010427@oss.qualcomm.com?part=3
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 04/10] ptp: qcom: Add PTP driver for the Qualcomm TSC hardware
2026-11-08 13:18 [PATCH v2 00/10] Add support for Qualcomm TSCSS hardware Imran Shaik
` (2 preceding siblings ...)
2026-11-08 13:18 ` [PATCH v2 03/10] dt-bindings: ptp: Document TSCSS hardware on Qualcomm Nord and Shikra SoCs Imran Shaik
@ 2026-11-08 13:18 ` Imran Shaik
2026-11-09 13:19 ` sashiko-bot
2026-11-08 13:18 ` [PATCH v2 05/10] arm64: defconfig: Enable Qualcomm TSC driver Imran Shaik
` (5 subsequent siblings)
9 siblings, 1 reply; 24+ messages in thread
From: Imran Shaik @ 2026-11-08 13:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Eric Dumazet
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev, Imran Shaik
Add a PTP Hardware Clock driver for the Qualcomm Timestamp Counter (TSC)
hardware found on Qualcomm SA8775P, QDU1000 and Nord SoCs. The TSC is a
free running hardware counter used for time synchronization, clocked by
an AHB configuration clock and a global counter clock, with the counter
resolution varying across SoCs.
Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
drivers/ptp/Kconfig | 11 +
drivers/ptp/Makefile | 1 +
drivers/ptp/ptp_qcom_tsc.c | 598 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 610 insertions(+)
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index feb50f8cc406..91bc347b2c50 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -264,4 +264,15 @@ config PTP_NETC_V4_TIMER
synchronization. It also supports periodic output signal (e.g. PPS)
and external trigger timestamping.
+config PTP_QCOM_TSC
+ tristate "Qualcomm TSC as PTP clock"
+ depends on ARCH_QCOM || COMPILE_TEST
+ depends on COMMON_CLK && PTP_1588_CLOCK
+ help
+ This driver adds support for using the Qualcomm Timestamp Counter
+ Subsystem (TSCSS) as a PTP clock.
+
+ To compile this driver as a module, choose M here: the module
+ will be called ptp_qcom_tsc.
+
endmenu
diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
index bdc47e284f14..ff029323e98f 100644
--- a/drivers/ptp/Makefile
+++ b/drivers/ptp/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_PTP_1588_CLOCK_OCP) += ptp_ocp.o
obj-$(CONFIG_PTP_DFL_TOD) += ptp_dfl_tod.o
obj-$(CONFIG_PTP_S390) += ptp_s390.o
obj-$(CONFIG_PTP_NETC_V4_TIMER) += ptp_netc.o
+obj-$(CONFIG_PTP_QCOM_TSC) += ptp_qcom_tsc.o
diff --git a/drivers/ptp/ptp_qcom_tsc.c b/drivers/ptp/ptp_qcom_tsc.c
new file mode 100644
index 000000000000..82ddbdd63389
--- /dev/null
+++ b/drivers/ptp/ptp_qcom_tsc.c
@@ -0,0 +1,598 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/ptp_clock_kernel.h>
+#include <linux/platform_device.h>
+
+#define ROLLOVER_VAL 999999999
+#define NSEC_SHIFT 32
+#define PULSE_WIDTH_MASK GENMASK(7, 6)
+#define DRIFT_MAX_RES 0x1FFFF
+#define DRIFT_JUMP_SWALLOW BIT(31)
+#define DRIFT_PERIOD_MASK GENMASK(28, 12)
+#define DRIFT_SUBPERIOD_MASK GENMASK(11, 0)
+#define DRIFT_INTERVAL_US 10
+#define DRIFT_MIN_TIMEOUT_US 5000
+
+#define DRIFT_TIMEOUT_US(period, subperiod, cntr_res) \
+ max_t(u64, div_u64((u64)(period) * (subperiod) * (cntr_res), NSEC_PER_USEC), \
+ DRIFT_MIN_TIMEOUT_US)
+
+/* Dynamic (continuous) drift correction, used on Nord/Shikra */
+#define DRIFT_STATUS BIT(1)
+#define DRIFT_DYNAMIC_EN BIT(2)
+#define DYNAMIC_DRIFT_SUBPERIOD_MASK GENMASK(27, 0)
+#define DYNAMIC_DRIFT_MIN_SUBPERIOD 6
+#define DYNAMIC_DRIFT_INCR_VAL 8
+#define DYNAMIC_DRIFT_POLL_US 10
+#define DYNAMIC_DRIFT_DISABLE_TIMEOUT_US 1000
+
+struct qcom_tsc_regs {
+ u32 control_cntcr;
+ u32 control_cntcv_lo;
+ u32 control_cntcv_hi;
+ u32 drift_correct_incr_val;
+ u32 drift_correct_duration;
+ u32 drift_correct_cmd;
+ u32 drift_correct_duration_2;
+ u32 drift_correct_cmd_2;
+ u32 rollover_val;
+ u32 offset_lo;
+ u32 offset_hi;
+ u32 read_cntcv_lo;
+ u32 read_cntcv_hi;
+};
+
+/**
+ * struct qcom_tsc_soc_data - SoC specific TSC hardware capabilities
+ *
+ * @rollover: indicates the counter uses sec/nsec split
+ * @offset_correction: hardware supports one-shot offset correction
+ * @dynamic_drift_correction: hardware supports continuous drift correction,
+ * instead of a one-shot jump/swallow correction
+ * @pulse_width: valid pulse width in cycles for drift correction
+ * @cntr_res: TSC counter resolution in nsec
+ * @reg_layout: register layout for this SoC/version
+ */
+struct qcom_tsc_soc_data {
+ bool rollover;
+ bool offset_correction;
+ bool dynamic_drift_correction;
+ int pulse_width;
+ int cntr_res;
+ const struct qcom_tsc_regs *reg_layout;
+};
+
+struct qcom_tsc {
+ struct device *dev;
+ void __iomem *base;
+ const struct qcom_tsc_soc_data *soc;
+ struct clk *ahb_clk;
+ struct clk *cntr_clk;
+ bool clocks_enabled;
+ struct ptp_clock *ptp;
+ struct ptp_clock_info ptp_info;
+ /* Mutex to protect operations from being interrupted */
+ struct mutex lock;
+};
+
+static bool qcom_tsc_is_enabled(struct qcom_tsc *tsc)
+{
+ const struct qcom_tsc_regs *regs = tsc->soc->reg_layout;
+
+ return readl_relaxed(tsc->base + regs->control_cntcr) & BIT(0);
+}
+
+static int qcom_tsc_read_time(struct qcom_tsc *tsc, struct timespec64 *ts)
+{
+ const struct qcom_tsc_regs *regs = tsc->soc->reg_layout;
+ u32 hi, lo;
+
+ if (!qcom_tsc_is_enabled(tsc))
+ return -EINVAL;
+
+ hi = readl_relaxed(tsc->base + regs->read_cntcv_hi);
+ lo = readl_relaxed(tsc->base + regs->read_cntcv_lo);
+
+ if (tsc->soc->rollover) {
+ ts->tv_sec = hi;
+ ts->tv_nsec = lo;
+ } else {
+ u64 ns = ((u64)hi << NSEC_SHIFT) | lo;
+
+ *ts = ns_to_timespec64(ns);
+ }
+
+ return 0;
+}
+
+static int qcom_tsc_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
+{
+ struct qcom_tsc *tsc = container_of(ptp, struct qcom_tsc, ptp_info);
+ int ret;
+
+ mutex_lock(&tsc->lock);
+
+ if (!tsc->clocks_enabled) {
+ mutex_unlock(&tsc->lock);
+ return -EINVAL;
+ }
+
+ ret = qcom_tsc_read_time(tsc, ts);
+ mutex_unlock(&tsc->lock);
+
+ return ret;
+}
+
+static void qcom_tsc_split_ts(struct qcom_tsc *tsc, struct timespec64 ts, u32 *hi, u32 *lo)
+{
+ if (tsc->soc->rollover) {
+ *hi = ts.tv_sec;
+ *lo = ts.tv_nsec;
+ } else {
+ u64 ns = timespec64_to_ns(&ts);
+
+ *lo = lower_32_bits(ns);
+ *hi = upper_32_bits(ns);
+ }
+}
+
+static void qcom_tsc_clk_disable(void *data)
+{
+ clk_disable_unprepare(data);
+}
+
+static int qcom_tsc_enable_clocks(struct qcom_tsc *tsc)
+{
+ int ret;
+
+ if (tsc->clocks_enabled)
+ return 0;
+
+ ret = clk_prepare_enable(tsc->ahb_clk);
+ if (ret)
+ return ret;
+
+ ret = devm_add_action_or_reset(tsc->dev, qcom_tsc_clk_disable, tsc->ahb_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(tsc->cntr_clk);
+ if (ret)
+ return ret;
+
+ ret = devm_add_action_or_reset(tsc->dev, qcom_tsc_clk_disable, tsc->cntr_clk);
+ if (ret)
+ return ret;
+
+ tsc->clocks_enabled = true;
+
+ return 0;
+}
+
+static int qcom_tsc_update_counter(struct qcom_tsc *tsc, struct timespec64 ts)
+{
+ const struct qcom_tsc_regs *regs = tsc->soc->reg_layout;
+ u32 regval, hi, lo;
+
+ qcom_tsc_split_ts(tsc, ts, &hi, &lo);
+
+ writel_relaxed(lo, tsc->base + regs->control_cntcv_lo);
+ writel_relaxed(hi, tsc->base + regs->control_cntcv_hi);
+
+ regval = readl_relaxed(tsc->base + regs->control_cntcr);
+ regval |= BIT(0);
+ writel_relaxed(regval, tsc->base + regs->control_cntcr);
+
+ return 0;
+}
+
+static int qcom_tsc_update_offset(struct qcom_tsc *tsc, const struct timespec64 ts)
+{
+ const struct qcom_tsc_regs *regs = tsc->soc->reg_layout;
+ struct timespec64 tod;
+ u32 regval, hi, lo;
+ int ret;
+
+ if (tsc->soc->offset_correction) {
+ qcom_tsc_split_ts(tsc, ts, &hi, &lo);
+
+ writel_relaxed(lo, tsc->base + regs->offset_lo);
+ writel_relaxed(hi, tsc->base + regs->offset_hi);
+
+ return 0;
+ }
+
+ /*
+ * No hardware offset correction support: disable and reload the
+ * counter with the corrected time, as recommended by the hardware
+ * design team.
+ */
+ ret = qcom_tsc_read_time(tsc, &tod);
+ if (ret)
+ return ret;
+
+ regval = readl_relaxed(tsc->base + regs->control_cntcr);
+ regval &= ~BIT(0);
+ writel_relaxed(regval, tsc->base + regs->control_cntcr);
+
+ return qcom_tsc_update_counter(tsc, timespec64_add(tod, ts));
+}
+
+static int qcom_tsc_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts)
+{
+ struct qcom_tsc *tsc = container_of(ptp, struct qcom_tsc, ptp_info);
+ const struct qcom_tsc_regs *regs = tsc->soc->reg_layout;
+ struct timespec64 tod;
+ u32 regval;
+ int ret;
+
+ mutex_lock(&tsc->lock);
+
+ ret = qcom_tsc_enable_clocks(tsc);
+ if (ret) {
+ mutex_unlock(&tsc->lock);
+ return ret;
+ }
+
+ if (qcom_tsc_is_enabled(tsc)) {
+ qcom_tsc_read_time(tsc, &tod);
+ ret = qcom_tsc_update_offset(tsc, timespec64_sub(*ts, tod));
+ mutex_unlock(&tsc->lock);
+ return ret;
+ }
+
+ /* Configure and enable the TSC counter */
+ regval = readl_relaxed(tsc->base + regs->control_cntcr);
+ regval &= ~PULSE_WIDTH_MASK;
+ regval |= FIELD_PREP(PULSE_WIDTH_MASK, tsc->soc->pulse_width);
+ writel_relaxed(regval, tsc->base + regs->control_cntcr);
+
+ if (tsc->soc->rollover)
+ writel_relaxed(ROLLOVER_VAL, tsc->base + regs->rollover_val);
+
+ ret = qcom_tsc_update_counter(tsc, *ts);
+ mutex_unlock(&tsc->lock);
+
+ return ret;
+}
+
+static int qcom_tsc_adjtime(struct ptp_clock_info *ptp, s64 delta)
+{
+ struct qcom_tsc *tsc = container_of(ptp, struct qcom_tsc, ptp_info);
+ int ret;
+
+ mutex_lock(&tsc->lock);
+
+ if (!tsc->clocks_enabled) {
+ mutex_unlock(&tsc->lock);
+ return -EINVAL;
+ }
+
+ ret = qcom_tsc_update_offset(tsc, ns_to_timespec64(delta));
+ mutex_unlock(&tsc->lock);
+
+ return ret;
+}
+
+static int qcom_tsc_drift_correction(struct qcom_tsc *tsc, long scaled_ppm)
+{
+ const struct qcom_tsc_soc_data *soc = tsc->soc;
+ const struct qcom_tsc_regs *regs = soc->reg_layout;
+ long ppb = scaled_ppm_to_ppb(scaled_ppm);
+ u64 period, incval = 0;
+ u32 regval = 0, subperiod;
+
+ if (ppb == 0)
+ return 0;
+
+ if (ppb < 0) {
+ ppb = -ppb;
+ regval &= ~DRIFT_JUMP_SWALLOW;
+
+ period = div_u64(ppb, soc->cntr_res);
+ if (period >= DRIFT_MAX_RES)
+ period = DRIFT_MAX_RES;
+ } else {
+ regval |= DRIFT_JUMP_SWALLOW;
+
+ period = div_u64(ppb, soc->cntr_res);
+ if (period >= DRIFT_MAX_RES) {
+ period = DRIFT_MAX_RES;
+ incval = soc->cntr_res * 2;
+ } else if (ppb < soc->cntr_res) {
+ incval = soc->cntr_res + ppb;
+ period = 1;
+ } else {
+ incval = soc->cntr_res * 2;
+ }
+ }
+
+ subperiod = soc->pulse_width * 2;
+ regval |= FIELD_PREP(DRIFT_SUBPERIOD_MASK, subperiod);
+ regval |= FIELD_PREP(DRIFT_PERIOD_MASK, period);
+
+ /* Update jump/swallow, period, subperiod */
+ writel_relaxed(regval, tsc->base + regs->drift_correct_duration);
+
+ writel_relaxed(incval, tsc->base + regs->drift_correct_incr_val);
+
+ /* Trigger the drift correction */
+ regval = readl_relaxed(tsc->base + regs->drift_correct_cmd);
+ regval |= BIT(0);
+ writel_relaxed(regval, tsc->base + regs->drift_correct_cmd);
+
+ return readl_poll_timeout(tsc->base + regs->drift_correct_cmd, regval,
+ !(regval & BIT(1)), DRIFT_INTERVAL_US,
+ DRIFT_TIMEOUT_US(period, subperiod, soc->cntr_res));
+}
+
+static bool qcom_tsc_dynamic_drift_type_matches(u32 duration, bool neg_adj)
+{
+ return !(duration & DRIFT_JUMP_SWALLOW) == neg_adj;
+}
+
+static void qcom_tsc_set_dynamic_drift_enable(struct qcom_tsc *tsc, u32 cmd, bool enable)
+{
+ const struct qcom_tsc_regs *regs = tsc->soc->reg_layout;
+
+ if (enable)
+ cmd |= DRIFT_DYNAMIC_EN;
+ else
+ cmd &= ~DRIFT_DYNAMIC_EN;
+
+ writel_relaxed(cmd, tsc->base + regs->drift_correct_cmd);
+}
+
+static int qcom_tsc_disable_dynamic_drift(struct qcom_tsc *tsc, u32 cmd)
+{
+ const struct qcom_tsc_regs *regs = tsc->soc->reg_layout;
+
+ qcom_tsc_set_dynamic_drift_enable(tsc, cmd, false);
+
+ return readl_poll_timeout(tsc->base + regs->drift_correct_cmd, cmd,
+ !(cmd & DRIFT_STATUS), DYNAMIC_DRIFT_POLL_US,
+ DYNAMIC_DRIFT_DISABLE_TIMEOUT_US);
+}
+
+static void qcom_tsc_program_dynamic_drift(struct qcom_tsc *tsc, u32 duration,
+ bool neg_adj, u32 subperiod)
+{
+ const struct qcom_tsc_regs *regs = tsc->soc->reg_layout;
+
+ if (neg_adj)
+ duration &= ~DRIFT_JUMP_SWALLOW;
+ else
+ duration |= DRIFT_JUMP_SWALLOW;
+
+ writel_relaxed(duration, tsc->base + regs->drift_correct_duration);
+ writel_relaxed(DYNAMIC_DRIFT_INCR_VAL, tsc->base + regs->drift_correct_incr_val);
+ writel_relaxed(FIELD_PREP(DYNAMIC_DRIFT_SUBPERIOD_MASK, subperiod),
+ tsc->base + regs->drift_correct_duration_2);
+}
+
+/*
+ * Unlike qcom_tsc_drift_correction()'s one-shot jump/swallow correction,
+ * hardware supporting dynamic drift correction keeps the correction
+ * continuously active across adjfine() calls. The subperiod can be updated
+ * in place while active, as long as the correction direction (jump vs
+ * swallow) is unchanged; otherwise the correction must be disabled and
+ * reprogrammed before being re-enabled.
+ */
+static int qcom_tsc_dynamic_drift_correction(struct qcom_tsc *tsc, long scaled_ppm)
+{
+ const struct qcom_tsc_regs *regs = tsc->soc->reg_layout;
+ long ppb = scaled_ppm_to_ppb(scaled_ppm);
+ bool neg_adj = ppb < 0;
+ u32 duration, cmd, subperiod;
+ int ret;
+
+ if (neg_adj)
+ ppb = -ppb;
+
+ cmd = readl_relaxed(tsc->base + regs->drift_correct_cmd);
+
+ if (ppb == 0) {
+ if (cmd & DRIFT_STATUS)
+ return qcom_tsc_disable_dynamic_drift(tsc, cmd);
+
+ return 0;
+ }
+
+ subperiod = NSEC_PER_SEC / ppb;
+ subperiod = clamp_val(subperiod, DYNAMIC_DRIFT_MIN_SUBPERIOD, DYNAMIC_DRIFT_SUBPERIOD_MASK);
+
+ duration = readl_relaxed(tsc->base + regs->drift_correct_duration);
+
+ if ((cmd & DRIFT_STATUS) && qcom_tsc_dynamic_drift_type_matches(duration, neg_adj)) {
+ writel_relaxed(FIELD_PREP(DYNAMIC_DRIFT_SUBPERIOD_MASK, subperiod),
+ tsc->base + regs->drift_correct_duration_2);
+ return 0;
+ }
+
+ if (cmd & DRIFT_STATUS) {
+ ret = qcom_tsc_disable_dynamic_drift(tsc, cmd);
+ if (ret)
+ return ret;
+
+ cmd = readl_relaxed(tsc->base + regs->drift_correct_cmd);
+ }
+
+ qcom_tsc_program_dynamic_drift(tsc, duration, neg_adj, subperiod);
+ qcom_tsc_set_dynamic_drift_enable(tsc, cmd, true);
+
+ return 0;
+}
+
+static int qcom_tsc_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
+{
+ struct qcom_tsc *tsc = container_of(ptp, struct qcom_tsc, ptp_info);
+ int ret;
+
+ mutex_lock(&tsc->lock);
+
+ if (!tsc->clocks_enabled) {
+ mutex_unlock(&tsc->lock);
+ return -EINVAL;
+ }
+
+ if (tsc->soc->dynamic_drift_correction)
+ ret = qcom_tsc_dynamic_drift_correction(tsc, scaled_ppm);
+ else
+ ret = qcom_tsc_drift_correction(tsc, scaled_ppm);
+ mutex_unlock(&tsc->lock);
+
+ return ret;
+}
+
+static struct ptp_clock_info qcom_ptp_info = {
+ .owner = THIS_MODULE,
+ .name = "PTP_QCOM_TSC",
+ .max_adj = 9999999,
+ .adjfine = qcom_tsc_adjfine,
+ .adjtime = qcom_tsc_adjtime,
+ .gettime64 = qcom_tsc_gettime,
+ .settime64 = qcom_tsc_settime,
+};
+
+static const struct qcom_tsc_regs qcom_tsc_layout = {
+ .control_cntcr = 0x0,
+ .control_cntcv_lo = 0x8,
+ .control_cntcv_hi = 0xc,
+ .drift_correct_incr_val = 0x2c,
+ .drift_correct_duration = 0x30,
+ .drift_correct_cmd = 0x34,
+ .rollover_val = 0x3c,
+ .offset_lo = 0x50,
+ .offset_hi = 0x54,
+ .read_cntcv_lo = 0x1000,
+ .read_cntcv_hi = 0x1004,
+};
+
+static const struct qcom_tsc_regs qcom_tsc_layout_v2 = {
+ .control_cntcr = 0x0,
+ .control_cntcv_lo = 0x8,
+ .control_cntcv_hi = 0xc,
+ .drift_correct_incr_val = 0x2c,
+ .drift_correct_duration = 0x30,
+ .drift_correct_duration_2 = 0x34,
+ .drift_correct_cmd = 0x38,
+ .drift_correct_cmd_2 = 0x3c,
+ .rollover_val = 0x44,
+ .offset_lo = 0x50,
+ .offset_hi = 0x54,
+ .read_cntcv_lo = 0x1000,
+ .read_cntcv_hi = 0x1004,
+};
+
+static const struct qcom_tsc_soc_data qcom_tsc_sa8775p = {
+ .reg_layout = &qcom_tsc_layout,
+ .rollover = false,
+ .offset_correction = false,
+ .pulse_width = 2,
+ .cntr_res = 64,
+};
+
+static const struct qcom_tsc_soc_data qcom_tsc_qdu1000 = {
+ .reg_layout = &qcom_tsc_layout,
+ .rollover = true,
+ .offset_correction = true,
+ .pulse_width = 3,
+ .cntr_res = 2,
+};
+
+static const struct qcom_tsc_soc_data qcom_tsc_nord = {
+ .reg_layout = &qcom_tsc_layout_v2,
+ .rollover = false,
+ .offset_correction = true,
+ .dynamic_drift_correction = true,
+ .pulse_width = 3,
+ .cntr_res = 4,
+};
+
+static const struct of_device_id qcom_tsc_of_match[] = {
+ { .compatible = "qcom,sa8775p-tscss", .data = &qcom_tsc_sa8775p },
+ { .compatible = "qcom,qdu1000-tscss", .data = &qcom_tsc_qdu1000 },
+ { .compatible = "qcom,nord-tscss", .data = &qcom_tsc_nord },
+ { }
+};
+MODULE_DEVICE_TABLE(of, qcom_tsc_of_match);
+
+static int qcom_ptp_tsc_probe(struct platform_device *pdev)
+{
+ const struct qcom_tsc_soc_data *soc;
+ struct qcom_tsc *tsc;
+ int ret;
+
+ soc = of_device_get_match_data(&pdev->dev);
+ if (!soc)
+ return -ENODEV;
+
+ tsc = devm_kzalloc(&pdev->dev, sizeof(*tsc), GFP_KERNEL);
+ if (!tsc)
+ return -ENOMEM;
+
+ tsc->dev = &pdev->dev;
+ tsc->soc = soc;
+
+ ret = devm_mutex_init(&pdev->dev, &tsc->lock);
+ if (ret)
+ return ret;
+
+ tsc->base = devm_platform_ioremap_resource_byname(pdev, "tsc");
+ if (IS_ERR(tsc->base))
+ return PTR_ERR(tsc->base);
+
+ /* Both clocks are enabled on first use, when the counter is set */
+ tsc->ahb_clk = devm_clk_get(&pdev->dev, "ahb");
+ if (IS_ERR(tsc->ahb_clk))
+ return PTR_ERR(tsc->ahb_clk);
+
+ tsc->cntr_clk = devm_clk_get(&pdev->dev, "cntr");
+ if (IS_ERR(tsc->cntr_clk))
+ return PTR_ERR(tsc->cntr_clk);
+
+ tsc->ptp_info = qcom_ptp_info;
+
+ tsc->ptp = ptp_clock_register(&tsc->ptp_info, &pdev->dev);
+ if (IS_ERR(tsc->ptp))
+ return dev_err_probe(&pdev->dev, PTR_ERR(tsc->ptp),
+ "Failed to register ptp clock\n");
+
+ platform_set_drvdata(pdev, tsc);
+
+ return 0;
+}
+
+static void qcom_ptp_tsc_remove(struct platform_device *pdev)
+{
+ struct qcom_tsc *tsc = platform_get_drvdata(pdev);
+
+ if (tsc && tsc->ptp) {
+ ptp_clock_unregister(tsc->ptp);
+ tsc->ptp = NULL;
+ }
+}
+
+static struct platform_driver qcom_ptp_tsc_driver = {
+ .probe = qcom_ptp_tsc_probe,
+ .remove = qcom_ptp_tsc_remove,
+ .driver = {
+ .name = "qcom_ptp_tsc",
+ .of_match_table = qcom_tsc_of_match,
+ },
+};
+module_platform_driver(qcom_ptp_tsc_driver);
+
+MODULE_DESCRIPTION("PTP QCOM TSC driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 04/10] ptp: qcom: Add PTP driver for the Qualcomm TSC hardware
2026-11-08 13:18 ` [PATCH v2 04/10] ptp: qcom: Add PTP driver for the Qualcomm TSC hardware Imran Shaik
@ 2026-11-09 13:19 ` sashiko-bot
0 siblings, 0 replies; 24+ messages in thread
From: sashiko-bot @ 2026-11-09 13:19 UTC (permalink / raw)
To: Imran Shaik; +Cc: devicetree, robh, conor+dt
Thank you for your contribution! Sashiko AI review found 4 potential
issues to consider:
- [High] ptp: qcom: torn 64-bit counter read in qcom_tsc_read_time() on
rollover
- [High] ptp: qcom: period truncated to 0 for small negative ppb in
adjfine()
- [Medium] ptp: qcom: ahb_clk and devres leak in
qcom_tsc_enable_clocks() on error
- [Medium] ptp: qcom: uninitialized clock at probe and skipped config in
qcom_tsc_settime()
--
commit 9c266c0baa9449c0c5ca7b1a7e003c4cbd0cb88b
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>
ptp: qcom: Add PTP driver for the Qualcomm TSC hardware
This commit adds a PTP Hardware Clock driver for the Qualcomm Timestamp
Counter (TSC) hardware on SA8775P, QDU1000, and Nord SoCs.
> diff --git a/drivers/ptp/ptp_qcom_tsc.c b/drivers/ptp/ptp_qcom_tsc.c
> new file mode 100644
> index 0000000000000..82ddbdd63389d
> --- /dev/null
> +++ b/drivers/ptp/ptp_qcom_tsc.c
> @@ -0,0 +1,598 @@
[ ... ]
> +static int qcom_tsc_read_time(struct qcom_tsc *tsc, struct timespec64 *ts)
> +{
> + const struct qcom_tsc_regs *regs = tsc->soc->reg_layout;
> + u32 hi, lo;
> +
> + if (!qcom_tsc_is_enabled(tsc))
> + return -EINVAL;
> +
> + hi = readl_relaxed(tsc->base + regs->read_cntcv_hi);
> + lo = readl_relaxed(tsc->base + regs->read_cntcv_lo);
[Severity: High]
Can read_cntcv_lo roll over between reading read_cntcv_hi and
read_cntcv_lo? If the lower word wraps between the two 32-bit reads, the
old upper word is paired with the post-rollover lower word, returning a
timestamp that jumps backward by 1 second (when rollover is true) or ~4.295
seconds (when rollover is false). Because qcom_tsc_settime() and
qcom_tsc_update_offset() call qcom_tsc_read_time() to compute the delta or
new counter value written back to the hardware, a torn read during
settime64() or adjtime() also permanently shifts the hardware clock.
Re-reading read_cntcv_hi in a loop until two consecutive upper-word reads
match would avoid this.
[ ... ]
> +static int qcom_tsc_enable_clocks(struct qcom_tsc *tsc)
> +{
> + int ret;
> +
> + if (tsc->clocks_enabled)
> + return 0;
> +
> + ret = clk_prepare_enable(tsc->ahb_clk);
> + if (ret)
> + return ret;
> +
> + ret = devm_add_action_or_reset(tsc->dev, qcom_tsc_clk_disable, tsc->ahb_clk);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(tsc->cntr_clk);
> + if (ret)
> + return ret;
> +
> + ret = devm_add_action_or_reset(tsc->dev, qcom_tsc_clk_disable, tsc->cntr_clk);
> + if (ret)
> + return ret;
> +
> + tsc->clocks_enabled = true;
> +
> + return 0;
> +}
[Severity: Medium]
If enabling tsc->cntr_clk or registering its devm action fails here, does
tsc->ahb_clk remain enabled with tsc->clocks_enabled still false? Because
qcom_tsc_enable_clocks() runs from the runtime .settime64 callback rather
than probe, returning an error does not unwind devres actions on tsc->dev,
and each subsequent qcom_tsc_settime() call will prepare_enable
tsc->ahb_clk and queue another devres action again.
[ ... ]
> +static int qcom_tsc_drift_correction(struct qcom_tsc *tsc, long scaled_ppm)
> +{
> + const struct qcom_tsc_soc_data *soc = tsc->soc;
> + const struct qcom_tsc_regs *regs = soc->reg_layout;
> + long ppb = scaled_ppm_to_ppb(scaled_ppm);
> + u64 period, incval = 0;
> + u32 regval = 0, subperiod;
> +
> + if (ppb == 0)
> + return 0;
> +
> + if (ppb < 0) {
> + ppb = -ppb;
> + regval &= ~DRIFT_JUMP_SWALLOW;
> +
> + period = div_u64(ppb, soc->cntr_res);
> + if (period >= DRIFT_MAX_RES)
> + period = DRIFT_MAX_RES;
> + } else {
> + regval |= DRIFT_JUMP_SWALLOW;
> +
> + period = div_u64(ppb, soc->cntr_res);
> + if (period >= DRIFT_MAX_RES) {
> + period = DRIFT_MAX_RES;
> + incval = soc->cntr_res * 2;
> + } else if (ppb < soc->cntr_res) {
> + incval = soc->cntr_res + ppb;
> + period = 1;
> + } else {
> + incval = soc->cntr_res * 2;
> + }
> + }
[Severity: High]
Does the negative ppb branch truncate period to 0 when 0 < -ppb <
soc->cntr_res (for example, -63 <= ppb <= -1 on SA8775P where cntr_res is
64)? Unlike the positive branch, which clamps period to 1 and adjusts
incval when ppb < soc->cntr_res, the negative branch leaves period = 0 and
incval = 0 and triggers drift_correct_cmd with a zero period, dropping fine
negative frequency adjustments during PTP synchronization.
[ ... ]
> +static int qcom_ptp_tsc_probe(struct platform_device *pdev)
> +{
[ ... ]
> + /* Both clocks are enabled on first use, when the counter is set */
> + tsc->ahb_clk = devm_clk_get(&pdev->dev, "ahb");
> + if (IS_ERR(tsc->ahb_clk))
> + return PTR_ERR(tsc->ahb_clk);
> +
> + tsc->cntr_clk = devm_clk_get(&pdev->dev, "cntr");
> + if (IS_ERR(tsc->cntr_clk))
> + return PTR_ERR(tsc->cntr_clk);
> +
> + tsc->ptp_info = qcom_ptp_info;
> +
> + tsc->ptp = ptp_clock_register(&tsc->ptp_info, &pdev->dev);
[Severity: Medium]
Should the clocks and hardware counter be initialized before
ptp_clock_register() exposes the PHC? Because tsc->clocks_enabled starts
as false and the counter is only enabled in qcom_tsc_settime(), any
gettime64(), adjtime(), adjfine(), or virtual clock creation
(n_vclocks_store() -> ptp_vclock_register()) fails with -EINVAL until
userspace calls clock_settime(). In addition, if BIT(0) in control_cntcr
is already set at probe (from firmware or a prior driver bind/unbind, since
qcom_ptp_tsc_remove() does not disable the counter), the first
qcom_tsc_settime() call sees qcom_tsc_is_enabled(tsc) == true and takes the
qcom_tsc_update_offset() path without programming PULSE_WIDTH_MASK or
ROLLOVER_VAL:
drivers/ptp/ptp_qcom_tsc.c:qcom_tsc_settime() {
...
if (qcom_tsc_is_enabled(tsc)) {
qcom_tsc_read_time(tsc, &tod);
ret = qcom_tsc_update_offset(tsc, timespec64_sub(*ts, tod));
mutex_unlock(&tsc->lock);
return ret;
}
/* Configure and enable the TSC counter */
regval = readl_relaxed(tsc->base + regs->control_cntcr);
regval &= ~PULSE_WIDTH_MASK;
regval |= FIELD_PREP(PULSE_WIDTH_MASK, tsc->soc->pulse_width);
writel_relaxed(regval, tsc->base + regs->control_cntcr);
if (tsc->soc->rollover)
writel_relaxed(ROLLOVER_VAL, tsc->base + regs->rollover_val);
...
}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261108-tscss-v2-0-d5f575010427@oss.qualcomm.com?part=4
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 05/10] arm64: defconfig: Enable Qualcomm TSC driver
2026-11-08 13:18 [PATCH v2 00/10] Add support for Qualcomm TSCSS hardware Imran Shaik
` (3 preceding siblings ...)
2026-11-08 13:18 ` [PATCH v2 04/10] ptp: qcom: Add PTP driver for the Qualcomm TSC hardware Imran Shaik
@ 2026-11-08 13:18 ` Imran Shaik
2026-11-08 13:18 ` [PATCH v2 06/10] arm64: dts: qcom: lemans: Add support for TSCSS node Imran Shaik
` (4 subsequent siblings)
9 siblings, 0 replies; 24+ messages in thread
From: Imran Shaik @ 2026-11-08 13:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Eric Dumazet
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev, Imran Shaik
Enable PTP_QCOM_TSC as a module to support the Timestamp Counter (TSC)
synchronization functionality on Qualcomm Lemans, Monaco and QDU1000
platforms.
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7b4985b29b21..9af55787b236 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -689,6 +689,7 @@ CONFIG_SPI_SPIDEV=m
CONFIG_SPMI=y
CONFIG_SPMI_APPLE=m
CONFIG_SPMI_MTK_PMIF=m
+CONFIG_PTP_QCOM_TSC=m
CONFIG_PINCTRL_APPLE_GPIO=m
CONFIG_PINCTRL_DA9062=m
CONFIG_PINCTRL_MAX77620=y
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 06/10] arm64: dts: qcom: lemans: Add support for TSCSS node
2026-11-08 13:18 [PATCH v2 00/10] Add support for Qualcomm TSCSS hardware Imran Shaik
` (4 preceding siblings ...)
2026-11-08 13:18 ` [PATCH v2 05/10] arm64: defconfig: Enable Qualcomm TSC driver Imran Shaik
@ 2026-11-08 13:18 ` Imran Shaik
2026-11-09 12:52 ` Krzysztof Kozlowski
2026-11-09 13:19 ` sashiko-bot
2026-11-08 13:18 ` [PATCH v2 07/10] arm64: dts: qcom: monaco: " Imran Shaik
` (3 subsequent siblings)
9 siblings, 2 replies; 24+ messages in thread
From: Imran Shaik @ 2026-11-08 13:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Eric Dumazet
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev, Imran Shaik
Add Timestamp Counter Subsystem (TSCSS) node support on Qualcomm Lemans
SoCs.
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 1fdb72fa5518..4c76c820cacb 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -3022,6 +3022,18 @@ pcie1_phy: phy@1c14000 {
status = "disabled";
};
+ ptp@1c80000 {
+ compatible = "qcom,sa8775p-tscss";
+ reg = <0x0 0x01c80000 0x0 0x2000>;
+ reg-names = "tsc";
+ clocks = <&gcc GCC_TSCSS_AHB_CLK>,
+ <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>,
+ <&gcc GCC_TSCSS_ETU_CLK>;
+ clock-names = "ahb", "cntr", "etu";
+ assigned-clocks = <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>;
+ assigned-clock-rates = <15625000>;
+ };
+
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 06/10] arm64: dts: qcom: lemans: Add support for TSCSS node
2026-11-08 13:18 ` [PATCH v2 06/10] arm64: dts: qcom: lemans: Add support for TSCSS node Imran Shaik
@ 2026-11-09 12:52 ` Krzysztof Kozlowski
2026-11-09 13:19 ` sashiko-bot
1 sibling, 0 replies; 24+ messages in thread
From: Krzysztof Kozlowski @ 2026-11-09 12:52 UTC (permalink / raw)
To: Imran Shaik
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev
On Sun, Nov 08, 2026 at 06:48:27PM +0530, Imran Shaik wrote:
> Add Timestamp Counter Subsystem (TSCSS) node support on Qualcomm Lemans
> SoCs.
>
> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/lemans.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 1fdb72fa5518..4c76c820cacb 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -3022,6 +3022,18 @@ pcie1_phy: phy@1c14000 {
> status = "disabled";
> };
>
> + ptp@1c80000 {
> + compatible = "qcom,sa8775p-tscss";
> + reg = <0x0 0x01c80000 0x0 0x2000>;
Where is the rest of PTP devices? Your binding clearly said there are
PTP with one and with two address spaces.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH v2 06/10] arm64: dts: qcom: lemans: Add support for TSCSS node
2026-11-08 13:18 ` [PATCH v2 06/10] arm64: dts: qcom: lemans: Add support for TSCSS node Imran Shaik
2026-11-09 12:52 ` Krzysztof Kozlowski
@ 2026-11-09 13:19 ` sashiko-bot
1 sibling, 0 replies; 24+ messages in thread
From: sashiko-bot @ 2026-11-09 13:19 UTC (permalink / raw)
To: Imran Shaik; +Cc: devicetree, robh, conor+dt
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] arm64: dts: qcom: lemans: missing CX power-domain and OPP in
ptp@1c80000
--
commit 75dd9885f6f6ae470214655cb90edbd903d34847
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>
arm64: dts: qcom: lemans: Add support for TSCSS node
This commit adds the Timestamp Counter Subsystem node to the Qualcomm
Lemans SoC devicetree.
> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 1fdb72fa55184..4c76c820cacb1 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -3022,6 +3022,18 @@ pcie1_phy: phy@1c14000 {
> status = "disabled";
> };
>
> + ptp@1c80000 {
> + compatible = "qcom,sa8775p-tscss";
> + reg = <0x0 0x01c80000 0x0 0x2000>;
> + reg-names = "tsc";
> + clocks = <&gcc GCC_TSCSS_AHB_CLK>,
> + <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>,
> + <&gcc GCC_TSCSS_ETU_CLK>;
> + clock-names = "ahb", "cntr", "etu";
> + assigned-clocks = <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>;
> + assigned-clock-rates = <15625000>;
> + };
[Severity: Medium]
As reported by Konrad Dybcio on v1 [1], does ptp@1c80000 need
power-domains = <&rpmhpd SA8775P_CX> and
required-opps = <&rpmhpd_opp_svs_l1>?
Running the counter clock at 15.625 MHz requires the rpmhpd_opp_svs_l1
performance state, and rpmhpd_opp_table defines rpmhpd_opp_min_svs,
rpmhpd_opp_low_svs, and rpmhpd_opp_svs below it. Once rpmhpd_sync_state()
completes, the CX power domain can drop to one of those lower corners when
other consumers vote lower levels or are idle, operating the counter clock
below its required voltage corner.
[1] https://lore.kernel.org/r/a93f11c5-d0cf-4acd-a959-53fecc996e5f@oss.qualcomm.com
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261108-tscss-v2-0-d5f575010427@oss.qualcomm.com?part=6
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 07/10] arm64: dts: qcom: monaco: Add support for TSCSS node
2026-11-08 13:18 [PATCH v2 00/10] Add support for Qualcomm TSCSS hardware Imran Shaik
` (5 preceding siblings ...)
2026-11-08 13:18 ` [PATCH v2 06/10] arm64: dts: qcom: lemans: Add support for TSCSS node Imran Shaik
@ 2026-11-08 13:18 ` Imran Shaik
2026-11-08 13:18 ` [PATCH v2 08/10] arm64: dts: qcom: qdu1000: " Imran Shaik
` (2 subsequent siblings)
9 siblings, 0 replies; 24+ messages in thread
From: Imran Shaik @ 2026-11-08 13:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Eric Dumazet
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev, Imran Shaik
Add Timestamp Counter Subsystem (TSCSS) node support on Qualcomm Monaco
SoCs.
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/monaco.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 35fbee63d4c6..b87ba4b3a5a6 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -2628,6 +2628,18 @@ pcie1_phy: phy@1c14000 {
status = "disabled";
};
+ ptp@1c80000 {
+ compatible = "qcom,qcs8300-tscss", "qcom,sa8775p-tscss";
+ reg = <0x0 0x01c80000 0x0 0x2000>;
+ reg-names = "tsc";
+ clocks = <&gcc GCC_TSCSS_AHB_CLK>,
+ <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>,
+ <&gcc GCC_TSCSS_ETU_CLK>;
+ clock-names = "ahb", "cntr", "etu";
+ assigned-clocks = <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>;
+ assigned-clock-rates = <15625000>;
+ };
+
ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 08/10] arm64: dts: qcom: qdu1000: Add support for TSCSS node
2026-11-08 13:18 [PATCH v2 00/10] Add support for Qualcomm TSCSS hardware Imran Shaik
` (6 preceding siblings ...)
2026-11-08 13:18 ` [PATCH v2 07/10] arm64: dts: qcom: monaco: " Imran Shaik
@ 2026-11-08 13:18 ` Imran Shaik
2026-11-09 12:52 ` Krzysztof Kozlowski
2026-11-08 13:18 ` [PATCH v2 09/10] arm64: dts: qcom: shikra: " Imran Shaik
2026-11-08 13:18 ` [PATCH v2 10/10] arm64: dts: qcom: nord: " Imran Shaik
9 siblings, 1 reply; 24+ messages in thread
From: Imran Shaik @ 2026-11-08 13:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Eric Dumazet
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev, Imran Shaik
Add Timestamp Counter Subsystem (TSCSS) node support on Qualcomm QDU1000
SoCs.
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index 3a25b5100836..0f4028c41b2f 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -877,6 +877,19 @@ system_noc: interconnect@1640000 {
#interconnect-cells = <2>;
};
+ ptp@1da0000 {
+ compatible = "qcom,qdu1000-tscss";
+ reg = <0x0 0x01da0000 0x0 0x2000>;
+ reg-names = "tsc";
+
+ clocks = <&gcc GCC_TSC_CFG_AHB_CLK>,
+ <&gcc GCC_TSC_CNTR_CLK>,
+ <&gcc GCC_TSC_ETU_CLK>;
+ clock-names = "ahb", "cntr", "etu";
+ assigned-clocks = <&gcc GCC_TSC_CNTR_CLK>;
+ assigned-clock-rates = <500000000>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x1f40000 0x0 0x20000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 08/10] arm64: dts: qcom: qdu1000: Add support for TSCSS node
2026-11-08 13:18 ` [PATCH v2 08/10] arm64: dts: qcom: qdu1000: " Imran Shaik
@ 2026-11-09 12:52 ` Krzysztof Kozlowski
0 siblings, 0 replies; 24+ messages in thread
From: Krzysztof Kozlowski @ 2026-11-09 12:52 UTC (permalink / raw)
To: Imran Shaik
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev
On Sun, Nov 08, 2026 at 06:48:29PM +0530, Imran Shaik wrote:
> Add Timestamp Counter Subsystem (TSCSS) node support on Qualcomm QDU1000
> SoCs.
>
> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> index 3a25b5100836..0f4028c41b2f 100644
> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> @@ -877,6 +877,19 @@ system_noc: interconnect@1640000 {
> #interconnect-cells = <2>;
> };
>
> + ptp@1da0000 {
> + compatible = "qcom,qdu1000-tscss";
> + reg = <0x0 0x01da0000 0x0 0x2000>;
> + reg-names = "tsc";
I see only one PTP, what about the rest?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 09/10] arm64: dts: qcom: shikra: Add support for TSCSS node
2026-11-08 13:18 [PATCH v2 00/10] Add support for Qualcomm TSCSS hardware Imran Shaik
` (7 preceding siblings ...)
2026-11-08 13:18 ` [PATCH v2 08/10] arm64: dts: qcom: qdu1000: " Imran Shaik
@ 2026-11-08 13:18 ` Imran Shaik
2026-11-08 13:18 ` [PATCH v2 10/10] arm64: dts: qcom: nord: " Imran Shaik
9 siblings, 0 replies; 24+ messages in thread
From: Imran Shaik @ 2026-11-08 13:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Eric Dumazet
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev, Imran Shaik
Add Timestamp Counter Subsystem (TSCSS) node support on Qualcomm Shikra
SoCs.
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 2623e139196f..09aabbf447e0 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -2481,6 +2481,18 @@ compute-cb@6 {
};
};
+ ptp@4b00000 {
+ compatible = "qcom,shikra-tscss", "qcom,nord-tscss";
+ reg = <0x0 0x04b00000 0x0 0x2000>;
+ reg-names = "tsc";
+ clocks = <&gcc GCC_TSCSS_AHB_CLK>,
+ <&gcc GCC_TSCSS_CNTR_CLK>,
+ <&gcc GCC_TSCSS_ETU_CLK>;
+ clock-names = "ahb", "cntr", "etu";
+ assigned-clocks = <&gcc GCC_TSCSS_CNTR_CLK>;
+ assigned-clock-rates = <250000000>;
+ };
+
usb_2: usb@4c00000 {
compatible = "qcom,shikra-dwc3", "qcom,snps-dwc3";
reg = <0x0 0x04c00000 0x0 0xfc100>;
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 10/10] arm64: dts: qcom: nord: Add support for TSCSS node
2026-11-08 13:18 [PATCH v2 00/10] Add support for Qualcomm TSCSS hardware Imran Shaik
` (8 preceding siblings ...)
2026-11-08 13:18 ` [PATCH v2 09/10] arm64: dts: qcom: shikra: " Imran Shaik
@ 2026-11-08 13:18 ` Imran Shaik
2026-11-09 8:43 ` Shawn Guo
2026-11-09 12:52 ` Krzysztof Kozlowski
9 siblings, 2 replies; 24+ messages in thread
From: Imran Shaik @ 2026-11-08 13:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Eric Dumazet
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev, Imran Shaik
Add Timestamp Counter Subsystem (TSCSS) node support on Qualcomm Nord
SoCs.
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
index 1ab7d9bc3cfe..1d5f27336f73 100644
--- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
@@ -736,6 +736,20 @@ pcie_data_inbound: interconnect@1c00000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ ptp@1c80000 {
+ compatible = "qcom,nord-tscss";
+ reg = <0x0 0x01c80000 0x0 0x2000>;
+ reg-names = "tsc";
+
+ clocks = <&segcc SE_GCC_TSCSS_AHB_CLK>,
+ <&segcc SE_GCC_TSCSS_CNTR_CLK>,
+ <&segcc SE_GCC_TSCSS_ETU_CLK>;
+ clock-names = "ahb", "cntr", "etu";
+
+ assigned-clocks = <&segcc SE_GCC_TSCSS_CNTR_CLK>;
+ assigned-clock-rates = <250000000>;
+ };
+
ufs_mem_phy: phy@1d40000 {
compatible = "qcom,nord-qmp-ufs-phy",
"qcom,sm8650-qmp-ufs-phy";
--
2.34.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 10/10] arm64: dts: qcom: nord: Add support for TSCSS node
2026-11-08 13:18 ` [PATCH v2 10/10] arm64: dts: qcom: nord: " Imran Shaik
@ 2026-11-09 8:43 ` Shawn Guo
2026-11-09 12:52 ` Krzysztof Kozlowski
1 sibling, 0 replies; 24+ messages in thread
From: Shawn Guo @ 2026-11-09 8:43 UTC (permalink / raw)
To: Imran Shaik
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev
On Sun, Nov 08, 2026 at 06:48:31PM +0530, Imran Shaik wrote:
> Add Timestamp Counter Subsystem (TSCSS) node support on Qualcomm Nord
> SoCs.
>
> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
> index 1ab7d9bc3cfe..1d5f27336f73 100644
> --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
> @@ -736,6 +736,20 @@ pcie_data_inbound: interconnect@1c00000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + ptp@1c80000 {
> + compatible = "qcom,nord-tscss";
> + reg = <0x0 0x01c80000 0x0 0x2000>;
> + reg-names = "tsc";
The node should probably go to nord.dtsi with nord-embedded.dtsi
supplementing Embedded specific resources like clocks.
Shawn
> +
> + clocks = <&segcc SE_GCC_TSCSS_AHB_CLK>,
> + <&segcc SE_GCC_TSCSS_CNTR_CLK>,
> + <&segcc SE_GCC_TSCSS_ETU_CLK>;
> + clock-names = "ahb", "cntr", "etu";
> +
> + assigned-clocks = <&segcc SE_GCC_TSCSS_CNTR_CLK>;
> + assigned-clock-rates = <250000000>;
> + };
> +
> ufs_mem_phy: phy@1d40000 {
> compatible = "qcom,nord-qmp-ufs-phy",
> "qcom,sm8650-qmp-ufs-phy";
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH v2 10/10] arm64: dts: qcom: nord: Add support for TSCSS node
2026-11-08 13:18 ` [PATCH v2 10/10] arm64: dts: qcom: nord: " Imran Shaik
2026-11-09 8:43 ` Shawn Guo
@ 2026-11-09 12:52 ` Krzysztof Kozlowski
1 sibling, 0 replies; 24+ messages in thread
From: Krzysztof Kozlowski @ 2026-11-09 12:52 UTC (permalink / raw)
To: Imran Shaik
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Andrew Lunn, David S. Miller, Jakub Kicinski, Paolo Abeni,
Bjorn Andersson, Konrad Dybcio, Eric Dumazet, Abel Vesa,
Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm,
devicetree, linux-kernel, netdev
On Sun, Nov 08, 2026 at 06:48:31PM +0530, Imran Shaik wrote:
> Add Timestamp Counter Subsystem (TSCSS) node support on Qualcomm Nord
> SoCs.
>
> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
> index 1ab7d9bc3cfe..1d5f27336f73 100644
> --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
> @@ -736,6 +736,20 @@ pcie_data_inbound: interconnect@1c00000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + ptp@1c80000 {
> + compatible = "qcom,nord-tscss";
> + reg = <0x0 0x01c80000 0x0 0x2000>;
> + reg-names = "tsc";
And the rest of the devices or entries here? Are you sure you are adding
complete DTS for this device?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 24+ messages in thread