[PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32

[PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32

[Atish Patra]

Pass the upper half of the initial value of the counter correctly
for RV32.

Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 drivers/perf/riscv_pmu_sbi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index a1317a483512..24cea59612be 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -526,7 +526,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
 			max_period = riscv_pmu_ctr_get_width_mask(event);
 			init_val = local64_read(&hwc->prev_count) & max_period;
 			sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
-				  flag, init_val, 0, 0);
+				  flag, init_val, init_val >> 32, 0);
 		}
 		ctr_ovf_mask = ctr_ovf_mask >> 1;
 		idx++;
-- 
2.25.1

[PATCH 2/2] RISC-V: Update user page mapping only once during start

[Atish Patra]

Currently, riscv_pmu_event_set_period updates the userpage mapping.
However, the caller of riscv_pmu_event_set_period should update
the userpage mapping because the counter can not be updated/started
from set_period function in counter overflow path.

Invoke the perf_event_update_userpage at the caller so that it
doesn't get invoked twice during counter start path.

Fixes: f5bfa23f576f ("RISC-V: Add a perf core library for pmu drivers")

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 drivers/perf/riscv_pmu.c     | 1 -
 drivers/perf/riscv_pmu_sbi.c | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c
index b2b8d2074ed0..130b9f1a40e0 100644
--- a/drivers/perf/riscv_pmu.c
+++ b/drivers/perf/riscv_pmu.c
@@ -170,7 +170,6 @@ int riscv_pmu_event_set_period(struct perf_event *event)
 		left = (max_period >> 1);
 
 	local64_set(&hwc->prev_count, (u64)-left);
-	perf_event_update_userpage(event);
 
 	return overflow;
 }
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 24cea59612be..2eac5db2cc18 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -527,6 +527,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
 			init_val = local64_read(&hwc->prev_count) & max_period;
 			sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
 				  flag, init_val, init_val >> 32, 0);
+			perf_event_update_userpage(event);
 		}
 		ctr_ovf_mask = ctr_ovf_mask >> 1;
 		idx++;
-- 
2.25.1

Re: [PATCH 2/2] RISC-V: Update user page mapping only once during start

[Anup Patel]

On Thu, May 12, 2022 at 1:41 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> Currently, riscv_pmu_event_set_period updates the userpage mapping.
> However, the caller of riscv_pmu_event_set_period should update
> the userpage mapping because the counter can not be updated/started
> from set_period function in counter overflow path.
>
> Invoke the perf_event_update_userpage at the caller so that it
> doesn't get invoked twice during counter start path.
>
> Fixes: f5bfa23f576f ("RISC-V: Add a perf core library for pmu drivers")
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
>  drivers/perf/riscv_pmu.c     | 1 -
>  drivers/perf/riscv_pmu_sbi.c | 1 +
>  2 files changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c
> index b2b8d2074ed0..130b9f1a40e0 100644
> --- a/drivers/perf/riscv_pmu.c
> +++ b/drivers/perf/riscv_pmu.c
> @@ -170,7 +170,6 @@ int riscv_pmu_event_set_period(struct perf_event *event)
>                 left = (max_period >> 1);
>
>         local64_set(&hwc->prev_count, (u64)-left);
> -       perf_event_update_userpage(event);
>
>         return overflow;
>  }
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 24cea59612be..2eac5db2cc18 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -527,6 +527,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
>                         init_val = local64_read(&hwc->prev_count) & max_period;
>                         sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
>                                   flag, init_val, init_val >> 32, 0);
> +                       perf_event_update_userpage(event);
>                 }
>                 ctr_ovf_mask = ctr_ovf_mask >> 1;
>                 idx++;
> --
> 2.25.1
>

Re: [PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32

[Anup Patel]

On Thu, May 12, 2022 at 1:41 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> Pass the upper half of the initial value of the counter correctly
> for RV32.
>
> Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>  drivers/perf/riscv_pmu_sbi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index a1317a483512..24cea59612be 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -526,7 +526,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
>                         max_period = riscv_pmu_ctr_get_width_mask(event);
>                         init_val = local64_read(&hwc->prev_count) & max_period;
>                         sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
> -                                 flag, init_val, 0, 0);
> +                                 flag, init_val, init_val >> 32, 0);

This should be under "#if __riscv_xlen == 32".

>                 }
>                 ctr_ovf_mask = ctr_ovf_mask >> 1;
>                 idx++;
> --
> 2.25.1
>

Apart from above, this looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

Re: [PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32

[Heiko Stübner]

Am Donnerstag, 12. Mai 2022, 06:44:12 CEST schrieb Anup Patel:
> On Thu, May 12, 2022 at 1:41 AM Atish Patra <atishp@rivosinc.com> wrote:
> >
> > Pass the upper half of the initial value of the counter correctly
> > for RV32.
> >
> > Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
> >
> > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > ---
> >  drivers/perf/riscv_pmu_sbi.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> > index a1317a483512..24cea59612be 100644
> > --- a/drivers/perf/riscv_pmu_sbi.c
> > +++ b/drivers/perf/riscv_pmu_sbi.c
> > @@ -526,7 +526,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
> >                         max_period = riscv_pmu_ctr_get_width_mask(event);
> >                         init_val = local64_read(&hwc->prev_count) & max_period;
> >                         sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
> > -                                 flag, init_val, 0, 0);
> > +                                 flag, init_val, init_val >> 32, 0);
> 
> This should be under "#if __riscv_xlen == 32".

What's the difference between using CONFIG_32BIT
and checking the __riscv_xlen flag value?

CONFIG_32BIT seems to be a bit the more kernel'ish
way to do this, but it looks like most SBI parts check the
__riscv_xlen instead.


In any case, looking at the opensbi-side of the call,
this fix is abviously correct, so

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

Re: [PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32

[Anup Patel]

On Thu, May 12, 2022 at 6:12 PM Heiko Stübner <heiko@sntech.de> wrote:
>
> Am Donnerstag, 12. Mai 2022, 06:44:12 CEST schrieb Anup Patel:
> > On Thu, May 12, 2022 at 1:41 AM Atish Patra <atishp@rivosinc.com> wrote:
> > >
> > > Pass the upper half of the initial value of the counter correctly
> > > for RV32.
> > >
> > > Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
> > >
> > > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > > ---
> > >  drivers/perf/riscv_pmu_sbi.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> > > index a1317a483512..24cea59612be 100644
> > > --- a/drivers/perf/riscv_pmu_sbi.c
> > > +++ b/drivers/perf/riscv_pmu_sbi.c
> > > @@ -526,7 +526,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
> > >                         max_period = riscv_pmu_ctr_get_width_mask(event);
> > >                         init_val = local64_read(&hwc->prev_count) & max_period;
> > >                         sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
> > > -                                 flag, init_val, 0, 0);
> > > +                                 flag, init_val, init_val >> 32, 0);
> >
> > This should be under "#if __riscv_xlen == 32".
>
> What's the difference between using CONFIG_32BIT
> and checking the __riscv_xlen flag value?

It's one and the same.

>
> CONFIG_32BIT seems to be a bit the more kernel'ish
> way to do this, but it looks like most SBI parts check the
> __riscv_xlen instead.

I agree with you. We should prefer "#ifdef CONFIG_32BIT"
in this case to match the kernel coding style.

Currently, OpenSBI does not have CONFIG_xyz defines so
over there we use "#if __riscv_xlen == 32".

Regards,
Anup

>
>
> In any case, looking at the opensbi-side of the call,
> this fix is abviously correct, so
>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
>
>
>

Re: [PATCH 1/2] RISC-V: Fix counter restart during overflow for RV32

[Atish Kumar Patra]

On Thu, May 12, 2022 at 8:36 AM Anup Patel <anup@brainfault.org> wrote:
>
> On Thu, May 12, 2022 at 6:12 PM Heiko Stübner <heiko@sntech.de> wrote:
> >
> > Am Donnerstag, 12. Mai 2022, 06:44:12 CEST schrieb Anup Patel:
> > > On Thu, May 12, 2022 at 1:41 AM Atish Patra <atishp@rivosinc.com> wrote:
> > > >
> > > > Pass the upper half of the initial value of the counter correctly
> > > > for RV32.
> > > >
> > > > Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
> > > >
> > > > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > > > ---
> > > >  drivers/perf/riscv_pmu_sbi.c | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> > > > index a1317a483512..24cea59612be 100644
> > > > --- a/drivers/perf/riscv_pmu_sbi.c
> > > > +++ b/drivers/perf/riscv_pmu_sbi.c
> > > > @@ -526,7 +526,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
> > > >                         max_period = riscv_pmu_ctr_get_width_mask(event);
> > > >                         init_val = local64_read(&hwc->prev_count) & max_period;
> > > >                         sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
> > > > -                                 flag, init_val, 0, 0);
> > > > +                                 flag, init_val, init_val >> 32, 0);
> > >
> > > This should be under "#if __riscv_xlen == 32".
> >
> > What's the difference between using CONFIG_32BIT
> > and checking the __riscv_xlen flag value?
>
> It's one and the same.
>
> >
> > CONFIG_32BIT seems to be a bit the more kernel'ish
> > way to do this, but it looks like most SBI parts check the
> > __riscv_xlen instead.
>

Not only SBI parts, there are more users of __riscv_xlen compared
CONFIG_32BIT in arch/riscv.

> I agree with you. We should prefer "#ifdef CONFIG_32BIT"
> in this case to match the kernel coding style.
>

Sure. I will change it to CONFIG_32BIT.


> Currently, OpenSBI does not have CONFIG_xyz defines so
> over there we use "#if __riscv_xlen == 32".
>
> Regards,
> Anup
>
> >
> >
> > In any case, looking at the opensbi-side of the call,
> > this fix is abviously correct, so
> >
> > Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> >
> >
> >