* [PATCH v3 1/2] dt-bindings: i2c: qcom-cci: Document QCM2290 compatible
@ 2025-04-03 10:22 Loic Poulain
2025-04-03 10:22 ` [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node Loic Poulain
2025-04-11 19:19 ` [PATCH v3 1/2] dt-bindings: i2c: qcom-cci: Document QCM2290 compatible Konrad Dybcio
0 siblings, 2 replies; 10+ messages in thread
From: Loic Poulain @ 2025-04-03 10:22 UTC (permalink / raw)
To: andersson, konradybcio
Cc: linux-arm-msm, devicetree, krzk+dt, robh, Loic Poulain,
Krzysztof Kozlowski
The CCI on QCM2290 is the interface for controlling camera sensor over I2C.
It requires only two clocks.
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
v2: Reorder commits and Fix binding testing syntax
v3: Add clocks minItems for msm8974 as top-level minItems changed
.../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 22 +++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
index 73144473b9b2..5d117c8e238c 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
@@ -25,6 +25,7 @@ properties:
- items:
- enum:
+ - qcom,qcm2290-cci
- qcom,sc7280-cci
- qcom,sc8280xp-cci
- qcom,sdm670-cci
@@ -44,11 +45,11 @@ properties:
const: 0
clocks:
- minItems: 3
+ minItems: 2
maxItems: 6
clock-names:
- minItems: 3
+ minItems: 2
maxItems: 6
interrupts:
@@ -113,6 +114,7 @@ allOf:
then:
properties:
clocks:
+ minItems: 3
maxItems: 3
clock-names:
items:
@@ -120,6 +122,22 @@ allOf:
- const: cci_ahb
- const: cci
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcm2290-cci
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: camss_top_ahb
+ - const: cci
+
- if:
properties:
compatible:
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node
2025-04-03 10:22 [PATCH v3 1/2] dt-bindings: i2c: qcom-cci: Document QCM2290 compatible Loic Poulain
@ 2025-04-03 10:22 ` Loic Poulain
2025-04-04 12:10 ` Bryan O'Donoghue
` (2 more replies)
2025-04-11 19:19 ` [PATCH v3 1/2] dt-bindings: i2c: qcom-cci: Document QCM2290 compatible Konrad Dybcio
1 sibling, 3 replies; 10+ messages in thread
From: Loic Poulain @ 2025-04-03 10:22 UTC (permalink / raw)
To: andersson, konradybcio
Cc: linux-arm-msm, devicetree, krzk+dt, robh, Loic Poulain
Add Camera Control Interface (CCI), supporting two I2C masters.
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
---
v2: Reorder commits; Update dts properties order and style
v3: No change for this patch
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 50 +++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
index 7fb5de92bc4c..43fcb4f40a8c 100644
--- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
@@ -557,6 +557,20 @@ qup_uart4_default: qup-uart4-default-state {
bias-disable;
};
+ cci0_default: cci0-default-state {
+ pins = "gpio22", "gpio23";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cci1_default: cci1-default-state {
+ pins = "gpio29", "gpio30";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
sdc1_state_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
@@ -1603,6 +1617,42 @@ adreno_smmu: iommu@59a0000 {
#iommu-cells = <2>;
};
+ cci: cci@5c1b000 {
+ compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x5c1b000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>;
+ clock-names = "camss_top_ahb", "cci";
+ assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>;
+ assigned-clock-rates = <37500000>;
+
+ power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
+
+ pinctrl-0 = <&cci0_default &cci1_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
mdss: display-subsystem@5e00000 {
compatible = "qcom,qcm2290-mdss";
reg = <0x0 0x05e00000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node
2025-04-03 10:22 ` [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node Loic Poulain
@ 2025-04-04 12:10 ` Bryan O'Donoghue
2025-04-07 14:56 ` Loic Poulain
2025-04-08 9:39 ` Bryan O'Donoghue
2025-04-11 19:19 ` Konrad Dybcio
2 siblings, 1 reply; 10+ messages in thread
From: Bryan O'Donoghue @ 2025-04-04 12:10 UTC (permalink / raw)
To: Loic Poulain, andersson, konradybcio
Cc: linux-arm-msm, devicetree, krzk+dt, robh
On 03/04/2025 11:22, Loic Poulain wrote:
> Add Camera Control Interface (CCI), supporting two I2C masters.
>
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> ---
> v2: Reorder commits; Update dts properties order and style
> v3: No change for this patch
>
> arch/arm64/boot/dts/qcom/qcm2290.dtsi | 50 +++++++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> index 7fb5de92bc4c..43fcb4f40a8c 100644
> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> @@ -557,6 +557,20 @@ qup_uart4_default: qup-uart4-default-state {
> bias-disable;
> };
>
> + cci0_default: cci0-default-state {
> + pins = "gpio22", "gpio23";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cci1_default: cci1-default-state {
> + pins = "gpio29", "gpio30";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> sdc1_state_on: sdc1-on-state {
> clk-pins {
> pins = "sdc1_clk";
> @@ -1603,6 +1617,42 @@ adreno_smmu: iommu@59a0000 {
> #iommu-cells = <2>;
> };
>
> + cci: cci@5c1b000 {
> + compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x5c1b000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
> +
> + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>;
> + clock-names = "camss_top_ahb", "cci";
do you not need an axi clock GCC_CAMSS_AXI_CLK ?
> + assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>;
> + assigned-clock-rates = <37500000>;
> +
> + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
> +
> + pinctrl-0 = <&cci0_default &cci1_default>;
> + pinctrl-names = "default";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> mdss: display-subsystem@5e00000 {
> compatible = "qcom,qcm2290-mdss";
> reg = <0x0 0x05e00000 0x0 0x1000>;
> --
> 2.34.1
>
>
other than that
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node
2025-04-04 12:10 ` Bryan O'Donoghue
@ 2025-04-07 14:56 ` Loic Poulain
2025-04-09 18:39 ` Konrad Dybcio
0 siblings, 1 reply; 10+ messages in thread
From: Loic Poulain @ 2025-04-07 14:56 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: andersson, konradybcio, linux-arm-msm, devicetree, krzk+dt, robh
Hi Bryan,
On Fri, Apr 4, 2025 at 2:10 PM Bryan O'Donoghue
<bryan.odonoghue@linaro.org> wrote:
>
> On 03/04/2025 11:22, Loic Poulain wrote:
> > Add Camera Control Interface (CCI), supporting two I2C masters.
> >
> > Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> > ---
> > v2: Reorder commits; Update dts properties order and style
> > v3: No change for this patch
> >
> > arch/arm64/boot/dts/qcom/qcm2290.dtsi | 50 +++++++++++++++++++++++++++
> > 1 file changed, 50 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> > index 7fb5de92bc4c..43fcb4f40a8c 100644
> > --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> > @@ -557,6 +557,20 @@ qup_uart4_default: qup-uart4-default-state {
> > bias-disable;
> > };
> >
> > + cci0_default: cci0-default-state {
> > + pins = "gpio22", "gpio23";
> > + function = "cci_i2c";
> > + drive-strength = <2>;
> > + bias-disable;
> > + };
> > +
> > + cci1_default: cci1-default-state {
> > + pins = "gpio29", "gpio30";
> > + function = "cci_i2c";
> > + drive-strength = <2>;
> > + bias-disable;
> > + };
> > +
> > sdc1_state_on: sdc1-on-state {
> > clk-pins {
> > pins = "sdc1_clk";
> > @@ -1603,6 +1617,42 @@ adreno_smmu: iommu@59a0000 {
> > #iommu-cells = <2>;
> > };
> >
> > + cci: cci@5c1b000 {
> > + compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci";
> > + reg = <0x0 0x5c1b000 0x0 0x1000>;
> > +
> > + interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
> > +
> > + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>;
> > + clock-names = "camss_top_ahb", "cci";
>
> do you not need an axi clock GCC_CAMSS_AXI_CLK ?
AFAIU AXI is not involved for CCI.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node
2025-04-03 10:22 ` [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node Loic Poulain
2025-04-04 12:10 ` Bryan O'Donoghue
@ 2025-04-08 9:39 ` Bryan O'Donoghue
2025-04-11 19:19 ` Konrad Dybcio
2 siblings, 0 replies; 10+ messages in thread
From: Bryan O'Donoghue @ 2025-04-08 9:39 UTC (permalink / raw)
To: Loic Poulain, andersson, konradybcio
Cc: linux-arm-msm, devicetree, krzk+dt, robh
On 03/04/2025 11:22, Loic Poulain wrote:
> Add Camera Control Interface (CCI), supporting two I2C masters.
>
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> ---
> v2: Reorder commits; Update dts properties order and style
> v3: No change for this patch
>
> arch/arm64/boot/dts/qcom/qcm2290.dtsi | 50 +++++++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> index 7fb5de92bc4c..43fcb4f40a8c 100644
> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> @@ -557,6 +557,20 @@ qup_uart4_default: qup-uart4-default-state {
> bias-disable;
> };
>
> + cci0_default: cci0-default-state {
> + pins = "gpio22", "gpio23";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cci1_default: cci1-default-state {
> + pins = "gpio29", "gpio30";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> sdc1_state_on: sdc1-on-state {
> clk-pins {
> pins = "sdc1_clk";
> @@ -1603,6 +1617,42 @@ adreno_smmu: iommu@59a0000 {
> #iommu-cells = <2>;
> };
>
> + cci: cci@5c1b000 {
> + compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x5c1b000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
> +
> + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>;
> + clock-names = "camss_top_ahb", "cci";
> + assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>;
> + assigned-clock-rates = <37500000>;
> +
> + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
> +
> + pinctrl-0 = <&cci0_default &cci1_default>;
> + pinctrl-names = "default";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> mdss: display-subsystem@5e00000 {
> compatible = "qcom,qcm2290-mdss";
> reg = <0x0 0x05e00000 0x0 0x1000>;
> --
> 2.34.1
>
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node
2025-04-07 14:56 ` Loic Poulain
@ 2025-04-09 18:39 ` Konrad Dybcio
2025-04-11 8:02 ` Loic Poulain
0 siblings, 1 reply; 10+ messages in thread
From: Konrad Dybcio @ 2025-04-09 18:39 UTC (permalink / raw)
To: Loic Poulain, Bryan O'Donoghue
Cc: andersson, konradybcio, linux-arm-msm, devicetree, krzk+dt, robh
On 4/7/25 4:56 PM, Loic Poulain wrote:
> Hi Bryan,
>
>
> On Fri, Apr 4, 2025 at 2:10 PM Bryan O'Donoghue
> <bryan.odonoghue@linaro.org> wrote:
>>
>> On 03/04/2025 11:22, Loic Poulain wrote:
>>> Add Camera Control Interface (CCI), supporting two I2C masters.
>>>
>>> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
>>> ---
>>> v2: Reorder commits; Update dts properties order and style
>>> v3: No change for this patch
>>>
>>> arch/arm64/boot/dts/qcom/qcm2290.dtsi | 50 +++++++++++++++++++++++++++
>>> 1 file changed, 50 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>>> index 7fb5de92bc4c..43fcb4f40a8c 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>>> @@ -557,6 +557,20 @@ qup_uart4_default: qup-uart4-default-state {
>>> bias-disable;
>>> };
>>>
>>> + cci0_default: cci0-default-state {
>>> + pins = "gpio22", "gpio23";
>>> + function = "cci_i2c";
>>> + drive-strength = <2>;
>>> + bias-disable;
>>> + };
>>> +
>>> + cci1_default: cci1-default-state {
>>> + pins = "gpio29", "gpio30";
>>> + function = "cci_i2c";
>>> + drive-strength = <2>;
>>> + bias-disable;
>>> + };
>>> +
>>> sdc1_state_on: sdc1-on-state {
>>> clk-pins {
>>> pins = "sdc1_clk";
>>> @@ -1603,6 +1617,42 @@ adreno_smmu: iommu@59a0000 {
>>> #iommu-cells = <2>;
>>> };
>>>
>>> + cci: cci@5c1b000 {
>>> + compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci";
>>> + reg = <0x0 0x5c1b000 0x0 0x1000>;
>>> +
>>> + interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
>>> +
>>> + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>;
>>> + clock-names = "camss_top_ahb", "cci";
>>
>> do you not need an axi clock GCC_CAMSS_AXI_CLK ?
>
> AFAIU AXI is not involved for CCI.
I'm not able to infer that from statically provided infromation, try
forcefully shutting the clock down (both the branch and _SRC) and
poking at the CCI
Konrad
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node
2025-04-09 18:39 ` Konrad Dybcio
@ 2025-04-11 8:02 ` Loic Poulain
2025-04-11 19:15 ` Konrad Dybcio
0 siblings, 1 reply; 10+ messages in thread
From: Loic Poulain @ 2025-04-11 8:02 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bryan O'Donoghue, andersson, konradybcio, linux-arm-msm,
devicetree, krzk+dt, robh
Hi Konrad, Bryan,
On Wed, Apr 9, 2025 at 8:39 PM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 4/7/25 4:56 PM, Loic Poulain wrote:
> > Hi Bryan,
> >
> >
> > On Fri, Apr 4, 2025 at 2:10 PM Bryan O'Donoghue
> > <bryan.odonoghue@linaro.org> wrote:
> >>
> >> On 03/04/2025 11:22, Loic Poulain wrote:
> >>> Add Camera Control Interface (CCI), supporting two I2C masters.
> >>>
> >>> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> >>> ---
> >>> v2: Reorder commits; Update dts properties order and style
> >>> v3: No change for this patch
> >>>
> >>> arch/arm64/boot/dts/qcom/qcm2290.dtsi | 50 +++++++++++++++++++++++++++
> >>> 1 file changed, 50 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> >>> index 7fb5de92bc4c..43fcb4f40a8c 100644
> >>> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> >>> @@ -557,6 +557,20 @@ qup_uart4_default: qup-uart4-default-state {
> >>> bias-disable;
> >>> };
> >>>
> >>> + cci0_default: cci0-default-state {
> >>> + pins = "gpio22", "gpio23";
> >>> + function = "cci_i2c";
> >>> + drive-strength = <2>;
> >>> + bias-disable;
> >>> + };
> >>> +
> >>> + cci1_default: cci1-default-state {
> >>> + pins = "gpio29", "gpio30";
> >>> + function = "cci_i2c";
> >>> + drive-strength = <2>;
> >>> + bias-disable;
> >>> + };
> >>> +
> >>> sdc1_state_on: sdc1-on-state {
> >>> clk-pins {
> >>> pins = "sdc1_clk";
> >>> @@ -1603,6 +1617,42 @@ adreno_smmu: iommu@59a0000 {
> >>> #iommu-cells = <2>;
> >>> };
> >>>
> >>> + cci: cci@5c1b000 {
> >>> + compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci";
> >>> + reg = <0x0 0x5c1b000 0x0 0x1000>;
> >>> +
> >>> + interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
> >>> +
> >>> + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>;
> >>> + clock-names = "camss_top_ahb", "cci";
> >>
> >> do you not need an axi clock GCC_CAMSS_AXI_CLK ?
> >
> > AFAIU AXI is not involved for CCI.
>
> I'm not able to infer that from statically provided infromation, try
> forcefully shutting the clock down (both the branch and _SRC) and
> poking at the CCI
CCI is a 'slow' device, both control and data flow go through register
R/W (ahb/cnoc).
Below is an experiment showing CAMSS AXI can be off during CCI operation.
```
$ cat /sys/kernel/debug/clk/clk_summary | grep -e camss_axi -e camss_cci
gcc_camss_axi_clk_src 0 0 0
19200000 0 0 50000 ? deviceless
gcc_camss_axi_clk 0 0 0
19200000 0 0 50000 N 5c52000.camss
bus
gcc_camss_cci_clk_src 0 0 0
37500000 0 0 50000 ? deviceless
gcc_camss_cci_0_clk 0 0 0
37500000 0 0 50000 N cci@5c1b000
$ echo on > /sys/bus/platform/drivers/i2c-qcom-cci/5c1b000.cci/power/control
$ cat /sys/kernel/debug/clk/clk_summary | grep -e camss_axi -e camss_cci
gcc_camss_axi_clk_src 0 0 0
19200000 0 0 50000 ? deviceless
gcc_camss_axi_clk 0 0 0
19200000 0 0 50000 N 5c52000.camss
bus
gcc_camss_cci_clk_src 1 1 0
37500000 0 0 50000 ? deviceless
gcc_camss_cci_0_clk 1 1 0
37500000 0 0 50000 Y cci@5c1b000
$ cat /sys/class/i2c-dev/i2c-2/name
Qualcomm-CCI
$ i2cdetect -y -r -a 2
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
# Dump GCC CAMSS AXI clock registers
$ dd if=/sys/kernel/debug/regmap/1400000.clock-controller/registers
count=8 bs=16 skip=90123
5802c: 80000000 # CAMSS_AXI_CMD_RCGR => ROOT_EN_DISABLE | ROOT_OFF
58030: 00000000 # CAMSS_AXI_CFG_RCGR => SRC_0 | BYPASS | HW_CLK_DISABLE
[...]
58044: 80000220 # CAMSS_AXI_CBCR => CLK_DISABLE | SLEEP_CLOCK2 |
WAKEUP_CLK2 | CLK_OFF
58048: 00010c00 # GCC_CAMSS_AXI_SREGR => MEM_CORE_ON_ACK |
MEM_PERIPH_ON_ACK | PSCBC_SPARE_CTRL_IN
```
Regards,
Loic
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node
2025-04-11 8:02 ` Loic Poulain
@ 2025-04-11 19:15 ` Konrad Dybcio
0 siblings, 0 replies; 10+ messages in thread
From: Konrad Dybcio @ 2025-04-11 19:15 UTC (permalink / raw)
To: Loic Poulain
Cc: Bryan O'Donoghue, andersson, konradybcio, linux-arm-msm,
devicetree, krzk+dt, robh
On 4/11/25 10:02 AM, Loic Poulain wrote:
> Hi Konrad, Bryan,
>
> On Wed, Apr 9, 2025 at 8:39 PM Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 4/7/25 4:56 PM, Loic Poulain wrote:
>>> Hi Bryan,
>>>
>>>
>>> On Fri, Apr 4, 2025 at 2:10 PM Bryan O'Donoghue
>>> <bryan.odonoghue@linaro.org> wrote:
>>>>
>>>> On 03/04/2025 11:22, Loic Poulain wrote:
>>>>> Add Camera Control Interface (CCI), supporting two I2C masters.
>>>>>
>>>>> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
>>>>> ---
>>>>> v2: Reorder commits; Update dts properties order and style
>>>>> v3: No change for this patch
>>>>>
>>>>> arch/arm64/boot/dts/qcom/qcm2290.dtsi | 50 +++++++++++++++++++++++++++
>>>>> 1 file changed, 50 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>>>>> index 7fb5de92bc4c..43fcb4f40a8c 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>>>>> @@ -557,6 +557,20 @@ qup_uart4_default: qup-uart4-default-state {
>>>>> bias-disable;
>>>>> };
>>>>>
>>>>> + cci0_default: cci0-default-state {
>>>>> + pins = "gpio22", "gpio23";
>>>>> + function = "cci_i2c";
>>>>> + drive-strength = <2>;
>>>>> + bias-disable;
>>>>> + };
>>>>> +
>>>>> + cci1_default: cci1-default-state {
>>>>> + pins = "gpio29", "gpio30";
>>>>> + function = "cci_i2c";
>>>>> + drive-strength = <2>;
>>>>> + bias-disable;
>>>>> + };
>>>>> +
>>>>> sdc1_state_on: sdc1-on-state {
>>>>> clk-pins {
>>>>> pins = "sdc1_clk";
>>>>> @@ -1603,6 +1617,42 @@ adreno_smmu: iommu@59a0000 {
>>>>> #iommu-cells = <2>;
>>>>> };
>>>>>
>>>>> + cci: cci@5c1b000 {
>>>>> + compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci";
>>>>> + reg = <0x0 0x5c1b000 0x0 0x1000>;
>>>>> +
>>>>> + interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
>>>>> +
>>>>> + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>;
>>>>> + clock-names = "camss_top_ahb", "cci";
>>>>
>>>> do you not need an axi clock GCC_CAMSS_AXI_CLK ?
>>>
>>> AFAIU AXI is not involved for CCI.
>>
>> I'm not able to infer that from statically provided infromation, try
>> forcefully shutting the clock down (both the branch and _SRC) and
>> poking at the CCI
>
> CCI is a 'slow' device, both control and data flow go through register
> R/W (ahb/cnoc).
This is not always a given ;)
> Below is an experiment showing CAMSS AXI can be off during CCI operation.
>
> ```
> $ cat /sys/kernel/debug/clk/clk_summary | grep -e camss_axi -e camss_cci
> gcc_camss_axi_clk_src 0 0 0
> 19200000 0 0 50000 ? deviceless
> gcc_camss_axi_clk 0 0 0
> 19200000 0 0 50000 N 5c52000.camss
> bus
> gcc_camss_cci_clk_src 0 0 0
> 37500000 0 0 50000 ? deviceless
> gcc_camss_cci_0_clk 0 0 0
> 37500000 0 0 50000 N cci@5c1b000
>
> $ echo on > /sys/bus/platform/drivers/i2c-qcom-cci/5c1b000.cci/power/control
>
> $ cat /sys/kernel/debug/clk/clk_summary | grep -e camss_axi -e camss_cci
> gcc_camss_axi_clk_src 0 0 0
> 19200000 0 0 50000 ? deviceless
> gcc_camss_axi_clk 0 0 0
> 19200000 0 0 50000 N 5c52000.camss
> bus
> gcc_camss_cci_clk_src 1 1 0
> 37500000 0 0 50000 ? deviceless
> gcc_camss_cci_0_clk 1 1 0
> 37500000 0 0 50000 Y cci@5c1b000
>
> $ cat /sys/class/i2c-dev/i2c-2/name
> Qualcomm-CCI
>
> $ i2cdetect -y -r -a 2
> 0 1 2 3 4 5 6 7 8 9 a b c d e f
> 00: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
> 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
> 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
> 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
> 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
> 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
> 60: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
> 70: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>
> # Dump GCC CAMSS AXI clock registers
> $ dd if=/sys/kernel/debug/regmap/1400000.clock-controller/registers
> count=8 bs=16 skip=90123
> 5802c: 80000000 # CAMSS_AXI_CMD_RCGR => ROOT_EN_DISABLE | ROOT_OFF
> 58030: 00000000 # CAMSS_AXI_CFG_RCGR => SRC_0 | BYPASS | HW_CLK_DISABLE
> [...]
> 58044: 80000220 # CAMSS_AXI_CBCR => CLK_DISABLE | SLEEP_CLOCK2 |
> WAKEUP_CLK2 | CLK_OFF
> 58048: 00010c00 # GCC_CAMSS_AXI_SREGR => MEM_CORE_ON_ACK |
> MEM_PERIPH_ON_ACK | PSCBC_SPARE_CTRL_IN
Amazing, thank you
Konrad
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: i2c: qcom-cci: Document QCM2290 compatible
2025-04-03 10:22 [PATCH v3 1/2] dt-bindings: i2c: qcom-cci: Document QCM2290 compatible Loic Poulain
2025-04-03 10:22 ` [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node Loic Poulain
@ 2025-04-11 19:19 ` Konrad Dybcio
1 sibling, 0 replies; 10+ messages in thread
From: Konrad Dybcio @ 2025-04-11 19:19 UTC (permalink / raw)
To: Loic Poulain, andersson, konradybcio
Cc: linux-arm-msm, devicetree, krzk+dt, robh, Krzysztof Kozlowski
On 4/3/25 12:22 PM, Loic Poulain wrote:
> The CCI on QCM2290 is the interface for controlling camera sensor over I2C.
> It requires only two clocks.
>
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
[...]
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,qcm2290-cci
> + then:
> + properties:
> + clocks:
> + minItems: 2
> + maxItems: 2
> + clock-names:
> + items:
> + - const: camss_top_ahb
> + - const: cci
Since you've proven that only these two clocks are necessary and we're
adding new bindings anyway, let's call the first one 'ahb' (cci doesn't
really know it's inside the camss block), sorry I didn't think about
this earlier
Konrad
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node
2025-04-03 10:22 ` [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node Loic Poulain
2025-04-04 12:10 ` Bryan O'Donoghue
2025-04-08 9:39 ` Bryan O'Donoghue
@ 2025-04-11 19:19 ` Konrad Dybcio
2 siblings, 0 replies; 10+ messages in thread
From: Konrad Dybcio @ 2025-04-11 19:19 UTC (permalink / raw)
To: Loic Poulain, andersson, konradybcio
Cc: linux-arm-msm, devicetree, krzk+dt, robh
On 4/3/25 12:22 PM, Loic Poulain wrote:
> Add Camera Control Interface (CCI), supporting two I2C masters.
>
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 10+ messages in thread
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2025-04-03 10:22 [PATCH v3 1/2] dt-bindings: i2c: qcom-cci: Document QCM2290 compatible Loic Poulain
2025-04-03 10:22 ` [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node Loic Poulain
2025-04-04 12:10 ` Bryan O'Donoghue
2025-04-07 14:56 ` Loic Poulain
2025-04-09 18:39 ` Konrad Dybcio
2025-04-11 8:02 ` Loic Poulain
2025-04-11 19:15 ` Konrad Dybcio
2025-04-08 9:39 ` Bryan O'Donoghue
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