* [PATCH 01/10] soc: renesas: Identify RZ/G2M v3.0 SoC
2026-08-21 15:03 [PATCH 00/10] Add support for Renesas RZ/G2M v3.0 (a.k.a R8A774A3) SoC Ayman Chaudhry
@ 2026-08-21 15:03 ` Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 02/10] dt-bindings: power: Add r8a774a3 SYSC power domain definitions Ayman Chaudhry
` (8 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Ayman Chaudhry @ 2026-08-21 15:03 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stephen Boyd, Brian Masney, Jerome Brunet,
Ulf Hansson
Cc: Ayman Chaudhry, linux-renesas-soc, devicetree, linux-kernel,
linux-clk, linux-pm, Chris Paterson, Biju Das, Fabrizio Castro,
Lad Prabhakar
Add support to identify the Renesas RZ/G2M v3.0 (a.k.a. R8A774A3) SoC.
The RZ/G2M v3.0 is assigned the same Product ID Number in the Product
Register as the Renesas RZ/G2M v1.3 (a.k.a. R8A774A1), so use the same
SoC data.
Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
---
drivers/soc/renesas/Kconfig | 7 +++++++
drivers/soc/renesas/renesas-soc.c | 3 +++
2 files changed, 10 insertions(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index eb8ac0d47d9d..35479c2330f3 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -227,6 +227,13 @@ config ARCH_R8A774A1
help
This enables support for the Renesas RZ/G2M SoC.
+config ARCH_R8A774A3
+ bool "ARM64 Platform support for R8A774A3 (RZ/G2M v3.0)"
+ default y if ARCH_RENESAS
+ select ARCH_RCAR_GEN3
+ help
+ This enables support for the Renesas RZ/G2M SoC (version 3.0).
+
config ARCH_R8A774B1
bool "ARM64 Platform support for R8A774B1 (RZ/G2N)"
default y if ARCH_RENESAS
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 18acca73064c..5a5d05013eb7 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -312,6 +312,9 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = {
#ifdef CONFIG_ARCH_R8A774A1
{ .compatible = "renesas,r8a774a1", .data = &soc_rz_g2m },
#endif
+#ifdef CONFIG_ARCH_R8A774A3
+ { .compatible = "renesas,r8a774a3", .data = &soc_rz_g2m },
+#endif
#ifdef CONFIG_ARCH_R8A774B1
{ .compatible = "renesas,r8a774b1", .data = &soc_rz_g2n },
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 02/10] dt-bindings: power: Add r8a774a3 SYSC power domain definitions
2026-08-21 15:03 [PATCH 00/10] Add support for Renesas RZ/G2M v3.0 (a.k.a R8A774A3) SoC Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 01/10] soc: renesas: Identify RZ/G2M v3.0 SoC Ayman Chaudhry
@ 2026-08-21 15:03 ` Ayman Chaudhry
2026-08-22 7:29 ` Krzysztof Kozlowski
2026-08-21 15:03 ` [PATCH 03/10] pmdomain: renesas: rcar-sys: Add r8a774a3 support Ayman Chaudhry
` (7 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Ayman Chaudhry @ 2026-08-21 15:03 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stephen Boyd, Brian Masney, Jerome Brunet,
Ulf Hansson
Cc: Ayman Chaudhry, linux-renesas-soc, devicetree, linux-kernel,
linux-clk, linux-pm, Chris Paterson, Biju Das, Fabrizio Castro,
Lad Prabhakar
This patch adds power domain indices for the Renesas RZ/G2M v3.0
(a.k.a. R8A774A3) SoC.
Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
---
include/dt-bindings/power/r8a774a3-sysc.h | 30 +++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 include/dt-bindings/power/r8a774a3-sysc.h
diff --git a/include/dt-bindings/power/r8a774a3-sysc.h b/include/dt-bindings/power/r8a774a3-sysc.h
new file mode 100644
index 000000000000..5694a422b771
--- /dev/null
+++ b/include/dt-bindings/power/r8a774a3-sysc.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A774A3_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A774A3_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A774A3_PD_CA57_CPU0 0
+#define R8A774A3_PD_CA57_CPU1 1
+#define R8A774A3_PD_CA53_CPU0 5
+#define R8A774A3_PD_CA53_CPU1 6
+#define R8A774A3_PD_CA53_CPU2 7
+#define R8A774A3_PD_CA53_CPU3 8
+#define R8A774A3_PD_CA57_SCU 12
+#define R8A774A3_PD_A3VC 14
+#define R8A774A3_PD_3DG_A 17
+#define R8A774A3_PD_3DG_B 18
+#define R8A774A3_PD_CA53_SCU 21
+#define R8A774A3_PD_A2VC1 26
+
+/* Always-on power area */
+#define R8A774A3_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A774A3_SYSC_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 02/10] dt-bindings: power: Add r8a774a3 SYSC power domain definitions
2026-08-21 15:03 ` [PATCH 02/10] dt-bindings: power: Add r8a774a3 SYSC power domain definitions Ayman Chaudhry
@ 2026-08-22 7:29 ` Krzysztof Kozlowski
0 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2026-08-22 7:29 UTC (permalink / raw)
To: Ayman Chaudhry, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Stephen Boyd, Brian Masney,
Jerome Brunet, Ulf Hansson
Cc: linux-renesas-soc, devicetree, linux-kernel, linux-clk, linux-pm,
Chris Paterson, Biju Das, Fabrizio Castro, Lad Prabhakar
On 21/08/2026 17:03, Ayman Chaudhry wrote:
> This patch adds power domain indices for the Renesas RZ/G2M v3.0
Please do not use "This commit/patch/change", but imperative mood. See
longer explanation here:
https://elixir.bootlin.com/linux/v6.16/source/Documentation/process/submitting-patches.rst#L94
> (a.k.a. R8A774A3) SoC.
>
> Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
> ---
> include/dt-bindings/power/r8a774a3-sysc.h | 30 +++++++++++++++++++++++
Filename must match compatible.
> 1 file changed, 30 insertions(+)
> create mode 100644 include/dt-bindings/power/r8a774a3-sysc.h
>
> diff --git a/include/dt-bindings/power/r8a774a3-sysc.h b/include/dt-bindings/power/r8a774a3-sysc.h
> new file mode 100644
> index 000000000000..5694a422b771
> --- /dev/null
> +++ b/include/dt-bindings/power/r8a774a3-sysc.h
> @@ -0,0 +1,30 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_POWER_R8A774A3_SYSC_H__
> +#define __DT_BINDINGS_POWER_R8A774A3_SYSC_H__
> +
> +/*
> + * These power domain indices match the numbers of the interrupt bits
No, that's not a binding then.
Also, why is this sent separately from the binding?
> + * representing the power areas in the various Interrupt Registers
> + * (e.g. SYSCISR, Interrupt Status Register)
> + */
> +
> +#define R8A774A3_PD_CA57_CPU0 0
> +#define R8A774A3_PD_CA57_CPU1 1
> +#define R8A774A3_PD_CA53_CPU0 5
No, value is 2. Or not a binding.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 03/10] pmdomain: renesas: rcar-sys: Add r8a774a3 support
2026-08-21 15:03 [PATCH 00/10] Add support for Renesas RZ/G2M v3.0 (a.k.a R8A774A3) SoC Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 01/10] soc: renesas: Identify RZ/G2M v3.0 SoC Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 02/10] dt-bindings: power: Add r8a774a3 SYSC power domain definitions Ayman Chaudhry
@ 2026-08-21 15:03 ` Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 04/10] soc: renesas: Enable SYSC driver for r8a774a3 Ayman Chaudhry
` (6 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Ayman Chaudhry @ 2026-08-21 15:03 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stephen Boyd, Brian Masney, Jerome Brunet,
Ulf Hansson
Cc: Ayman Chaudhry, linux-renesas-soc, devicetree, linux-kernel,
linux-clk, linux-pm, Chris Paterson, Biju Das, Fabrizio Castro,
Lad Prabhakar
Add support for Renesas RZ/G2M v3.0 (a.k.a. R8A774A3) SoC power areas
to the R-Car SYSC driver. The RZ/G2M v3.0 SYSC is similar to the RZ/G2M
v1.3 SYSC, however it lacks the A2VC0 power area.
Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
---
drivers/pmdomain/renesas/Kconfig | 4 +++
drivers/pmdomain/renesas/Makefile | 1 +
drivers/pmdomain/renesas/r8a774a3-sysc.c | 45 ++++++++++++++++++++++++
drivers/pmdomain/renesas/rcar-sysc.c | 3 ++
drivers/pmdomain/renesas/rcar-sysc.h | 1 +
5 files changed, 54 insertions(+)
create mode 100644 drivers/pmdomain/renesas/r8a774a3-sysc.c
diff --git a/drivers/pmdomain/renesas/Kconfig b/drivers/pmdomain/renesas/Kconfig
index f2f52d3c29a0..df19b95c4655 100644
--- a/drivers/pmdomain/renesas/Kconfig
+++ b/drivers/pmdomain/renesas/Kconfig
@@ -37,6 +37,10 @@ config SYSC_R8A774A1
bool "System Controller support for R8A774A1 (RZ/G2M)" if COMPILE_TEST
select SYSC_RCAR
+config SYSC_R8A774A3
+ bool "System Controller support for R8A774A3 (RZ/G2M v3.0)" if COMPILE_TEST
+ select SYSC_RCAR
+
config SYSC_R8A774B1
bool "System Controller support for R8A774B1 (RZ/G2N)" if COMPILE_TEST
select SYSC_RCAR
diff --git a/drivers/pmdomain/renesas/Makefile b/drivers/pmdomain/renesas/Makefile
index 17849aad37a5..8eda820478e4 100644
--- a/drivers/pmdomain/renesas/Makefile
+++ b/drivers/pmdomain/renesas/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o
obj-$(CONFIG_SYSC_R8A774A1) += r8a774a1-sysc.o
+obj-$(CONFIG_SYSC_R8A774A3) += r8a774a3-sysc.o
obj-$(CONFIG_SYSC_R8A774B1) += r8a774b1-sysc.o
obj-$(CONFIG_SYSC_R8A774C0) += r8a774c0-sysc.o
obj-$(CONFIG_SYSC_R8A774E1) += r8a774e1-sysc.o
diff --git a/drivers/pmdomain/renesas/r8a774a3-sysc.c b/drivers/pmdomain/renesas/r8a774a3-sysc.c
new file mode 100644
index 000000000000..7c8160e09cf3
--- /dev/null
+++ b/drivers/pmdomain/renesas/r8a774a3-sysc.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2M v3.0 System Controller
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ *
+ * Based on Renesas R-Car M3-W System Controller
+ * Copyright (C) 2016 Glider bvba
+ */
+
+#include <linux/kernel.h>
+
+#include <dt-bindings/power/r8a774a3-sysc.h>
+
+#include "rcar-sysc.h"
+
+static const struct rcar_sysc_area r8a774a3_areas[] __initconst = {
+ { "always-on", 0, 0, R8A774A3_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+ { "ca57-scu", 0x1c0, 0, R8A774A3_PD_CA57_SCU, R8A774A3_PD_ALWAYS_ON,
+ PD_SCU },
+ { "ca57-cpu0", 0x80, 0, R8A774A3_PD_CA57_CPU0, R8A774A3_PD_CA57_SCU,
+ PD_CPU_NOCR },
+ { "ca57-cpu1", 0x80, 1, R8A774A3_PD_CA57_CPU1, R8A774A3_PD_CA57_SCU,
+ PD_CPU_NOCR},
+ { "ca53-scu", 0x140, 0, R8A774A3_PD_CA53_SCU, R8A774A3_PD_ALWAYS_ON,
+ PD_SCU },
+ { "ca53-cpu0", 0x200, 0, R8A774A3_PD_CA53_CPU0, R8A774A3_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "ca53-cpu1", 0x200, 1, R8A774A3_PD_CA53_CPU1, R8A774A3_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "ca53-cpu2", 0x200, 2, R8A774A3_PD_CA53_CPU2, R8A774A3_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "ca53-cpu3", 0x200, 3, R8A774A3_PD_CA53_CPU3, R8A774A3_PD_CA53_SCU,
+ PD_CPU_NOCR },
+ { "a3vc", 0x380, 0, R8A774A3_PD_A3VC, R8A774A3_PD_ALWAYS_ON },
+ { "a2vc1", 0x3c0, 1, R8A774A3_PD_A2VC1, R8A774A3_PD_A3VC },
+ { "3dg-a", 0x100, 0, R8A774A3_PD_3DG_A, R8A774A3_PD_ALWAYS_ON },
+ { "3dg-b", 0x100, 1, R8A774A3_PD_3DG_B, R8A774A3_PD_3DG_A },
+};
+
+const struct rcar_sysc_info r8a774a3_sysc_info __initconst = {
+ .areas = r8a774a3_areas,
+ .num_areas = ARRAY_SIZE(r8a774a3_areas),
+ .extmask_offs = 0x2f8,
+ .extmask_val = BIT(0),
+};
diff --git a/drivers/pmdomain/renesas/rcar-sysc.c b/drivers/pmdomain/renesas/rcar-sysc.c
index bd7bb9cbd9da..3c8a44c6d772 100644
--- a/drivers/pmdomain/renesas/rcar-sysc.c
+++ b/drivers/pmdomain/renesas/rcar-sysc.c
@@ -284,6 +284,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
#ifdef CONFIG_SYSC_R8A774A1
{ .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info },
#endif
+#ifdef CONFIG_SYSC_R8A774A3
+ { .compatible = "renesas,r8a774a3-sysc", .data = &r8a774a3_sysc_info },
+#endif
#ifdef CONFIG_SYSC_R8A774B1
{ .compatible = "renesas,r8a774b1-sysc", .data = &r8a774b1_sysc_info },
#endif
diff --git a/drivers/pmdomain/renesas/rcar-sysc.h b/drivers/pmdomain/renesas/rcar-sysc.h
index 07ffce310686..9e93a1f98f68 100644
--- a/drivers/pmdomain/renesas/rcar-sysc.h
+++ b/drivers/pmdomain/renesas/rcar-sysc.h
@@ -55,6 +55,7 @@ extern const struct rcar_sysc_info r8a7743_sysc_info;
extern const struct rcar_sysc_info r8a7745_sysc_info;
extern const struct rcar_sysc_info r8a77470_sysc_info;
extern const struct rcar_sysc_info r8a774a1_sysc_info;
+extern const struct rcar_sysc_info r8a774a3_sysc_info;
extern const struct rcar_sysc_info r8a774b1_sysc_info;
extern const struct rcar_sysc_info r8a774c0_sysc_info;
extern const struct rcar_sysc_info r8a774e1_sysc_info;
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 04/10] soc: renesas: Enable SYSC driver for r8a774a3
2026-08-21 15:03 [PATCH 00/10] Add support for Renesas RZ/G2M v3.0 (a.k.a R8A774A3) SoC Ayman Chaudhry
` (2 preceding siblings ...)
2026-08-21 15:03 ` [PATCH 03/10] pmdomain: renesas: rcar-sys: Add r8a774a3 support Ayman Chaudhry
@ 2026-08-21 15:03 ` Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 05/10] soc: renesas: rcar-rst: Add support for RZ/G2M v3.0 Ayman Chaudhry
` (5 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Ayman Chaudhry @ 2026-08-21 15:03 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stephen Boyd, Brian Masney, Jerome Brunet,
Ulf Hansson
Cc: Ayman Chaudhry, linux-renesas-soc, devicetree, linux-kernel,
linux-clk, linux-pm, Chris Paterson, Biju Das, Fabrizio Castro,
Lad Prabhakar
Select SYSC_R8A774A3 config option if ARCH_R8A774A3 is enabled
so that System Controller driver is enabled on Renesas RZ/G2M v3.0 SoC.
Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
---
drivers/soc/renesas/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 35479c2330f3..cfc56276cb0c 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -231,6 +231,7 @@ config ARCH_R8A774A3
bool "ARM64 Platform support for R8A774A3 (RZ/G2M v3.0)"
default y if ARCH_RENESAS
select ARCH_RCAR_GEN3
+ select SYSC_R8A774A3
help
This enables support for the Renesas RZ/G2M SoC (version 3.0).
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 05/10] soc: renesas: rcar-rst: Add support for RZ/G2M v3.0
2026-08-21 15:03 [PATCH 00/10] Add support for Renesas RZ/G2M v3.0 (a.k.a R8A774A3) SoC Ayman Chaudhry
` (3 preceding siblings ...)
2026-08-21 15:03 ` [PATCH 04/10] soc: renesas: Enable SYSC driver for r8a774a3 Ayman Chaudhry
@ 2026-08-21 15:03 ` Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 06/10] dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions Ayman Chaudhry
` (4 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Ayman Chaudhry @ 2026-08-21 15:03 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stephen Boyd, Brian Masney, Jerome Brunet,
Ulf Hansson
Cc: Ayman Chaudhry, linux-renesas-soc, devicetree, linux-kernel,
linux-clk, linux-pm, Chris Paterson, Biju Das, Fabrizio Castro,
Lad Prabhakar
Add support for Renesas RZ/G2M v3.0 (a.k.a. R8A774A3) SoC to the R-Car
RST driver.
Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
---
drivers/soc/renesas/rcar-rst.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index 0541990901fc..26f976880d3f 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -93,6 +93,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
{ .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
/* RZ/G2 is handled like R-Car Gen3 */
{ .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },
+ { .compatible = "renesas,r8a774a3-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a774b1-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a774c0-rst", .data = &rcar_rst_gen3 },
{ .compatible = "renesas,r8a774e1-rst", .data = &rcar_rst_gen3 },
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 06/10] dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions
2026-08-21 15:03 [PATCH 00/10] Add support for Renesas RZ/G2M v3.0 (a.k.a R8A774A3) SoC Ayman Chaudhry
` (4 preceding siblings ...)
2026-08-21 15:03 ` [PATCH 05/10] soc: renesas: rcar-rst: Add support for RZ/G2M v3.0 Ayman Chaudhry
@ 2026-08-21 15:03 ` Ayman Chaudhry
2026-08-22 7:31 ` Krzysztof Kozlowski
2026-08-21 15:03 ` [PATCH 07/10] clk: renesas: Add support for RZ/G2M v3.0 Ayman Chaudhry
` (3 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Ayman Chaudhry @ 2026-08-21 15:03 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stephen Boyd, Brian Masney, Jerome Brunet,
Ulf Hansson
Cc: Ayman Chaudhry, linux-renesas-soc, devicetree, linux-kernel,
linux-clk, linux-pm, Chris Paterson, Biju Das, Fabrizio Castro,
Lad Prabhakar
Add all the Renesas RZ/G2M v3.0 (a.k.a. R8A774A3) SoC Clock Pulse
Generator Core Clock Outputs, as listed in Table 11.3 ("List of Clocks
[RZ/G2M V1.3, RZ/G2M V3.0]") of the RZ/G2 Hardware User's Manual.
Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
---
include/dt-bindings/clock/r8a774a3-cpg-mssr.h | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a774a3-cpg-mssr.h
diff --git a/include/dt-bindings/clock/r8a774a3-cpg-mssr.h b/include/dt-bindings/clock/r8a774a3-cpg-mssr.h
new file mode 100644
index 000000000000..213695ddbd50
--- /dev/null
+++ b/include/dt-bindings/clock/r8a774a3-cpg-mssr.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A774A3_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A774A3_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a774a3 CPG Core Clocks */
+#define R8A774A3_CLK_Z 0
+#define R8A774A3_CLK_Z2 1
+#define R8A774A3_CLK_ZG 2
+#define R8A774A3_CLK_ZTR 3
+#define R8A774A3_CLK_ZTRD2 4
+#define R8A774A3_CLK_ZT 5
+#define R8A774A3_CLK_ZX 6
+#define R8A774A3_CLK_S0D1 7
+#define R8A774A3_CLK_S0D2 8
+#define R8A774A3_CLK_S0D3 9
+#define R8A774A3_CLK_S0D4 10
+#define R8A774A3_CLK_S0D6 11
+#define R8A774A3_CLK_S0D8 12
+#define R8A774A3_CLK_S0D12 13
+#define R8A774A3_CLK_S1D2 14
+#define R8A774A3_CLK_S1D4 15
+#define R8A774A3_CLK_S2D1 16
+#define R8A774A3_CLK_S2D2 17
+#define R8A774A3_CLK_S2D4 18
+#define R8A774A3_CLK_S3D1 19
+#define R8A774A3_CLK_S3D2 20
+#define R8A774A3_CLK_S3D4 21
+#define R8A774A3_CLK_LB 22
+#define R8A774A3_CLK_CL 23
+#define R8A774A3_CLK_ZB3 24
+#define R8A774A3_CLK_ZB3D2 25
+#define R8A774A3_CLK_ZB3D4 26
+#define R8A774A3_CLK_CR 27
+#define R8A774A3_CLK_CRD2 28
+#define R8A774A3_CLK_SD0H 29
+#define R8A774A3_CLK_SD0 30
+#define R8A774A3_CLK_SD1H 31
+#define R8A774A3_CLK_SD1 32
+#define R8A774A3_CLK_SD2H 33
+#define R8A774A3_CLK_SD2 34
+#define R8A774A3_CLK_SD3H 35
+#define R8A774A3_CLK_SD3 36
+#define R8A774A3_CLK_RPC 37
+#define R8A774A3_CLK_RPCD2 38
+#define R8A774A3_CLK_MSO 39
+#define R8A774A3_CLK_CANFD 40
+#define R8A774A3_CLK_HDMI 41
+#define R8A774A3_CLK_CSI0 42
+#define R8A774A3_CLK_CP 43
+#define R8A774A3_CLK_CPEX 44
+#define R8A774A3_CLK_R 45
+#define R8A774A3_CLK_OSC 46
+
+#endif /* __DT_BINDINGS_CLOCK_R8A774A3_CPG_MSSR_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 06/10] dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions
2026-08-21 15:03 ` [PATCH 06/10] dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions Ayman Chaudhry
@ 2026-08-22 7:31 ` Krzysztof Kozlowski
0 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2026-08-22 7:31 UTC (permalink / raw)
To: Ayman Chaudhry, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Stephen Boyd, Brian Masney,
Jerome Brunet, Ulf Hansson
Cc: linux-renesas-soc, devicetree, linux-kernel, linux-clk, linux-pm,
Chris Paterson, Biju Das, Fabrizio Castro, Lad Prabhakar
On 21/08/2026 17:03, Ayman Chaudhry wrote:
> Add all the Renesas RZ/G2M v3.0 (a.k.a. R8A774A3) SoC Clock Pulse
> Generator Core Clock Outputs, as listed in Table 11.3 ("List of Clocks
> [RZ/G2M V1.3, RZ/G2M V3.0]") of the RZ/G2 Hardware User's Manual.
>
> Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
> ---
> include/dt-bindings/clock/r8a774a3-cpg-mssr.h | 59 +++++++++++++++++++
Same comments. Why are you using discouraged naming and why are you
sending it SEPARATELY from the binding?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 07/10] clk: renesas: Add support for RZ/G2M v3.0
2026-08-21 15:03 [PATCH 00/10] Add support for Renesas RZ/G2M v3.0 (a.k.a R8A774A3) SoC Ayman Chaudhry
` (5 preceding siblings ...)
2026-08-21 15:03 ` [PATCH 06/10] dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions Ayman Chaudhry
@ 2026-08-21 15:03 ` Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 08/10] arm64: dts: renesas: Add initial SoC DTSI " Ayman Chaudhry
` (2 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Ayman Chaudhry @ 2026-08-21 15:03 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stephen Boyd, Brian Masney, Jerome Brunet,
Ulf Hansson
Cc: Ayman Chaudhry, linux-renesas-soc, devicetree, linux-kernel,
linux-clk, linux-pm, Chris Paterson, Biju Das, Fabrizio Castro,
Lad Prabhakar
Add initial support for Renesas RZ/G2M v3.0 (a.k.a. R8A774A3) SoC,
including basic core clocks, and SCIF2 (serial console) and INTC-AP
(GIC) module clocks. The RZ/G2M v3.0 CPG is similar to the RZ/G2M v1.3,
however it lacks some modules such as the FCPCI.
Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
---
drivers/clk/renesas/Kconfig | 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a774a3-cpg-mssr.c | 168 ++++++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6 +
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
5 files changed, 181 insertions(+)
create mode 100644 drivers/clk/renesas/r8a774a3-cpg-mssr.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 17b95a2e96fb..86d1c48c2cec 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -13,6 +13,7 @@ config CLK_RENESAS
select CLK_R8A7745 if ARCH_R8A7745
select CLK_R8A77470 if ARCH_R8A77470
select CLK_R8A774A1 if ARCH_R8A774A1
+ select CLK_R8A774A3 if ARCH_R8A774A3
select CLK_R8A774B1 if ARCH_R8A774B1
select CLK_R8A774C0 if ARCH_R8A774C0
select CLK_R8A774E1 if ARCH_R8A774E1
@@ -93,6 +94,10 @@ config CLK_R8A774A1
bool "RZ/G2M clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
+config CLK_R8A774A3
+ bool "RZ/G2M v3.0 clock support" if COMPILE_TEST
+ select CLK_RCAR_GEN3_CPG
+
config CLK_R8A774B1
bool "RZ/G2N clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 658f8aac5127..5c1b798118db 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A774A3) += r8a774a3-cpg-mssr.o
obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a774a3-cpg-mssr.c b/drivers/clk/renesas/r8a774a3-cpg-mssr.c
new file mode 100644
index 000000000000..327e529c562b
--- /dev/null
+++ b/drivers/clk/renesas/r8a774a3-cpg-mssr.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a774a3 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ *
+ * Based on r8a7796-cpg-mssr.c
+ *
+ * Copyright (C) 2016 Glider bvba
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a774a3-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A774A3_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL3,
+ CLK_PLL4,
+ CLK_PLL1_DIV2,
+ CLK_PLL1_DIV4,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a774a3_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
+
+ /* Core Clock Outputs */
+ DEF_GEN3_Z("z", R8A774A3_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
+ DEF_GEN3_Z("z2", R8A774A3_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
+ DEF_FIXED("s0d3", R8A774A3_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s3d1", R8A774A3_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d4", R8A774A3_CLK_S3D4, CLK_S3, 4, 1),
+};
+
+static const struct mssr_mod_clk r8a774a3_mod_clks[] __initconst = {
+ DEF_MOD("scif2", 310, R8A774A3_CLK_S3D4),
+ DEF_MOD("intc-ap", 408, R8A774A3_CLK_S0D3),
+};
+
+static const unsigned int r8a774a3_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(408), /* INTC-AP (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
+ * 14 13 19 17 (MHz)
+ *-------------------------------------------------------------------------
+ * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
+ * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
+ * 0 0 1 0 Prohibited setting
+ * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
+ * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
+ * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
+ * 0 1 1 0 Prohibited setting
+ * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
+ * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
+ * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
+ * 1 0 1 0 Prohibited setting
+ * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
+ * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
+ * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
+ * 1 1 1 0 Prohibited setting
+ * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
+ (((md) & BIT(13)) >> 11) | \
+ (((md) & BIT(19)) >> 18) | \
+ (((md) & BIT(17)) >> 17))
+
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
+ /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
+ { 1, 192, 1, 192, 1, 16, },
+ { 1, 192, 1, 128, 1, 16, },
+ { 0, /* Prohibited setting */ },
+ { 1, 192, 1, 192, 1, 16, },
+ { 1, 160, 1, 160, 1, 19, },
+ { 1, 160, 1, 106, 1, 19, },
+ { 0, /* Prohibited setting */ },
+ { 1, 160, 1, 160, 1, 19, },
+ { 1, 128, 1, 128, 1, 24, },
+ { 1, 128, 1, 84, 1, 24, },
+ { 0, /* Prohibited setting */ },
+ { 1, 128, 1, 128, 1, 24, },
+ { 2, 192, 1, 192, 1, 32, },
+ { 2, 192, 1, 128, 1, 32, },
+ { 0, /* Prohibited setting */ },
+ { 2, 192, 1, 192, 1, 32, },
+};
+
+static int __init r8a774a3_cpg_mssr_init(struct device *dev)
+{
+ const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+ u32 cpg_mode;
+ int error;
+
+ error = rcar_rst_read_mode_pins(&cpg_mode);
+ if (error)
+ return error;
+
+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+ if (!cpg_pll_config->extal_div) {
+ dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
+ return -EINVAL;
+ }
+
+ return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a774a3_cpg_mssr_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r8a774a3_core_clks,
+ .num_core_clks = ARRAY_SIZE(r8a774a3_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r8a774a3_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r8a774a3_mod_clks),
+ .num_hw_mod_clks = 12 * 32,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r8a774a3_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r8a774a3_crit_mod_clks),
+
+ /* Callbacks */
+ .init = r8a774a3_cpg_mssr_init,
+ .cpg_clk_register = rcar_gen3_cpg_clk_register,
+};
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 80f4403ea2ba..2d815712bbcc 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -944,6 +944,12 @@ static const struct of_device_id cpg_mssr_match[] = {
.data = &r8a774a1_cpg_mssr_info,
},
#endif
+#ifdef CONFIG_CLK_R8A774A3
+ {
+ .compatible = "renesas,r8a774a3-cpg-mssr",
+ .data = &r8a774a3_cpg_mssr_info,
+ },
+#endif
#ifdef CONFIG_CLK_R8A774B1
{
.compatible = "renesas,r8a774b1-cpg-mssr",
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index ad11ab5f0069..3e28bbf50d42 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -190,6 +190,7 @@ extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a774a3_cpg_mssr_info;
extern const struct cpg_mssr_info r8a774b1_cpg_mssr_info;
extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info;
extern const struct cpg_mssr_info r8a774e1_cpg_mssr_info;
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 08/10] arm64: dts: renesas: Add initial SoC DTSI for RZ/G2M v3.0
2026-08-21 15:03 [PATCH 00/10] Add support for Renesas RZ/G2M v3.0 (a.k.a R8A774A3) SoC Ayman Chaudhry
` (6 preceding siblings ...)
2026-08-21 15:03 ` [PATCH 07/10] clk: renesas: Add support for RZ/G2M v3.0 Ayman Chaudhry
@ 2026-08-21 15:03 ` Ayman Chaudhry
2026-08-22 7:38 ` Krzysztof Kozlowski
2026-08-21 15:03 ` [PATCH 09/10] arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC main board support Ayman Chaudhry
2026-08-21 15:03 ` [PATCH 10/10] arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC sub " Ayman Chaudhry
9 siblings, 1 reply; 15+ messages in thread
From: Ayman Chaudhry @ 2026-08-21 15:03 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stephen Boyd, Brian Masney, Jerome Brunet,
Ulf Hansson
Cc: Ayman Chaudhry, linux-renesas-soc, devicetree, linux-kernel,
linux-clk, linux-pm, Chris Paterson, Biju Das, Fabrizio Castro,
Lad Prabhakar
Add initial Device Tree Source Include (DTSI) file for the Renesas
RZ/G2M v3.0 (a.k.a. R8A774A3) SoC with basic support.
Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774a3.dtsi | 302 ++++++++++++++++++++++
1 file changed, 302 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r8a774a3.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r8a774a3.dtsi b/arch/arm64/boot/dts/renesas/r8a774a3.dtsi
new file mode 100644
index 000000000000..f60a31612b39
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774a3.dtsi
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a774a3 SoC
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a774a3-cpg-mssr.h>
+#include <dt-bindings/power/r8a774a3-sysc.h>
+
+/ {
+ compatible = "renesas,r8a774a3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ };
+
+ cluster1_opp: opp-table-1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&a57_0>;
+ };
+ core1 {
+ cpu = <&a57_1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&a53_0>;
+ };
+ core1 {
+ cpu = <&a53_1>;
+ };
+ core2 {
+ cpu = <&a53_2>;
+ };
+ core3 {
+ cpu = <&a53_3>;
+ };
+ };
+ };
+
+ a57_0: cpu@0 {
+ compatible = "arm,cortex-a57";
+ reg = <0x0>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A774A3_PD_CA57_CPU0>;
+ next-level-cache = <&L2_CA57>;
+ enable-method = "psci";
+ dynamic-power-coefficient = <854>;
+ clocks = <&cpg CPG_CORE R8A774A3_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
+ capacity-dmips-mhz = <1024>;
+ };
+
+ a57_1: cpu@1 {
+ compatible = "arm,cortex-a57";
+ reg = <0x1>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A774A3_PD_CA57_CPU1>;
+ next-level-cache = <&L2_CA57>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R8A774A3_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
+ capacity-dmips-mhz = <1024>;
+ };
+
+ a53_0: cpu@100 {
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A774A3_PD_CA53_CPU0>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ dynamic-power-coefficient = <277>;
+ clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <560>;
+ };
+
+ a53_1: cpu@101 {
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A774A3_PD_CA53_CPU1>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <560>;
+ };
+
+ a53_2: cpu@102 {
+ compatible = "arm,cortex-a53";
+ reg = <0x102>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A774A3_PD_CA53_CPU2>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <560>;
+ };
+
+ a53_3: cpu@103 {
+ compatible = "arm,cortex-a53";
+ reg = <0x103>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A774A3_PD_CA53_CPU3>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <560>;
+ };
+
+ L2_CA57: cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&sysc R8A774A3_PD_CA57_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ L2_CA53: cache-controller-1 {
+ compatible = "cache";
+ power-domains = <&sysc R8A774A3_PD_CA53_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ bootph-all;
+ };
+
+ extalr_clk: extalr {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ bootph-all;
+ };
+
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
+ };
+
+ pmu_a57 {
+ compatible = "arm,cortex-a57-pmu";
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a57_0>, <&a57_1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ /* External SCIF clock - to be overridden by boards that provide it */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ bootph-all;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a774a3-cpg-mssr";
+ reg = <0 0xe6150000 0 0x0bb0>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a774a3-rst";
+ reg = <0 0xe6160000 0 0x018c>;
+ bootph-all;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a774a3-sysc";
+ reg = <0 0xe6180000 0 0x0400>;
+ #power-domain-cells = <1>;
+ };
+
+ scif2: serial@e6e88000 {
+ compatible = "renesas,scif-r8a774a3",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e88000 0 0x40>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 310>,
+ <&cpg CPG_CORE R8A774A3_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A774A3_PD_ALWAYS_ON>;
+ resets = <&cpg 310>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@f1010000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xf1010000 0 0x1000>,
+ <0x0 0xf1020000 0 0x20000>,
+ <0x0 0xf1040000 0 0x20000>,
+ <0x0 0xf1060000 0 0x20000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A774A3_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ prr: chipid@fff00044 {
+ compatible = "renesas,prr";
+ reg = <0 0xfff00044 0 4>;
+ bootph-all;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 08/10] arm64: dts: renesas: Add initial SoC DTSI for RZ/G2M v3.0
2026-08-21 15:03 ` [PATCH 08/10] arm64: dts: renesas: Add initial SoC DTSI " Ayman Chaudhry
@ 2026-08-22 7:38 ` Krzysztof Kozlowski
0 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2026-08-22 7:38 UTC (permalink / raw)
To: Ayman Chaudhry, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Stephen Boyd, Brian Masney,
Jerome Brunet, Ulf Hansson
Cc: linux-renesas-soc, devicetree, linux-kernel, linux-clk, linux-pm,
Chris Paterson, Biju Das, Fabrizio Castro, Lad Prabhakar
On 21/08/2026 17:03, Ayman Chaudhry wrote:
> Add initial Device Tree Source Include (DTSI) file for the Renesas
> RZ/G2M v3.0 (a.k.a. R8A774A3) SoC with basic support.
>
> Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
> ---
> arch/arm64/boot/dts/renesas/r8a774a3.dtsi | 302 ++++++++++++++++++++++
> 1 file changed, 302 insertions(+)
> create mode 100644 arch/arm64/boot/dts/renesas/r8a774a3.dtsi
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a774a3.dtsi b/arch/arm64/boot/dts/renesas/r8a774a3.dtsi
> new file mode 100644
> index 000000000000..f60a31612b39
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a774a3.dtsi
> @@ -0,0 +1,302 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the r8a774a3 SoC
> + *
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/r8a774a3-cpg-mssr.h>
> +#include <dt-bindings/power/r8a774a3-sysc.h>
> +
> +/ {
> + compatible = "renesas,r8a774a3";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> +
> + cluster0_opp: opp-table-0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + opp-microvolt = <820000>;
> + clock-latency-ns = <300000>;
> + };
> + opp-1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <820000>;
> + clock-latency-ns = <300000>;
> + };
> + opp-1500000000 {
> + opp-hz = /bits/ 64 <1500000000>;
> + opp-microvolt = <820000>;
> + clock-latency-ns = <300000>;
> + opp-suspend;
> + };
> + };
> +
> + cluster1_opp: opp-table-1 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-microvolt = <820000>;
> + clock-latency-ns = <300000>;
> + };
> + opp-1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <820000>;
> + clock-latency-ns = <300000>;
> + };
> + opp-1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <820000>;
> + clock-latency-ns = <300000>;
> + };
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&a57_0>;
> + };
> + core1 {
> + cpu = <&a57_1>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&a53_0>;
> + };
> + core1 {
> + cpu = <&a53_1>;
> + };
> + core2 {
> + cpu = <&a53_2>;
> + };
> + core3 {
> + cpu = <&a53_3>;
> + };
> + };
> + };
> +
> + a57_0: cpu@0 {
> + compatible = "arm,cortex-a57";
> + reg = <0x0>;
> + device_type = "cpu";
> + power-domains = <&sysc R8A774A3_PD_CA57_CPU0>;
> + next-level-cache = <&L2_CA57>;
> + enable-method = "psci";
> + dynamic-power-coefficient = <854>;
> + clocks = <&cpg CPG_CORE R8A774A3_CLK_Z>;
> + operating-points-v2 = <&cluster0_opp>;
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + a57_1: cpu@1 {
> + compatible = "arm,cortex-a57";
> + reg = <0x1>;
> + device_type = "cpu";
> + power-domains = <&sysc R8A774A3_PD_CA57_CPU1>;
> + next-level-cache = <&L2_CA57>;
> + enable-method = "psci";
> + clocks = <&cpg CPG_CORE R8A774A3_CLK_Z>;
> + operating-points-v2 = <&cluster0_opp>;
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + a53_0: cpu@100 {
> + compatible = "arm,cortex-a53";
> + reg = <0x100>;
> + device_type = "cpu";
> + power-domains = <&sysc R8A774A3_PD_CA53_CPU0>;
> + next-level-cache = <&L2_CA53>;
> + enable-method = "psci";
> + dynamic-power-coefficient = <277>;
> + clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
> + operating-points-v2 = <&cluster1_opp>;
> + capacity-dmips-mhz = <560>;
> + };
> +
> + a53_1: cpu@101 {
> + compatible = "arm,cortex-a53";
> + reg = <0x101>;
> + device_type = "cpu";
> + power-domains = <&sysc R8A774A3_PD_CA53_CPU1>;
> + next-level-cache = <&L2_CA53>;
> + enable-method = "psci";
> + clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
> + operating-points-v2 = <&cluster1_opp>;
> + capacity-dmips-mhz = <560>;
> + };
> +
> + a53_2: cpu@102 {
> + compatible = "arm,cortex-a53";
> + reg = <0x102>;
> + device_type = "cpu";
> + power-domains = <&sysc R8A774A3_PD_CA53_CPU2>;
> + next-level-cache = <&L2_CA53>;
> + enable-method = "psci";
> + clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
> + operating-points-v2 = <&cluster1_opp>;
> + capacity-dmips-mhz = <560>;
> + };
> +
> + a53_3: cpu@103 {
> + compatible = "arm,cortex-a53";
> + reg = <0x103>;
> + device_type = "cpu";
> + power-domains = <&sysc R8A774A3_PD_CA53_CPU3>;
> + next-level-cache = <&L2_CA53>;
> + enable-method = "psci";
> + clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
> + operating-points-v2 = <&cluster1_opp>;
> + capacity-dmips-mhz = <560>;
> + };
> +
> + L2_CA57: cache-controller-0 {
> + compatible = "cache";
> + power-domains = <&sysc R8A774A3_PD_CA57_SCU>;
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + L2_CA53: cache-controller-1 {
> + compatible = "cache";
> + power-domains = <&sysc R8A774A3_PD_CA53_SCU>;
> + cache-unified;
> + cache-level = <2>;
> + };
> + };
> +
> + extal_clk: extal {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + bootph-all;
> + };
> +
> + extalr_clk: extalr {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + bootph-all;
> + };
> +
> + pmu_a53 {
Please, do not send us downstream code. It looks awfully like one. It's
long time fixed in all upstream platforms. Also, this causes now warnings.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 09/10] arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC main board support
2026-08-21 15:03 [PATCH 00/10] Add support for Renesas RZ/G2M v3.0 (a.k.a R8A774A3) SoC Ayman Chaudhry
` (7 preceding siblings ...)
2026-08-21 15:03 ` [PATCH 08/10] arm64: dts: renesas: Add initial SoC DTSI " Ayman Chaudhry
@ 2026-08-21 15:03 ` Ayman Chaudhry
2026-08-22 7:34 ` Krzysztof Kozlowski
2026-08-21 15:03 ` [PATCH 10/10] arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC sub " Ayman Chaudhry
9 siblings, 1 reply; 15+ messages in thread
From: Ayman Chaudhry @ 2026-08-21 15:03 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stephen Boyd, Brian Masney, Jerome Brunet,
Ulf Hansson
Cc: Ayman Chaudhry, linux-renesas-soc, devicetree, linux-kernel,
linux-clk, linux-pm, Chris Paterson, Biju Das, Fabrizio Castro,
Lad Prabhakar
Add support for the HiHope RZ/G2M v3.0 (a.k.a. R8A774A3) SoC main
board.
The RZ/G2M v3.0 SoC main board is similar to the RZ/G2M v1.3 SoC main
board, so there are already DTSI files available in the kernel. These
DTSI files will be included once additional support (e.g. I2C, GPIO
and sound) is added for the RZ/G2M v3.0 SoC.
Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
---
arch/arm64/boot/dts/renesas/Makefile | 2 +
.../dts/renesas/r8a774a3-hihope-rzg2m.dts | 50 +++++++++++++++++++
2 files changed, 52 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 8bf155badd11..6ae96027664d 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -8,6 +8,8 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
+dtb-$(CONFIG_ARCH_R8A774A3) += r8a774a3-hihope-rzg2m.dtb
+
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-beacon-rzg2n-kit.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts b/arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts
new file mode 100644
index 000000000000..f51ba4fd602e
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2M v3.0 SoC main board
+ *
+ *Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774a3.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2M v3.0 main board based on r8a774a3";
+ compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a3";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* First 128MiB is reserved for secure area */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ memory@600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x0 0x80000000>;
+ };
+
+ aliases {
+ serial0 = &scif2;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&scif2 {
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 09/10] arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC main board support
2026-08-21 15:03 ` [PATCH 09/10] arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC main board support Ayman Chaudhry
@ 2026-08-22 7:34 ` Krzysztof Kozlowski
0 siblings, 0 replies; 15+ messages in thread
From: Krzysztof Kozlowski @ 2026-08-22 7:34 UTC (permalink / raw)
To: Ayman Chaudhry, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Stephen Boyd, Brian Masney,
Jerome Brunet, Ulf Hansson
Cc: linux-renesas-soc, devicetree, linux-kernel, linux-clk, linux-pm,
Chris Paterson, Biju Das, Fabrizio Castro, Lad Prabhakar
On 21/08/2026 17:03, Ayman Chaudhry wrote:
> Add support for the HiHope RZ/G2M v3.0 (a.k.a. R8A774A3) SoC main
> board.
>
> The RZ/G2M v3.0 SoC main board is similar to the RZ/G2M v1.3 SoC main
> board, so there are already DTSI files available in the kernel. These
> DTSI files will be included once additional support (e.g. I2C, GPIO
> and sound) is added for the RZ/G2M v3.0 SoC.
>
> Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
> ---
> arch/arm64/boot/dts/renesas/Makefile | 2 +
> .../dts/renesas/r8a774a3-hihope-rzg2m.dts | 50 +++++++++++++++++++
> 2 files changed, 52 insertions(+)
> create mode 100644 arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts
>
> diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
> index 8bf155badd11..6ae96027664d 100644
> --- a/arch/arm64/boot/dts/renesas/Makefile
> +++ b/arch/arm64/boot/dts/renesas/Makefile
> @@ -8,6 +8,8 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb
> dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb
> dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
>
> +dtb-$(CONFIG_ARCH_R8A774A3) += r8a774a3-hihope-rzg2m.dtb
> +
> dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-beacon-rzg2n-kit.dtb
> dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
> dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
> diff --git a/arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts b/arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts
> new file mode 100644
> index 000000000000..f51ba4fd602e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the HiHope RZ/G2M v3.0 SoC main board
> + *
> + *Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +#include "r8a774a3.dtsi"
> +
> +/ {
> + model = "HopeRun HiHope RZ/G2M v3.0 main board based on r8a774a3";
> + compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a3";
> +
> + memory@48000000 {
> + device_type = "memory";
> + /* First 128MiB is reserved for secure area */
> + reg = <0x0 0x48000000 0x0 0x78000000>;
> + };
> +
> + memory@600000000 {
> + device_type = "memory";
> + reg = <0x6 0x00000000 0x0 0x80000000>;
> + };
> +
> + aliases {
> + serial0 = &scif2;
> + };
> +
> + chosen {
> + bootargs = "ignore_loglevel";
Drop bootargs. Not a mainline DTS attribute. Why should my board ignore
loglevel? How is it hardware description?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 10/10] arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC sub board support
2026-08-21 15:03 [PATCH 00/10] Add support for Renesas RZ/G2M v3.0 (a.k.a R8A774A3) SoC Ayman Chaudhry
` (8 preceding siblings ...)
2026-08-21 15:03 ` [PATCH 09/10] arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC main board support Ayman Chaudhry
@ 2026-08-21 15:03 ` Ayman Chaudhry
9 siblings, 0 replies; 15+ messages in thread
From: Ayman Chaudhry @ 2026-08-21 15:03 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Stephen Boyd, Brian Masney, Jerome Brunet,
Ulf Hansson
Cc: Ayman Chaudhry, linux-renesas-soc, devicetree, linux-kernel,
linux-clk, linux-pm, Chris Paterson, Biju Das, Fabrizio Castro,
Lad Prabhakar
The HiHope RZ/G2M sub board sits below the HiHope RZ/G2M v3.0
(a.k.a. R8A774A3) SoC main board.
The RZ/G2M v3.0 SoC sub board is similar to the RZ/G2M v1.3 SoC sub
board, so there are already DTSI files available in the kernel. These
DTSI files will be included once additional support (e.g. CAN, PCIe
and ethernet) is added for the RZ/G2M v3.0 SoC.
Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com>
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
.../boot/dts/renesas/r8a774a3-hihope-rzg2m-ex.dts | 14 ++++++++++++++
2 files changed, 15 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m-ex.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 6ae96027664d..346670b10ada 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774A3) += r8a774a3-hihope-rzg2m.dtb
+dtb-$(CONFIG_ARCH_R8A774A3) += r8a774a3-hihope-rzg2m-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-beacon-rzg2n-kit.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m-ex.dts b/arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m-ex.dts
new file mode 100644
index 000000000000..fc46ce321d59
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m-ex.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2M v3.0 SoC sub board
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+#include "r8a774a3-hihope-rzg2m.dts"
+
+/ {
+ model = "HopeRun HiHope RZ/G2M v3.0 with sub board";
+ compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m",
+ "renesas,r8a774a3";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread