[PATCH v2 0/2] PCI: qcom: Add PCIe support for upcoming Hawi SoC

[PATCH v2 0/2] PCI: qcom: Add PCIe support for upcoming Hawi SoC

[Matthew Leung]

This series adds PCIe support for the Qualcomm Hawi SoC. The Hawi
platform features two PCIe controllers: one capable of Gen3 x2 operation
and one capable of Gen4 x1 operation. The first patch adds the device
tree bindings documentation for the Hawi PCIe controller, and the second
patch adds driver support by enabling the Hawi compatible string in the
existing qcom PCIe driver.

This series depends on the following series queued on linux-next:
- [PATCH v3 0/7] clk: qcom: Add initial clock controllers for the
  upcoming Hawi SoC (Change-ID: 20260316-clk-hawi-1ad4cad36d6a:v3)
- [PATCH v4 0/2] interconnect: qcom: Add support for upcoming Hawi SoC
  (Change-ID: 20260311-icc-hawi-d6dc165f8935:v4)

These provide the necessary headers for running dt_binding_check.

This series was rebased onto linux-next and applies cleanly without
additional prerequisites.

Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
Changes in v2:
- Rebased onto a newer linux-next snapshot
- Previously required dependency series are now queued on linux-next
- Added minItems constraint for clocks
- Moved description comments for clock-names, reg-names, and reset-names
  into 'description' entries in the devicetree bindings.
- Removed maxItems constraint for clocks, regs, resets for the fixed
  size 'items' list
- Link to v1: https://patch.msgid.link/20260508-hawi-pcie-v1-0-0c910906f7e5@oss.qualcomm.com

To: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Krzysztof Wilczyński <kwilczynski@kernel.org>
To: Manivannan Sadhasivam <mani@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Bjorn Andersson <andersson@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

---
Matthew Leung (2):
      dt-bindings: PCI: qcom: Document the Hawi PCIe Controller
      PCI: qcom: Add support for Hawi

 .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 204 +++++++++++++++++++++
 drivers/pci/controller/dwc/pcie-qcom.c             |   1 +
 2 files changed, 205 insertions(+)
---
base-commit: f7af91adc230aa99e23330ecf85bc9badd9780ad
change-id: 20260506-hawi-pcie-f61435ca420c

Best regards,
--  
Matthew Leung <matthew.leung@oss.qualcomm.com>

[PATCH v2 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[Matthew Leung]

Add a dedicated schema for the PCIe controllers found on the Hawi
platform.

Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
 .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 204 +++++++++++++++++++++
 1 file changed, 204 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
new file mode 100644
index 000000000000..7e47b8472af7
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
@@ -0,0 +1,204 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,hawi-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Hawi PCI Express Root Complex
+
+maintainers:
+  - Bjorn Andersson <andersson@kernel.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
+
+description:
+  Qualcomm Hawi SoC (and compatible) PCIe root complex controller is based on
+  the Synopsys DesignWare PCIe IP.
+
+properties:
+  compatible:
+    const: qcom,hawi-pcie
+
+  reg:
+    minItems: 5
+    items:
+      - description: Qualcomm specific registers
+      - description: DesignWare PCIe registers
+      - description: External local bus interface registers
+      - description: ATU address space
+      - description: PCIe configuration space
+      - description: MHI registers
+
+  reg-names:
+    minItems: 5
+    items:
+      - const: parf
+      - const: dbi
+      - const: elbi
+      - const: atu
+      - const: config
+      - const: mhi
+
+  clocks:
+    minItems: 6
+    items:
+      - description: PCIe Auxiliary clock
+      - description: PCIe Configuration clock
+      - description: PCIe Master AXI clock
+      - description: PCIe Slave AXI clock
+      - description: PCIe Slave Q2A AXI clock
+      - description: PCIe Aggre NoC AXI clock
+      - description: PCIe Config NoC AXI clock
+
+  clock-names:
+    minItems: 6
+    items:
+      - const: aux
+      - const: cfg
+      - const: bus_master
+      - const: bus_slave
+      - const: slave_q2a
+      - const: noc_aggr
+      - const: cnoc_sf_axi
+
+  interrupts:
+    minItems: 8
+    maxItems: 9
+
+  interrupt-names:
+    minItems: 8
+    items:
+      - const: msi0
+      - const: msi1
+      - const: msi2
+      - const: msi3
+      - const: msi4
+      - const: msi5
+      - const: msi6
+      - const: msi7
+      - const: global
+
+  resets:
+    minItems: 1
+    items:
+      - description: PCIe core reset
+      - description: PCIe link down reset
+
+  reset-names:
+    minItems: 1
+    items:
+      - const: pci
+      - const: link_down
+
+required:
+  - power-domains
+  - resets
+  - reset-names
+
+allOf:
+  - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,hawi-gcc.h>
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/interconnect/qcom,hawi-rpmh.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        pcie@1c00000 {
+            compatible = "qcom,hawi-pcie";
+            reg = <0 0x01c00000 0 0x3000>,
+                  <0 0x40000000 0 0xf1d>,
+                  <0 0x40000f20 0 0xa8>,
+                  <0 0x40001000 0 0x1000>,
+                  <0 0x40100000 0 0x100000>;
+            reg-names = "parf", "dbi", "elbi", "atu", "config";
+            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;
+
+            bus-range = <0x00 0xff>;
+            device_type = "pci";
+            linux,pci-domain = <0>;
+            num-lanes = <2>;
+
+            #address-cells = <3>;
+            #size-cells = <2>;
+
+            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+                     <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+                     <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
+            clock-names = "aux",
+                          "cfg",
+                          "bus_master",
+                          "bus_slave",
+                          "slave_q2a",
+                          "noc_aggr",
+                          "cnoc_sf_axi";
+
+            dma-coherent;
+
+            interrupts = <GIC_ESPI 205 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 206 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 207 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 208 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 209 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 210 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 211 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 212 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 204 IRQ_TYPE_LEVEL_HIGH>;
+            interrupt-names = "msi0", "msi1", "msi2", "msi3",
+                              "msi4", "msi5", "msi6", "msi7", "global";
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 0x7>;
+            interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                            <0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                            <0 0 0 3 &intc 0 0 GIC_ESPI 215 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                            <0 0 0 4 &intc 0 0 GIC_ESPI 216 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+            interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                            <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                             &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+            interconnect-names = "pcie-mem", "cpu-pcie";
+
+            iommu-map = <0x0 &apps_smmu 0x1000 0x1>,
+                        <0x100 &apps_smmu 0x1001 0x1>;
+
+            pinctrl-0 = <&pcie0_default_state>;
+            pinctrl-names = "default";
+
+            power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
+
+            resets = <&gcc GCC_PCIE_0_BCR>,
+                     <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
+            reset-names = "pci", "link_down";
+
+            msi-map = <0x0 &gic_its 0x1000 0x1>,
+                      <0x100 &gic_its 0x1001 0x1>;
+            msi-map-mask = <0xff00>;
+
+            pcie@0 {
+                device_type = "pci";
+                reg = <0x0 0x0 0x0 0x0 0x0>;
+                bus-range = <0x01 0xff>;
+
+                #address-cells = <3>;
+                #size-cells = <2>;
+                ranges;
+
+                phys = <&pcie0_phy>;
+                wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
+                reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+            };
+        };
+    };

-- 
2.34.1

Re: [PATCH v2 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[Krzysztof Kozlowski]

On Fri, May 29, 2026 at 01:10:08AM +0000, Matthew Leung wrote:
> Add a dedicated schema for the PCIe controllers found on the Hawi
> platform.
> 
> Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
> ---
>  .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 204 +++++++++++++++++++++

As replied to cover letter, cannot be tested by tooling, so dropping
from Patchwork.

Best regards,
Krzysztof

Re: [PATCH v2 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[Dmitry Baryshkov]

On Fri, May 29, 2026 at 01:10:08AM +0000, Matthew Leung wrote:
> Add a dedicated schema for the PCIe controllers found on the Hawi
> platform.
> 
> Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
> ---
>  .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 204 +++++++++++++++++++++
>  1 file changed, 204 insertions(+)
> 
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,hawi-gcc.h>
> +    #include <dt-bindings/gpio/gpio.h>
> +    #include <dt-bindings/interconnect/qcom,icc.h>
> +    #include <dt-bindings/interconnect/qcom,hawi-rpmh.h>

Stop referencing clocks and interconnect header files. Replace used nocs
with ephemeral values.

> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;

Not looking around should be a sin. Take a look at other Qualcomm PCIe
bindings. Compare them to yours. Then fix yours to follow.

Hint: the extra soc node is useless. This is just an example, so use the
default, 1 cells for address and size.

> +
> +        pcie@1c00000 {
> +            compatible = "qcom,hawi-pcie";
> +            reg = <0 0x01c00000 0 0x3000>,
> +                  <0 0x40000000 0 0xf1d>,
> +                  <0 0x40000f20 0 0xa8>,
> +                  <0 0x40001000 0 0x1000>,
> +                  <0 0x40100000 0 0x100000>;
> +            reg-names = "parf", "dbi", "elbi", "atu", "config";
> +            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> +                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;
> +
> +            bus-range = <0x00 0xff>;
> +            device_type = "pci";
> +            linux,pci-domain = <0>;
> +            num-lanes = <2>;
> +
> +            #address-cells = <3>;
> +            #size-cells = <2>;
> +
> +            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,

<&gcc_pcie_0_aux_clk>, etc.

> +                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> +                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> +                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> +                     <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
> +                     <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;

-- 
With best wishes
Dmitry

Re: [PATCH v2 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[Matthew Leung]

On Sun, Jun 07, 2026 at 11:01:10PM +0300, Dmitry Baryshkov wrote:
> On Fri, May 29, 2026 at 01:10:08AM +0000, Matthew Leung wrote:
> > Add a dedicated schema for the PCIe controllers found on the Hawi
> > platform.
> > 
> > Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
> > ---
> >  .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 204 +++++++++++++++++++++
> >  1 file changed, 204 insertions(+)
> > 
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/qcom,hawi-gcc.h>
> > +    #include <dt-bindings/gpio/gpio.h>
> > +    #include <dt-bindings/interconnect/qcom,icc.h>
> > +    #include <dt-bindings/interconnect/qcom,hawi-rpmh.h>
> 
> Stop referencing clocks and interconnect header files. Replace used nocs
> with ephemeral values.
> 
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +    soc {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> 
> Not looking around should be a sin. Take a look at other Qualcomm PCIe
> bindings. Compare them to yours. Then fix yours to follow.
> 
> Hint: the extra soc node is useless. This is just an example, so use the
> default, 1 cells for address and size.

Thank you for the feedback. This new binding follows the examples set in
the qcom,pcie-sm8x50 bindings and retains the same formatting (extra soc
node and header references).

I understand the example can be simplified with your suggestions but
want additional confirmation that these will be the convention for new
bindings going forward.

> 
> > +
> > +        pcie@1c00000 {
> > +            compatible = "qcom,hawi-pcie";
> > +            reg = <0 0x01c00000 0 0x3000>,
> > +                  <0 0x40000000 0 0xf1d>,
> > +                  <0 0x40000f20 0 0xa8>,
> > +                  <0 0x40001000 0 0x1000>,
> > +                  <0 0x40100000 0 0x100000>;
> > +            reg-names = "parf", "dbi", "elbi", "atu", "config";
> > +            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> > +                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;
> > +
> > +            bus-range = <0x00 0xff>;
> > +            device_type = "pci";
> > +            linux,pci-domain = <0>;
> > +            num-lanes = <2>;
> > +
> > +            #address-cells = <3>;
> > +            #size-cells = <2>;
> > +
> > +            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> 
> <&gcc_pcie_0_aux_clk>, etc.
> 
> > +                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> > +                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> > +                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> > +                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> > +                     <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
> > +                     <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
> 
> -- 
> With best wishes
> Dmitry

Re: [PATCH v2 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[Dmitry Baryshkov]

On Thu, Jun 11, 2026 at 06:17:57PM -0700, Matthew Leung wrote:
> On Sun, Jun 07, 2026 at 11:01:10PM +0300, Dmitry Baryshkov wrote:
> > On Fri, May 29, 2026 at 01:10:08AM +0000, Matthew Leung wrote:
> > > Add a dedicated schema for the PCIe controllers found on the Hawi
> > > platform.
> > > 
> > > Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
> > > ---
> > >  .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 204 +++++++++++++++++++++
> > >  1 file changed, 204 insertions(+)
> > > 
> > > +
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/clock/qcom,hawi-gcc.h>
> > > +    #include <dt-bindings/gpio/gpio.h>
> > > +    #include <dt-bindings/interconnect/qcom,icc.h>
> > > +    #include <dt-bindings/interconnect/qcom,hawi-rpmh.h>
> > 
> > Stop referencing clocks and interconnect header files. Replace used nocs
> > with ephemeral values.
> > 
> > > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +
> > > +    soc {
> > > +        #address-cells = <2>;
> > > +        #size-cells = <2>;
> > 
> > Not looking around should be a sin. Take a look at other Qualcomm PCIe
> > bindings. Compare them to yours. Then fix yours to follow.
> > 
> > Hint: the extra soc node is useless. This is just an example, so use the
> > default, 1 cells for address and size.
> 
> Thank you for the feedback. This new binding follows the examples set in
> the qcom,pcie-sm8x50 bindings and retains the same formatting (extra soc
> node and header references).

Hmm, interesting. Then I'm a sinner :-)

I looked at msm8996, but I didn't notice that the rest of the files use
the soc node (and match what you've sent). Please excuse me.

> 
> I understand the example can be simplified with your suggestions but
> want additional confirmation that these will be the convention for new
> bindings going forward.

At least, let's keep it for now. The other comment stands. To remove
dependencies please use ephemeral nodes instead of depending on DT
bindings from other subsystems.

> 
> > 
> > > +
> > > +        pcie@1c00000 {
> > > +            compatible = "qcom,hawi-pcie";
> > > +            reg = <0 0x01c00000 0 0x3000>,
> > > +                  <0 0x40000000 0 0xf1d>,
> > > +                  <0 0x40000f20 0 0xa8>,
> > > +                  <0 0x40001000 0 0x1000>,
> > > +                  <0 0x40100000 0 0x100000>;
> > > +            reg-names = "parf", "dbi", "elbi", "atu", "config";
> > > +            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> > > +                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;
> > > +
> > > +            bus-range = <0x00 0xff>;
> > > +            device_type = "pci";
> > > +            linux,pci-domain = <0>;
> > > +            num-lanes = <2>;
> > > +
> > > +            #address-cells = <3>;
> > > +            #size-cells = <2>;
> > > +
> > > +            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> > 
> > <&gcc_pcie_0_aux_clk>, etc.
> > 
> > > +                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> > > +                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> > > +                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> > > +                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> > > +                     <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
> > > +                     <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
> > 
> > -- 
> > With best wishes
> > Dmitry

-- 
With best wishes
Dmitry

Re: [PATCH v2 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[Matthew Leung]

On Fri, Jun 12, 2026 at 09:22:10AM +0300, Dmitry Baryshkov wrote:
> On Thu, Jun 11, 2026 at 06:17:57PM -0700, Matthew Leung wrote:
> > On Sun, Jun 07, 2026 at 11:01:10PM +0300, Dmitry Baryshkov wrote:
> > > On Fri, May 29, 2026 at 01:10:08AM +0000, Matthew Leung wrote:
> > > > Add a dedicated schema for the PCIe controllers found on the Hawi
> > > > platform.
> > > > 
> > > > Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
> > > > ---
> > > >  .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 204 +++++++++++++++++++++
> > > >  1 file changed, 204 insertions(+)
> > > > 
> > > > +
> > > > +examples:
> > > > +  - |
> > > > +    #include <dt-bindings/clock/qcom,hawi-gcc.h>
> > > > +    #include <dt-bindings/gpio/gpio.h>
> > > > +    #include <dt-bindings/interconnect/qcom,icc.h>
> > > > +    #include <dt-bindings/interconnect/qcom,hawi-rpmh.h>
> > > 
> > > Stop referencing clocks and interconnect header files. Replace used nocs
> > > with ephemeral values.
> > > 
> > > > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > +
> > > > +    soc {
> > > > +        #address-cells = <2>;
> > > > +        #size-cells = <2>;
> > > 
> > > Not looking around should be a sin. Take a look at other Qualcomm PCIe
> > > bindings. Compare them to yours. Then fix yours to follow.
> > > 
> > > Hint: the extra soc node is useless. This is just an example, so use the
> > > default, 1 cells for address and size.
> > 
> > Thank you for the feedback. This new binding follows the examples set in
> > the qcom,pcie-sm8x50 bindings and retains the same formatting (extra soc
> > node and header references).
> 
> Hmm, interesting. Then I'm a sinner :-)
> 
> I looked at msm8996, but I didn't notice that the rest of the files use
> the soc node (and match what you've sent). Please excuse me.

It's all good! :)

> 
> > 
> > I understand the example can be simplified with your suggestions but
> > want additional confirmation that these will be the convention for new
> > bindings going forward.
> 
> At least, let's keep it for now. The other comment stands. To remove
> dependencies please use ephemeral nodes instead of depending on DT
> bindings from other subsystems.

Agree. Will update in next version.

> 
> > 
> > > 
> > > > +
> > > > +        pcie@1c00000 {
> > > > +            compatible = "qcom,hawi-pcie";
> > > > +            reg = <0 0x01c00000 0 0x3000>,
> > > > +                  <0 0x40000000 0 0xf1d>,
> > > > +                  <0 0x40000f20 0 0xa8>,
> > > > +                  <0 0x40001000 0 0x1000>,
> > > > +                  <0 0x40100000 0 0x100000>;
> > > > +            reg-names = "parf", "dbi", "elbi", "atu", "config";
> > > > +            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> > > > +                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;
> > > > +
> > > > +            bus-range = <0x00 0xff>;
> > > > +            device_type = "pci";
> > > > +            linux,pci-domain = <0>;
> > > > +            num-lanes = <2>;
> > > > +
> > > > +            #address-cells = <3>;
> > > > +            #size-cells = <2>;
> > > > +
> > > > +            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> > > 
> > > <&gcc_pcie_0_aux_clk>, etc.
> > > 
> > > > +                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> > > > +                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> > > > +                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> > > > +                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> > > > +                     <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
> > > > +                     <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
> > > 
> > > -- 
> > > With best wishes
> > > Dmitry
> 
> -- 
> With best wishes
> Dmitry

Re: [PATCH v2 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[Manivannan Sadhasivam]

On Fri, Jun 12, 2026 at 09:22:10AM +0300, Dmitry Baryshkov wrote:
> On Thu, Jun 11, 2026 at 06:17:57PM -0700, Matthew Leung wrote:
> > On Sun, Jun 07, 2026 at 11:01:10PM +0300, Dmitry Baryshkov wrote:
> > > On Fri, May 29, 2026 at 01:10:08AM +0000, Matthew Leung wrote:
> > > > Add a dedicated schema for the PCIe controllers found on the Hawi
> > > > platform.
> > > > 
> > > > Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
> > > > ---
> > > >  .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 204 +++++++++++++++++++++
> > > >  1 file changed, 204 insertions(+)
> > > > 
> > > > +
> > > > +examples:
> > > > +  - |
> > > > +    #include <dt-bindings/clock/qcom,hawi-gcc.h>
> > > > +    #include <dt-bindings/gpio/gpio.h>
> > > > +    #include <dt-bindings/interconnect/qcom,icc.h>
> > > > +    #include <dt-bindings/interconnect/qcom,hawi-rpmh.h>
> > > 
> > > Stop referencing clocks and interconnect header files. Replace used nocs
> > > with ephemeral values.
> > > 
> > > > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > +
> > > > +    soc {
> > > > +        #address-cells = <2>;
> > > > +        #size-cells = <2>;
> > > 
> > > Not looking around should be a sin. Take a look at other Qualcomm PCIe
> > > bindings. Compare them to yours. Then fix yours to follow.
> > > 
> > > Hint: the extra soc node is useless. This is just an example, so use the
> > > default, 1 cells for address and size.
> > 
> > Thank you for the feedback. This new binding follows the examples set in
> > the qcom,pcie-sm8x50 bindings and retains the same formatting (extra soc
> > node and header references).
> 
> Hmm, interesting. Then I'm a sinner :-)
> 
> I looked at msm8996, but I didn't notice that the rest of the files use
> the soc node (and match what you've sent). Please excuse me.
> 

Stop looking at MSM8996 and have some compassion for newer SoCs ;)

> > 
> > I understand the example can be simplified with your suggestions but
> > want additional confirmation that these will be the convention for new
> > bindings going forward.
> 
> At least, let's keep it for now. The other comment stands. To remove
> dependencies please use ephemeral nodes instead of depending on DT
> bindings from other subsystems.
> 

Agree. Since this series missed 7.2 merge window, the dependency won't matter
now. But for the sake of correctness, we should use ephemeral nodes going
forward.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v2 2/2] PCI: qcom: Add support for Hawi

[Matthew Leung]

Add support for the Hawi platform which has two PCIe controllers: one
capable of Gen3 x2 operation and one capable of Gen4 x1 operation.

Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 11fc60489892..5fe8667fdb8f 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -2280,6 +2280,7 @@ static int qcom_pcie_resume_noirq(struct device *dev)
 }
 
 static const struct of_device_id qcom_pcie_match[] = {
+	{ .compatible = "qcom,hawi-pcie", .data = &cfg_1_9_0 },
 	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
 	{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },

-- 
2.34.1

Re: [PATCH v2 2/2] PCI: qcom: Add support for Hawi

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [Medium] The compatible string `qcom,hawi-pcie` violates the established Qualcomm PCIe naming convention and fails to differentiate between distinct controller instances.

Pre-existing issues:
- [High] Missing hardware readback before disabling clocks in qcom_pcie_deinit_2_7_0() can cause bus lockups.
- [High] Out-of-bounds memory read when parsing a malformed 'iommu-map' property in qcom_pcie_config_sid_1_9_0().
--

commit d9d16f2083b5ca557a88fe9cb78cb5c885342df2
Author: Matthew Leung <matthew.leung@oss.qualcomm.com>

PCI: qcom: Add support for Hawi

Add support for the Hawi platform which has two PCIe controllers: one
capable of Gen3 x2 operation and one capable of Gen4 x1 operation.

> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 11fc604898926..5fe8667fdb8f5 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -2280,6 +2280,7 @@ static int qcom_pcie_resume_noirq(struct device *dev)
>  }
>  
>  static const struct of_device_id qcom_pcie_match[] = {
> +	{ .compatible = "qcom,hawi-pcie", .data = &cfg_1_9_0 },

[Severity: Medium]
Since the commit message notes the platform has two controllers with differing
capabilities, is it intentional to use a single compatible string rather than
instance-specific ones?

Modern Qualcomm platforms typically use instance-specific compatibles like
qcom,pcie-sm8450-pcie0 and qcom,pcie-sm8450-pcie1 to manage differences in
interconnects, link speeds, and quirks. Lumping them under a single
compatible might prevent the driver from differentiating the controllers.

Additionally, the new compatible string reverses the established
qcom,pcie-<platform> naming pattern.

[ ... ]

[Severity: High]
This isn't a bug introduced by this patch, but I noticed a potential bus lockup
risk here:

drivers/pci/controller/dwc/pcie-qcom.c:qcom_pcie_deinit_2_7_0() {
    ...
	val = readl(pcie->parf + PARF_PHY_CTRL);
	val |= PHY_TEST_PWR_DOWN;
	writel(val, pcie->parf + PARF_PHY_CTRL);

	clk_bulk_disable_unprepare(res->num_clks, res->clks);
    ...
}

Because writel() performs a posted write, there is no guarantee that the
transaction has reached the peripheral before the clocks are removed.
Disabling the clock while a write is still propagating over the interconnect
can result in a lost write or a fatal bus lockup.

Does this need a hardware readback after the writel() to ensure completion
before disabling the clocks?

[Severity: High]
This is a pre-existing issue, but could this code cause an out-of-bounds
memory read when parsing a malformed iommu-map property?

drivers/pci/controller/dwc/pcie-qcom.c:qcom_pcie_config_sid_1_9_0() {
    ...
	of_get_property(dev->of_node, "iommu-map", &size);
	if (!size)
		return 0;
    ...
	map = kzalloc(size, GFP_KERNEL);
	if (!map)
		return -ENOMEM;

	of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map,
				   size / sizeof(u32));
    ...
	smmu_sid_base = map[0].smmu_sid;
    ...
}

If the iommu-map property is present but smaller than the size of one entry,
kzalloc() allocates only that small size. The code then unconditionally
accesses map[0].smmu_sid, which resides at offset 8.

Would this cause an out-of-bounds memory read from the heap, potentially
triggering a kernel panic if the buffer is at the end of a slab page?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260529-hawi-pcie-v2-0-de87c6cc230c@oss.qualcomm.com?part=2

Re: [PATCH v2 0/2] PCI: qcom: Add PCIe support for upcoming Hawi SoC

[Krzysztof Kozlowski]

On Fri, May 29, 2026 at 01:10:07AM +0000, Matthew Leung wrote:
> This series adds PCIe support for the Qualcomm Hawi SoC. The Hawi
> platform features two PCIe controllers: one capable of Gen3 x2 operation
> and one capable of Gen4 x1 operation. The first patch adds the device
> tree bindings documentation for the Hawi PCIe controller, and the second
> patch adds driver support by enabling the Hawi compatible string in the
> existing qcom PCIe driver.
> 
> This series depends on the following series queued on linux-next:
> - [PATCH v3 0/7] clk: qcom: Add initial clock controllers for the
>   upcoming Hawi SoC (Change-ID: 20260316-clk-hawi-1ad4cad36d6a:v3)
> - [PATCH v4 0/2] interconnect: qcom: Add support for upcoming Hawi SoC
>   (Change-ID: 20260311-icc-hawi-d6dc165f8935:v4)

It cannot depend there it makes it unmergeable and untestable. I skip
review in such case, please follow standard documented practices about
decoupling independent works.

Best regards,
Krzysztof

Re: [PATCH v2 0/2] PCI: qcom: Add PCIe support for upcoming Hawi SoC

[Matthew Leung]

On 5/30/2026 3:06 AM, Krzysztof Kozlowski wrote:
> On Fri, May 29, 2026 at 01:10:07AM +0000, Matthew Leung wrote:
>> This series adds PCIe support for the Qualcomm Hawi SoC. The Hawi
>> platform features two PCIe controllers: one capable of Gen3 x2 operation
>> and one capable of Gen4 x1 operation. The first patch adds the device
>> tree bindings documentation for the Hawi PCIe controller, and the second
>> patch adds driver support by enabling the Hawi compatible string in the
>> existing qcom PCIe driver.
>>
>> This series depends on the following series queued on linux-next:
>> - [PATCH v3 0/7] clk: qcom: Add initial clock controllers for the
>>   upcoming Hawi SoC (Change-ID: 20260316-clk-hawi-1ad4cad36d6a:v3)
>> - [PATCH v4 0/2] interconnect: qcom: Add support for upcoming Hawi SoC
>>   (Change-ID: 20260311-icc-hawi-d6dc165f8935:v4)
> 
> It cannot depend there it makes it unmergeable and untestable. I skip
> review in such case, please follow standard documented practices about
> decoupling independent works.

Thanks for the feedback. On checking the dependencies, the changes are
applied in their respective maintainer trees:
- clk: applied to qcom/linux.git for-next, commit d6cd9d5692ba
- icc: applied to djakov/icc.git icc-next, commit 07548b04dc36

Both commits are present in my linux-next base-commit and have checked
dt_binding_check passes cleanly.

I can resend with the dependency references updated accordingly.

> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v2 0/2] PCI: qcom: Add PCIe support for upcoming Hawi SoC

[Manivannan Sadhasivam]

On Wed, 3 Jun 2026 01:26:53 +0200, Matthew Leung
<matthew.leung@oss.qualcomm.com> said:
>
>
> On 5/30/2026 3:06 AM, Krzysztof Kozlowski wrote:
>> On Fri, May 29, 2026 at 01:10:07AM +0000, Matthew Leung wrote:
>>> This series adds PCIe support for the Qualcomm Hawi SoC. The Hawi
>>> platform features two PCIe controllers: one capable of Gen3 x2 operation
>>> and one capable of Gen4 x1 operation. The first patch adds the device
>>> tree bindings documentation for the Hawi PCIe controller, and the second
>>> patch adds driver support by enabling the Hawi compatible string in the
>>> existing qcom PCIe driver.
>>>
>>> This series depends on the following series queued on linux-next:
>>> - [PATCH v3 0/7] clk: qcom: Add initial clock controllers for the
>>>   upcoming Hawi SoC (Change-ID: 20260316-clk-hawi-1ad4cad36d6a:v3)
>>> - [PATCH v4 0/2] interconnect: qcom: Add support for upcoming Hawi SoC
>>>   (Change-ID: 20260311-icc-hawi-d6dc165f8935:v4)
>>
>> It cannot depend there it makes it unmergeable and untestable. I skip
>> review in such case, please follow standard documented practices about
>> decoupling independent works.
>
> Thanks for the feedback. On checking the dependencies, the changes are
> applied in their respective maintainer trees:
> - clk: applied to qcom/linux.git for-next, commit d6cd9d5692ba
> - icc: applied to djakov/icc.git icc-next, commit 07548b04dc36
>
> Both commits are present in my linux-next base-commit and have checked
> dt_binding_check passes cleanly.
>
> I can resend with the dependency references updated accordingly.
>

No. It will still break the pci tree when this series gets merged. Please
resubmit after v7.2-rc1.

- Mani

Re: [PATCH v2 0/2] PCI: qcom: Add PCIe support for upcoming Hawi SoC

[Matthew Leung]

On 6/4/2026 5:09 AM, Manivannan Sadhasivam wrote:
> On Wed, 3 Jun 2026 01:26:53 +0200, Matthew Leung
> <matthew.leung@oss.qualcomm.com> said:
>>
>>
>> On 5/30/2026 3:06 AM, Krzysztof Kozlowski wrote:
>>> On Fri, May 29, 2026 at 01:10:07AM +0000, Matthew Leung wrote:
>>>> This series adds PCIe support for the Qualcomm Hawi SoC. The Hawi
>>>> platform features two PCIe controllers: one capable of Gen3 x2 operation
>>>> and one capable of Gen4 x1 operation. The first patch adds the device
>>>> tree bindings documentation for the Hawi PCIe controller, and the second
>>>> patch adds driver support by enabling the Hawi compatible string in the
>>>> existing qcom PCIe driver.
>>>>
>>>> This series depends on the following series queued on linux-next:
>>>> - [PATCH v3 0/7] clk: qcom: Add initial clock controllers for the
>>>>   upcoming Hawi SoC (Change-ID: 20260316-clk-hawi-1ad4cad36d6a:v3)
>>>> - [PATCH v4 0/2] interconnect: qcom: Add support for upcoming Hawi SoC
>>>>   (Change-ID: 20260311-icc-hawi-d6dc165f8935:v4)
>>>
>>> It cannot depend there it makes it unmergeable and untestable. I skip
>>> review in such case, please follow standard documented practices about
>>> decoupling independent works.
>>
>> Thanks for the feedback. On checking the dependencies, the changes are
>> applied in their respective maintainer trees:
>> - clk: applied to qcom/linux.git for-next, commit d6cd9d5692ba
>> - icc: applied to djakov/icc.git icc-next, commit 07548b04dc36
>>
>> Both commits are present in my linux-next base-commit and have checked
>> dt_binding_check passes cleanly.
>>
>> I can resend with the dependency references updated accordingly.
>>
> 
> No. It will still break the pci tree when this series gets merged. Please
> resubmit after v7.2-rc1.

Okay, I will resubmit after the dependencies merge on mainline.

> 
> - Mani