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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Santhosh Kumar K <s-k6@ti.com>
Cc: Mark Brown <broonie@kernel.org>,  <robh@kernel.org>,
	<krzk+dt@kernel.org>,  <conor+dt@kernel.org>,  <richard@nod.at>,
	<vigneshr@ti.com>,  <pratyush@kernel.org>,  <mwalle@kernel.org>,
	<takahiro.kuwano@infineon.com>,  <linux-spi@vger.kernel.org>,
	<devicetree@vger.kernel.org>,  <linux-kernel@vger.kernel.org>,
	<linux-mtd@lists.infradead.org>,  <praneeth@ti.com>,
	<sebin.francis@ti.com>,  <u-kumar1@ti.com>,  <a-dutta@ti.com>
Subject: Re: [PATCH v9 08/18] spi: cadence-quadspi: add PHY tuning support
Date: Thu, 03 Sep 2026 10:16:28 +0200	[thread overview]
Message-ID: <875x0m7ns3.fsf@bootlin.com> (raw)
In-Reply-To: <ebf61988-9fe6-495b-b1e2-eaeba9f6b98f@ti.com> (Santhosh Kumar K.'s message of "Wed, 2 Sep 2026 15:15:24 +0530")

Hi Santhosh,

> The DQS bit in CQSPI_REG_READCAPTURE is used for read data capture and
> it's not consulted during writes.

In the end, how do you know you can expect a DQS signal during reads?
Will that work if the chip does not enable it? I still do not understand
how this can work.

Thanks,
Miquèl

  reply	other threads:[~2026-09-03  8:16 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-25 17:17 [PATCH v9 00/18] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 01/18] spi: dt-bindings: add spi-max-post-config-frequency-hz property Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 02/18] spi: dt-bindings: add spi-phy-pattern-partition property Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 03/18] spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz Santhosh Kumar K
2026-08-25 17:30   ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 04/18] spi: spi-mem: teach spi_mem_adjust_op_freq() about post-config ops Santhosh Kumar K
2026-08-25 17:30   ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 05/18] spi: spi-mem: add execute_tuning callback and spi_mem_execute_tuning() Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 06/18] spi: cadence-quadspi: move cqspi_readdata_capture earlier Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 07/18] spi: cadence-quadspi: add DQS support to read data capture Santhosh Kumar K
2026-08-25 17:29   ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 08/18] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-08-25 17:40   ` sashiko-bot
2026-08-26 21:43   ` Mark Brown
2026-09-02  9:45     ` Santhosh Kumar K
2026-09-03  8:16       ` Miquel Raynal [this message]
2026-08-25 17:17 ` [PATCH v9 09/18] spi: cadence-quadspi: skip DDR PHY tuning for 2-byte-address ops (i2383) Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 10/18] spi: cadence-quadspi: refactor direct read path for PHY support Santhosh Kumar K
2026-08-25 17:31   ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 11/18] spi: cadence-quadspi: enable PHY for direct reads Santhosh Kumar K
2026-08-25 17:32   ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 12/18] spi: cadence-quadspi: enable PHY for indirect writes Santhosh Kumar K
2026-08-25 17:32   ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 13/18] spi: cadence-quadspi: reprogram CS timing on every chip-select switch Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 14/18] spi: cadence-quadspi: reprogram PHY DLL on runtime resume Santhosh Kumar K
2026-08-25 17:36   ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 15/18] mtd: spinand: extract variant ranking logic into spinand_op_find_best_variant() Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 16/18] mtd: spinand: negotiate optimal controller operating point before dirmap creation Santhosh Kumar K
2026-08-25 17:43   ` sashiko-bot
2026-08-25 17:17 ` [PATCH v9 17/18] mtd: spi-nor: extract read op template construction into helper Santhosh Kumar K
2026-08-25 17:17 ` [PATCH v9 18/18] mtd: spi-nor: run controller optimization before dirmap creation Santhosh Kumar K
2026-08-25 17:45   ` sashiko-bot

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