* [PATCH v3 0/2] Add device tree support for NXP i.MX95 15x15 FRDM board
From: Lei Xu @ 2026-01-16 8:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, justin.jiang,
qijian.guo, lei.xu, Krzysztof Kozlowski, Daniel Baluta,
Laurentiu Mihalcea
The NXP i.MX95 15x15 FRDM board is a compact and cost-effective
development board based on the i.MX95 applications processor.
This patch set adds device tree support for the board:
- Patch 1 introduces the DT compatible string.
- Patch 2 provides the complete device tree description.
Signed-off-by: Lei Xu <lei.xu@nxp.com>
---
Changes in v3:
- Add a blank line between the cpu and codec node definitions.
- Link to v2: https://lore.kernel.org/r/20251217-127-v2-0-67cb12e56242@nxp.com
Changes in v2:
- Switched from 'xceiver-supply' to CAN PHY nodes using 'phys'.
- Added CAN PHY nodes for flexcan2/5 with shared silent-gpio, removed reg_can_stby.
- Updated MSI/IOMMU mapping comment to match the i.MX95 15x15 FRDM board.
Link to v1: https://lore.kernel.org/r/20251207-127-v1-0-5a2eeb69f150@nxp.com
---
Lei Xu (2):
dt-bindings: arm: fsl: Add compatible for i.MX95 15x15 FRDM board
arm64: dts: freescale: imx95: Add support for i.MX95 15x15 FRDM board
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts | 964 +++++++++++++++++++++
3 files changed, 966 insertions(+)
---
base-commit: 6987d58a9cbc5bd57c983baa514474a86c945d56
change-id: 20251207-127-4e8551e8bdaf
Best regards,
--
Lei Xu <lei.xu@nxp.com>
^ permalink raw reply
* Re: [PATCH v3 2/5] dt-bindings: i2c: qcom-cci: Document sm6150 compatible
From: Krzysztof Kozlowski @ 2026-01-16 8:54 UTC (permalink / raw)
To: Wenmeng Liu
Cc: Loic Poulain, Andi Shyti, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Robert Foss,
Todor Tomov, Bryan O'Donoghue, Vladimir Zapolskiy, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, linux-i2c,
linux-arm-msm, devicetree, linux-kernel, linux-media, imx,
linux-arm-kernel
In-Reply-To: <025cefd3-888b-4744-bde3-2d5c007db66f@oss.qualcomm.com>
On 16/01/2026 09:34, Wenmeng Liu wrote:
>
>
> On 1/16/2026 4:28 PM, Krzysztof Kozlowski wrote:
>> On Thu, Jan 15, 2026 at 06:12:38PM +0800, Wenmeng Liu wrote:
>>> Add the sm6150 CCI device string compatible.
>>>
>>> SM6150 include three clock:
>>> bus: Bus clock responsible for data transfer.
>>> iface: Interface clock responsible for register read and write.
>>> cci: Clock for CCI core operations.
>>>
>>> Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
>>> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
>>> ---
>>> .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 18 ++++++++++++++++++
>>> 1 file changed, 18 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>>> index a3fe1eea6aece9685674feaa5ec53765c1ce23d8..3472670fdc908ef8f3b3afc68ff437c0435b69a7 100644
>>> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>>> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>>> @@ -33,6 +33,7 @@ properties:
>>> - qcom,sc8280xp-cci
>>> - qcom,sdm670-cci
>>> - qcom,sdm845-cci
>>> + - qcom,sm6150-cci
>>> - qcom,sm6350-cci
>>> - qcom,sm8250-cci
>>> - qcom,sm8450-cci
>>> @@ -263,6 +264,23 @@ allOf:
>>> - const: cpas_ahb
>>> - const: cci
>>>
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + enum:
>>> + - qcom,sm6150-cci
>>> + then:
>>> + properties:
>>> + clocks:
>>> + minItems: 3
>>> + maxItems: 3
>>> + clock-names:
>>> + items:
>>> + - const: bus
>>> + - const: iface
>>> + - const: cci
>>
>> So basically the same as camnoc_axi+cpas_ahb+cci, so just put it into
>> existing enum with qcom,sm8550-cci.
>>
>> I asked for this at v1.
>> https://lore.kernel.org/all/43efa6fd-53c3-4680-8aca-7b37089ca295@kernel.org/
>>
>>
>> Best regards,
>> Krzysztof
>>
> I raised this question in the previous version.
> And got reply as:
And I asked to integrate them into existing names at v1. So we have v2
which did not do it, v3 now and your patches are still not reviewed :/
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 3/8] dt-bindings: mfd: Add Google GS101 TMU Syscon
From: Tudor Ambarus @ 2026-01-16 8:50 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lee Jones,
Alim Akhtar, Peter Griffin, André Draszik,
Bartlomiej Zolnierkiewicz, Kees Cook, Gustavo A. R. Silva,
willmcvicker, jyescas, shin.son, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-hardening
In-Reply-To: <fcc5405e-189d-4195-8db0-3acf35bbc0a9@linaro.org>
On 1/15/26 6:10 PM, Tudor Ambarus wrote:
>>> I'm going to link the ACPM TMU child node with the TMU node via a
>>> "samsung,tmu-regs" property.
>> This could be fine, but I actually wonder what's there. What registers
>> exactly. For example modern Exynos 88xx, already with APM block, still
>> have exactly the same TMU unit at 0x1008{04}000 with all typical
>> triminfo, current temperature and thresholds.
>>
> It's the same for gs101, the TMU instances have all the typical registers,
> it's just that everything is handled via ACPM but the intpend registers.
I could still use some guidance, Krzysztof, thanks for the help so far!
Based on the current feedback I was going to propose the following
description:
soc: soc@0 {
tmu_top: thermal-sensor@100a0000 {
compatible = "google,gs101-tmu-top";
reg = <0x100a0000 0x800>;
clocks = <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>;
interrupts = <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH 0>;
};
};
firmware {
acpm_ipc: power-management {
compatible = "google,gs101-acpm-ipc";
thermal-sensor {
compatible = "google,gs101-acpm-tmu-top";
samsung,tmu = <&tmu_top>;
#thermal-sensor-cells = <1>;
};
};
};
GS101 handles the thermal sensors in a hybrid way: it uses the TMU IP
block to read the INTPEND registers, and everything else is handled via
ACPM calls. There's also the abstraction that one ACPM sensor is comprised
of multiple physical TMU sensors.
My concern now is that the ACPM TMU child node is not hardware per se,
but just a firmware abstraction (One-to-Many sensors).
If everything was handled via ACPM, without the need to read the TMU's
INTPEND registers directly, I would have describe the sensor just as an
ACPM child.
Because of the hybrid approach I'm arguing the ACPM child node does not
fully describe the hardware, and it's just a firmware abstraction.
So option 2/ would be to have just the TMU IP block described with a
phandle to the ACPM IPC:
soc: soc@0 {
tmu@100a0000 {
compatible = "google,gs101-tmu-top";
reg = <0x100a0000 0x800>;
clocks = <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>;
interrupts = <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH 0>;
/* The "Firmware Phandle" approach */
samsung,acpm-ipc = <&acpm_ipc>;
#thermal-sensor-cells = <1>;
};
};
Which one do you think it better describes the hardware?
Thanks!
ta
^ permalink raw reply
* Re: Re: [PATCH v7 2/2] phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver
From: Yulin Lu @ 2026-01-16 8:50 UTC (permalink / raw)
To: Vinod Koul
Cc: neil.armstrong, robh, krzk+dt, conor+dt, p.zabel, linux-phy,
devicetree, linux-kernel, ningyu, zhengyu, linmin, huangyifeng,
fenglin, lianghujun
In-Reply-To: <aWeH5fn8nGOzjDpP@vaman>
> > +static int eic7700_sata_phy_init(struct phy *phy)
> > +{
> > + struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy);
> > + u32 val;
> > + int ret;
> > +
> > + ret = clk_prepare_enable(sata_phy->clk);
> > + if (ret)
> > + return ret;
> > +
> > + regmap_write(sata_phy->regmap, SATA_REF_CTRL1, SATA_CLK_RST_SOURCE_PHY);
> > +
> > + val = FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK, 0x42) |
> > + FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK, 0x46) |
> > + FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK, 0x73);
> > + regmap_write(sata_phy->regmap, SATA_PHY_CTRL0, val);
> > +
> > + val = FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN1_MASK, 0x5) |
> > + FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN2_MASK, 0x5) |
> > + FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN3_MASK, 0x8);
>
> Where are the magic values you are writing coming from..?
>
Hi Vinod,
These values set the TX preemphasis and amplitude parameters for the SATA PHY.
The actual numbers come from eye‑diagram tuning results on different hardware
development boards.
The current code reflects the settings for the Sifive HiFive Premier P550 board.
In the next patch I plan to move these into the devicetree (DTS).
Would that be acceptable?
> > + regmap_write(sata_phy->regmap, SATA_PHY_CTRL1, val);
> > +
> > + val = FIELD_PREP(SATA_LOS_LEVEL_MASK, 0x9) |
> > + FIELD_PREP(SATA_LOS_BIAS_MASK, 0x2);
> > + regmap_write(sata_phy->regmap, SATA_LOS_IDEN, val);
> > +
> > + val = SATA_M_CSYSREQ | SATA_S_CSYSREQ;
> > + regmap_write(sata_phy->regmap, SATA_AXI_LP_CTRL, val);
> > +
> > + val = SATA_REF_REPEATCLK_EN | SATA_REF_USE_PAD;
> > + regmap_write(sata_phy->regmap, SATA_REF_CTRL, val);
> > +
> > + val = FIELD_PREP(SATA_MPLL_MULTIPLIER_MASK, 0x3c);
> > + regmap_write(sata_phy->regmap, SATA_MPLL_CTRL, val);
> > +
> > + usleep_range(15, 20);
> > +
> > + ret = reset_control_deassert(sata_phy->rst);
> > + if (ret)
> > + goto disable_clk;
> > +
> > + ret = wait_for_phy_ready(sata_phy->regmap, SATA_P0_PHY_STAT,
> > + SATA_P0_PHY_READY, 1);
> > + if (ret < 0) {
> > + dev_err(&sata_phy->phy->dev, "PHY READY check failed\n");
> > + goto disable_clk;
> > + }
> > +
> > + return 0;
> > +
> > +disable_clk:
> > + clk_disable_unprepare(sata_phy->clk);
> > + return ret;
> > +}
> > +
> > +static int eic7700_sata_phy_exit(struct phy *phy)
> > +{
> > + struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy);
> > + int ret;
> > +
> > + ret = reset_control_assert(sata_phy->rst);
> > + if (ret)
> > + return ret;
> > +
> > + clk_disable_unprepare(sata_phy->clk);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct phy_ops eic7700_sata_phy_ops = {
> > + .init = eic7700_sata_phy_init,
> > + .exit = eic7700_sata_phy_exit,
> > + .owner = THIS_MODULE,
> > +};
> > +
> > +static int eic7700_sata_phy_probe(struct platform_device *pdev)
> > +{
> > + struct eic7700_sata_phy *sata_phy;
> > + struct phy_provider *phy_provider;
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + void __iomem *regs;
> > +
> > + sata_phy = devm_kzalloc(dev, sizeof(*sata_phy), GFP_KERNEL);
> > + if (!sata_phy)
> > + return -ENOMEM;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res)
> > + return -ENOENT;
> > +
> > + regs = devm_ioremap(dev, res->start, resource_size(res));
> > + if (IS_ERR(regs))
> > + return PTR_ERR(regs);
>
> devm_platform_get_and_ioremap_resource() please
>
As explained in my “v6 → v5” changes in the cover‑letter:
“Map the I/O resource with platform_get_resource and devm_ioremap
instead of the devm_platform_ioremap_resource API,
because the address region of the SATA‑PHY falls into the region of
the HSP clock & reset that has already been obtained by the HSP
clock‑and‑reset driver.”
The HSP clock-and-reset driver uses devm_platform_get_and_ioremap_resource(),
meaning this region has already been requested.
The HSP clock-and-reset driver is also currently being upstreamed.
Best regards,
Yulin Lu
^ permalink raw reply
* Re: [PATCH v2 2/3] media: dt-bindings: venus: Fix iommus property
From: Krzysztof Kozlowski @ 2026-01-16 8:47 UTC (permalink / raw)
To: Sumit Garg
Cc: linux-arm-msm, devicetree, andersson, konradybcio, robh, krzk+dt,
conor+dt, akhilpo, vikash.garodia, dikshita.agarwal, robin.clark,
lumag, loic.poulain, jorge.ramirez, linux-kernel, Sumit Garg
In-Reply-To: <20260116062004.237356-3-sumit.garg@kernel.org>
On Fri, Jan 16, 2026 at 11:50:03AM +0530, Sumit Garg wrote:
> From: Sumit Garg <sumit.garg@oss.qualcomm.com>
>
> Fix IOMMU DT propety for venus via dropping SMMU stream IDs which
> relates to secure context bank. Assigning Linux kernel (HLOS) VMID
> to secure context bank stream IDs is incorrect.
>
> The min value is added for iommus property to ensure in future when
You do not add min value (that would be "minimum") but change the list.
> secure context bank stream IDs are properly supported then the iommus
> property is extensible.
>
> These DT bindings changes should be backwards compatible.
>
> Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
> ---
> .../devicetree/bindings/media/qcom,qcm2290-venus.yaml | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml
> index 3f3ee82fc878..ae6bc0d0bea6 100644
> --- a/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml
> +++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml
> @@ -42,6 +42,7 @@ properties:
> - const: vcodec0_bus
>
> iommus:
> + minItems: 2
Same problem.
> maxItems: 5
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: display: msm: qcm2290-mdss: Fix iommus property
From: Krzysztof Kozlowski @ 2026-01-16 8:46 UTC (permalink / raw)
To: Sumit Garg
Cc: linux-arm-msm, devicetree, andersson, konradybcio, robh, krzk+dt,
conor+dt, akhilpo, vikash.garodia, dikshita.agarwal, robin.clark,
lumag, loic.poulain, jorge.ramirez, linux-kernel, Sumit Garg
In-Reply-To: <20260116062004.237356-2-sumit.garg@kernel.org>
On Fri, Jan 16, 2026 at 11:50:02AM +0530, Sumit Garg wrote:
> From: Sumit Garg <sumit.garg@oss.qualcomm.com>
>
> Fix IOMMU DT propety for display via dropping SMMU stream IDs which
> relates to secure context bank. Assigning Linux kernel (HLOS) VMID
> to secure context bank stream IDs is incorrect.
>
> The min value is added for iommus property to ensure in future when
> secure context bank stream IDs are properly supported then the iommus
> property is extensible.
>
> These DT bindings changes should be backwards compatible.
>
> Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
> ---
> .../devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
> index f0cdb5422688..5c888f07bc0b 100644
> --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
> @@ -33,6 +33,7 @@ properties:
> - const: core
>
> iommus:
> + minItems: 1
Same comment as other changes like that, which I already gave guideline
- you need to list the items (minItems stay), because you now claim the
order matters and is strictly defined.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: remoteproc: mediatek: Remove l1tcm MMIO from MT8188 dual
From: Krzysztof Kozlowski @ 2026-01-16 8:40 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: devicetree, andersson, mathieu.poirier, robh, krzk+dt, conor+dt,
matthias.bgg, tinghan.shen, olivia.wen, linux-remoteproc,
linux-kernel, linux-arm-kernel, linux-mediatek, kernel
In-Reply-To: <20260115111645.63295-1-angelogioacchino.delregno@collabora.com>
On Thu, Jan 15, 2026 at 12:16:45PM +0100, AngeloGioacchino Del Regno wrote:
> reg-names:
> - minItems: 2
> + minItems: 1
> maxItems: 3
>
> clocks:
> @@ -185,7 +185,7 @@ allOf:
> then:
> properties:
> reg:
> - maxItems: 3
> + minItems: 3
> reg-names:
> items:
> - const: sram
I think you also need to update the if:then: section with
mediatek,mt8183-scp+mediatek,mt8186-scp+mediatek,mt8188-scp
> @@ -196,11 +196,22 @@ allOf:
> compatible:
> enum:
> - mediatek,mt8188-scp-dual
> + then:
> + properties:
> + reg:
> + maxItems: 1
> + reg-names:
> + items:
> + - const: cfg
> + - if:
> + properties:
> + compatible:
> + enum:
> - mediatek,mt8195-scp-dual
> then:
> properties:
> reg:
> - maxItems: 2
> + minItems: 2
You still need maxItems here, otherwise you change the meaning to 2-3.
> reg-names:
> items:
> - const: cfg
> --
> 2.52.0
>
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: qcom: agatti: Fix IOMMU DT properties
From: Dmitry Baryshkov @ 2026-01-16 8:40 UTC (permalink / raw)
To: Sumit Garg
Cc: linux-arm-msm, devicetree, andersson, konradybcio, robh, krzk+dt,
conor+dt, akhilpo, vikash.garodia, dikshita.agarwal, robin.clark,
lumag, loic.poulain, jorge.ramirez, linux-kernel, Sumit Garg,
Prakash Gupta, Konrad Dybcio
In-Reply-To: <20260116062004.237356-4-sumit.garg@kernel.org>
On Fri, Jan 16, 2026 at 11:50:04AM +0530, Sumit Garg wrote:
> From: Sumit Garg <sumit.garg@oss.qualcomm.com>
>
> Fix IOMMU DT propeties for GPU, display and video peripherals via
> dropping SMMU stream IDs which relates to secure context bank.
>
> This problem only surfaced when the Gunyah based firmware stack is
> ported on Agatti replacing the legacy QHEE based firmware stack. Assigning
> Linux kernel (HLOS) VMID to secure context bank stream IDs is treated
> as a fault by Gunyah hypervisor which were previously ignored by QHEE
> hypervisor.
>
> The DT changes should be backwards compatible with legacy QHEE based
> firmware stack too.
>
> Suggested-by: Prakash Gupta <guptap@qti.qualcomm.com>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/agatti.dtsi | 11 +++--------
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v3 0/4] mux: gpio-mux: add enable GPIO support and ADG2404
From: Krzysztof Kozlowski @ 2026-01-16 8:37 UTC (permalink / raw)
To: Antoniu Miclaus
Cc: Peter Rosin, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Srinivas Kandagatla, Johan Hovold, David Lechner, devicetree,
linux-kernel
In-Reply-To: <20260115121943.23715-1-antoniu.miclaus@analog.com>
On Thu, Jan 15, 2026 at 02:18:18PM +0200, Antoniu Miclaus wrote:
> This series extends the gpio-mux driver with optional enable GPIO support
> to prevent glitches during channel transitions, then adds support for the
> Analog Devices ADG2404 multiplexer as the first user of this feature.
>
> The enable GPIO allows the multiplexer to be disabled before changing
> address lines and re-enabled after, preventing brief activation of
> unintended channels during transitions. This is particularly important
> for precision analog applications.
>
> The ADG2404 is a 4:1 analog multiplexer with low 0.62Ω on-resistance
> that requires this enable GPIO functionality for glitch-free operation.
>
> Changes in v3:
> * Extend gpio-mux driver instead of creating standalone adg2404 driver
> * Make enable GPIO optional for backward compatibility
> * Add MUX_IDLE_DISCONNECT support via enable GPIO
You are developing on some old kernel. You got stale Cc list of at least
three people! How could you for example get "johan+linaro@kernel.org" -
from which maintainer entry - but that at least is not bouncing like two
others.
You must use get_maintainers, not custom templates with fixed outdated
addresses.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 4/4] mux: gpio-mux: add adi,adg2404 support
From: Krzysztof Kozlowski @ 2026-01-16 8:34 UTC (permalink / raw)
To: Antoniu Miclaus
Cc: Peter Rosin, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Srinivas Kandagatla, Johan Hovold, Bartosz Golaszewski,
Linus Walleij, David Lechner, devicetree, linux-kernel
In-Reply-To: <20260116-lurking-beetle-of-imagination-2a05e6@quoll>
On 16/01/2026 09:32, Krzysztof Kozlowski wrote:
> On Thu, Jan 15, 2026 at 02:18:22PM +0200, Antoniu Miclaus wrote:
>> Add adi,adg2404 to the compatible list. The ADG2404 is a 4:1 analog
>> multiplexer that benefits from the enable GPIO support to prevent
>> glitches during channel transitions.
>>
>> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
>> ---
>> changes in v3:
>> * integrate with gpio-mux driver instead of standalone adg2404 driver
>> ---
>> drivers/mux/gpio.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/mux/gpio.c b/drivers/mux/gpio.c
>> index 93487483e81f..bd8f0c617dd6 100644
>> --- a/drivers/mux/gpio.c
>> +++ b/drivers/mux/gpio.c
>> @@ -59,6 +59,7 @@ static const struct mux_control_ops mux_gpio_ops = {
>>
>> static const struct of_device_id mux_gpio_dt_ids[] = {
>> { .compatible = "gpio-mux", },
>> + { .compatible = "adi,adg2404", },
>
> Why do you need the compatible? I do not understand this patchset. You
> are saying you integrate it into gpio-mux, but what you did is to
> duplicate the compatible and binding.
>
> Half of your patches are not necessary, you only needed to add
> enable-gpios to gpio-mux with argument that ADG2404 can use such binding
> (in complete/full/proper way).
... and Rob at v2 asked already that...
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 2/5] dt-bindings: i2c: qcom-cci: Document sm6150 compatible
From: Wenmeng Liu @ 2026-01-16 8:34 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Loic Poulain, Andi Shyti, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Robert Foss,
Todor Tomov, Bryan O'Donoghue, Vladimir Zapolskiy, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, linux-i2c,
linux-arm-msm, devicetree, linux-kernel, linux-media, imx,
linux-arm-kernel
In-Reply-To: <20260116-malachite-spaniel-of-refinement-af22ae@quoll>
On 1/16/2026 4:28 PM, Krzysztof Kozlowski wrote:
> On Thu, Jan 15, 2026 at 06:12:38PM +0800, Wenmeng Liu wrote:
>> Add the sm6150 CCI device string compatible.
>>
>> SM6150 include three clock:
>> bus: Bus clock responsible for data transfer.
>> iface: Interface clock responsible for register read and write.
>> cci: Clock for CCI core operations.
>>
>> Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
>> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
>> ---
>> .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>> index a3fe1eea6aece9685674feaa5ec53765c1ce23d8..3472670fdc908ef8f3b3afc68ff437c0435b69a7 100644
>> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
>> @@ -33,6 +33,7 @@ properties:
>> - qcom,sc8280xp-cci
>> - qcom,sdm670-cci
>> - qcom,sdm845-cci
>> + - qcom,sm6150-cci
>> - qcom,sm6350-cci
>> - qcom,sm8250-cci
>> - qcom,sm8450-cci
>> @@ -263,6 +264,23 @@ allOf:
>> - const: cpas_ahb
>> - const: cci
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,sm6150-cci
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 3
>> + maxItems: 3
>> + clock-names:
>> + items:
>> + - const: bus
>> + - const: iface
>> + - const: cci
>
> So basically the same as camnoc_axi+cpas_ahb+cci, so just put it into
> existing enum with qcom,sm8550-cci.
>
> I asked for this at v1.
> https://lore.kernel.org/all/43efa6fd-53c3-4680-8aca-7b37089ca295@kernel.org/
>
>
> Best regards,
> Krzysztof
>
I raised this question in the previous version.
And got reply as:
---
me:
+ clocks = <&camcc CAM_CC_SOC_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
clocks = <&camcc CAM_CC_SOC_AHB_CLK>,
clock-names = "camnoc_axi";
If this is acceptable, I will update it this way in the next version.
---
Loic:
No, the idea is to name the clock from the device’s perspective.
For example, from the CCI perspective, you typically have:
- A core clock, clocking the logic, which could be named 'core' (but
'cci' here is ok)
- Clocks related to the bus interfaces (such as AHB or AXI), which
could be named 'iface...' or 'bus...'.
This approach clearly identifies the role of each clock and keeps
naming consistent, without depending on where the clock originates or
its source name.
From that standpoint, some of the existing bus clock names defined in
qcom,i2c-cci.yaml are not ideal. You can find better naming in bindings
like qcom,i2c-qup.yaml or qcom,i2c-geni-qcom.yaml.
---
clocks = <&camcc CAM_CC_SOC_AHB_CLK>,
clock-names = "camnoc_axi";
so is this acceptable?
Thanks,
Wenmeng
^ permalink raw reply
* Re: [PATCH v3 3/4] dt-bindings: mux: gpio-mux: add adi,adg2404 support
From: Krzysztof Kozlowski @ 2026-01-16 8:34 UTC (permalink / raw)
To: Antoniu Miclaus
Cc: Peter Rosin, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Srinivas Kandagatla, Johan Hovold, Bartosz Golaszewski,
David Lechner, devicetree, linux-kernel
In-Reply-To: <20260116-invaluable-ambitious-piculet-dade13@quoll>
On 16/01/2026 09:29, Krzysztof Kozlowski wrote:
> On Thu, Jan 15, 2026 at 02:18:21PM +0200, Antoniu Miclaus wrote:
>> Add adi,adg2404 as a compatible string. The ADG2404 is a 4:1 analog
>> multiplexer that uses the enable-gpios feature.
>>
>> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
>> ---
>> changes in v3:
>> * integrate with gpio-mux bindings instead of separate adi,adg2404.yaml
>> ---
>> .../devicetree/bindings/mux/gpio-mux.yaml | 19 ++++++++++++++++++-
>> 1 file changed, 18 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mux/gpio-mux.yaml b/Documentation/devicetree/bindings/mux/gpio-mux.yaml
>> index 199792d42323..f5866b9f46dd 100644
>> --- a/Documentation/devicetree/bindings/mux/gpio-mux.yaml
>> +++ b/Documentation/devicetree/bindings/mux/gpio-mux.yaml
>> @@ -19,7 +19,9 @@ description: |+
>>
>> properties:
>> compatible:
>> - const: gpio-mux
>> + enum:
>> + - gpio-mux
>> + - adi,adg2404
>
> I do not understand why this was placed in gpio-mux. You have a strictly
> defined hardware, with known muxes, not a flexible semi-software
> binding.
>
> Otherwise please explain: why do you have both 0 and 1 cells?
>
> This is supposed to be in its own binding.
After reading further patches - this patch does not make sense, but it
should not be its own binding. Rob at v2 gave you advice what should be
done.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 4/4] mux: gpio-mux: add adi,adg2404 support
From: Krzysztof Kozlowski @ 2026-01-16 8:32 UTC (permalink / raw)
To: Antoniu Miclaus
Cc: Peter Rosin, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Srinivas Kandagatla, Johan Hovold, Bartosz Golaszewski,
Linus Walleij, David Lechner, devicetree, linux-kernel
In-Reply-To: <20260115121943.23715-5-antoniu.miclaus@analog.com>
On Thu, Jan 15, 2026 at 02:18:22PM +0200, Antoniu Miclaus wrote:
> Add adi,adg2404 to the compatible list. The ADG2404 is a 4:1 analog
> multiplexer that benefits from the enable GPIO support to prevent
> glitches during channel transitions.
>
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---
> changes in v3:
> * integrate with gpio-mux driver instead of standalone adg2404 driver
> ---
> drivers/mux/gpio.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mux/gpio.c b/drivers/mux/gpio.c
> index 93487483e81f..bd8f0c617dd6 100644
> --- a/drivers/mux/gpio.c
> +++ b/drivers/mux/gpio.c
> @@ -59,6 +59,7 @@ static const struct mux_control_ops mux_gpio_ops = {
>
> static const struct of_device_id mux_gpio_dt_ids[] = {
> { .compatible = "gpio-mux", },
> + { .compatible = "adi,adg2404", },
Why do you need the compatible? I do not understand this patchset. You
are saying you integrate it into gpio-mux, but what you did is to
duplicate the compatible and binding.
Half of your patches are not necessary, you only needed to add
enable-gpios to gpio-mux with argument that ADG2404 can use such binding
(in complete/full/proper way).
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 1/4] dt-bindings: mux: gpio-mux: add enable-gpios support
From: Krzysztof Kozlowski @ 2026-01-16 8:30 UTC (permalink / raw)
To: Antoniu Miclaus
Cc: Peter Rosin, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Srinivas Kandagatla, David Lechner, Bartosz Golaszewski,
devicetree, linux-kernel
In-Reply-To: <20260115121943.23715-2-antoniu.miclaus@analog.com>
On Thu, Jan 15, 2026 at 02:18:19PM +0200, Antoniu Miclaus wrote:
> Add support for an optional enable GPIO that allows the multiplexer
> to be disabled.
>
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---
> changes in v3:
> * new patch - extend gpio-mux instead of standalone driver approach
> ---
> Documentation/devicetree/bindings/mux/gpio-mux.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mux/gpio-mux.yaml b/Documentation/devicetree/bindings/mux/gpio-mux.yaml
> index ef7e33ec85d4..199792d42323 100644
> --- a/Documentation/devicetree/bindings/mux/gpio-mux.yaml
> +++ b/Documentation/devicetree/bindings/mux/gpio-mux.yaml
> @@ -25,6 +25,13 @@ properties:
> description:
> List of gpios used to control the multiplexer, least significant bit first.
>
> + enable-gpios:
> + description:
> + Optional GPIO to enable the multiplexer. When present, the mux will be
> + disabled before changing address lines and re-enabled after to prevent
> + glitches. Required for MUX_IDLE_DISCONNECT idle-state.
Where is any DTS user of such gpio-mux with enable-gpios?
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 3/4] dt-bindings: mux: gpio-mux: add adi,adg2404 support
From: Krzysztof Kozlowski @ 2026-01-16 8:29 UTC (permalink / raw)
To: Antoniu Miclaus
Cc: Peter Rosin, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Srinivas Kandagatla, Johan Hovold, Bartosz Golaszewski,
David Lechner, devicetree, linux-kernel
In-Reply-To: <20260115121943.23715-4-antoniu.miclaus@analog.com>
On Thu, Jan 15, 2026 at 02:18:21PM +0200, Antoniu Miclaus wrote:
> Add adi,adg2404 as a compatible string. The ADG2404 is a 4:1 analog
> multiplexer that uses the enable-gpios feature.
>
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---
> changes in v3:
> * integrate with gpio-mux bindings instead of separate adi,adg2404.yaml
> ---
> .../devicetree/bindings/mux/gpio-mux.yaml | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mux/gpio-mux.yaml b/Documentation/devicetree/bindings/mux/gpio-mux.yaml
> index 199792d42323..f5866b9f46dd 100644
> --- a/Documentation/devicetree/bindings/mux/gpio-mux.yaml
> +++ b/Documentation/devicetree/bindings/mux/gpio-mux.yaml
> @@ -19,7 +19,9 @@ description: |+
>
> properties:
> compatible:
> - const: gpio-mux
> + enum:
> + - gpio-mux
> + - adi,adg2404
I do not understand why this was placed in gpio-mux. You have a strictly
defined hardware, with known muxes, not a flexible semi-software
binding.
Otherwise please explain: why do you have both 0 and 1 cells?
This is supposed to be in its own binding.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 2/5] dt-bindings: i2c: qcom-cci: Document sm6150 compatible
From: Krzysztof Kozlowski @ 2026-01-16 8:28 UTC (permalink / raw)
To: Wenmeng Liu
Cc: Loic Poulain, Andi Shyti, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Robert Foss,
Todor Tomov, Bryan O'Donoghue, Vladimir Zapolskiy, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, linux-i2c,
linux-arm-msm, devicetree, linux-kernel, linux-media, imx,
linux-arm-kernel
In-Reply-To: <20260115-sm6150_evk-v3-2-81526dd15543@oss.qualcomm.com>
On Thu, Jan 15, 2026 at 06:12:38PM +0800, Wenmeng Liu wrote:
> Add the sm6150 CCI device string compatible.
>
> SM6150 include three clock:
> bus: Bus clock responsible for data transfer.
> iface: Interface clock responsible for register read and write.
> cci: Clock for CCI core operations.
>
> Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
> .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> index a3fe1eea6aece9685674feaa5ec53765c1ce23d8..3472670fdc908ef8f3b3afc68ff437c0435b69a7 100644
> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> @@ -33,6 +33,7 @@ properties:
> - qcom,sc8280xp-cci
> - qcom,sdm670-cci
> - qcom,sdm845-cci
> + - qcom,sm6150-cci
> - qcom,sm6350-cci
> - qcom,sm8250-cci
> - qcom,sm8450-cci
> @@ -263,6 +264,23 @@ allOf:
> - const: cpas_ahb
> - const: cci
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sm6150-cci
> + then:
> + properties:
> + clocks:
> + minItems: 3
> + maxItems: 3
> + clock-names:
> + items:
> + - const: bus
> + - const: iface
> + - const: cci
So basically the same as camnoc_axi+cpas_ahb+cci, so just put it into
existing enum with qcom,sm8550-cci.
I asked for this at v1.
https://lore.kernel.org/all/43efa6fd-53c3-4680-8aca-7b37089ca295@kernel.org/
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4 1/3] media: dt-bindings: add rockchip mipi csi-2 receiver
From: Krzysztof Kozlowski @ 2026-01-16 8:23 UTC (permalink / raw)
To: Michael Riesch
Cc: Chaoyi Chen, Kever Yang, Frank Li, Mehdi Djait,
Bryan O'Donoghue, Laurent Pinchart, Hans Verkuil,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Philipp Zabel, Sebastian Reichel,
Nicolas Dufresne, Collabora Kernel Team, Sakari Ailus,
linux-media, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20251114-rockchip-mipi-receiver-v4-1-a9c86fecd052@collabora.com>
On Thu, Jan 15, 2026 at 07:26:07PM +0100, Michael Riesch wrote:
> Add documentation for the Rockchip MIPI CSI-2 Receiver.
>
> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
> Signed-off-by: Michael Riesch <michael.riesch@collabora.com>
> ---
> .../bindings/media/rockchip,rk3568-mipi-csi2.yaml | 141 +++++++++++++++++++++
> MAINTAINERS | 6 +
> 2 files changed, 147 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v6 0/8] Support for Adreno 612 GPU - Respin
From: Akhil P Oommen @ 2026-01-16 8:13 UTC (permalink / raw)
To: rob.clark
Cc: Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar,
Marijn Suijten, David Airlie, Simona Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Jessica Zhang,
Gaurav Kohli, Dan Carpenter, linux-arm-msm, dri-devel, freedreno,
linux-kernel, devicetree, Jie Zhang, Dmitry Baryshkov,
Krzysztof Kozlowski, Krzysztof Kozlowski, Qingqing Zhou,
Konrad Dybcio, Jie Zhang
In-Reply-To: <CACSVV0006wVK-JWweuNYAfu-a9rtn=zp93sey1srPieGEaJWRg@mail.gmail.com>
On 1/16/2026 3:52 AM, Rob Clark wrote:
> On Wed, Dec 31, 2025 at 12:45 AM Akhil P Oommen
> <akhilpo@oss.qualcomm.com> wrote:
>>
>> This is a respin of an old series [1] that aimed to add support for
>> Adreno 612 GPU found in SM6150/QCS615 chipsets. In this version, we
>> have consolidated the previously separate series for DT and driver
>> support, along with some significant rework.
>>
>> Regarding A612 GPU, it falls under ADRENO_6XX_GEN1 family and is a cut
>> down version of A615 GPU. A612 has a new IP called Reduced Graphics
>> Management Unit or RGMU, a small state machine which helps to toggle
>> GX GDSC (connected to CX rail) to implement the IFPC feature. Unlike a
>> full-fledged GMU, the RGMU does not support features such as clock
>> control, resource voting via RPMh, HFI etc. Therefore, we require linux
>> clock driver support similar to gmu-wrapper implementations to control
>> gpu core clock and GX GDSC.
>>
>> In this series, the description of RGMU hardware in devicetree is more
>> complete than in previous version. However, the RGMU core is not
>> initialized from the driver as there is currently no need for it. We do
>> perform a dummy load of RGMU firmware (now available in linux-firmware)
>> to ensure that enabling RGMU core in the future won't break backward
>> compatibility for users.
>>
>> Due to significant changes compared to the old series, all R-b tags have
>> been dropped. Please review with fresh eyes.
>>
>> Last 3 patches are for Bjorn and the rest are for Rob Clark for pick up.
>
> I guess you meant the last 4 patches are for Bjorn?
Yes, that is correct. I missed updating this sentence after including
the GPU cooling related dt patch.
-Akhil
>
> BR,
> -R
>
>>
>> [1] Driver: https://lore.kernel.org/lkml/20241213-a612-gpu-support-v3-1-0e9b25570a69@quicinc.com/
>> Devicetree: https://lore.kernel.org/lkml/fu4rayftf3i4arf6l6bzqyzsctomglhpiniljkeuj74ftvzlpo@vklca2giwjlw/
>>
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>> ---
>> Changes in v6:
>> - Move the rgmu register range update from patch#8 to patch#6.
>> - Capture trailers
>> - Link to v5: https://lore.kernel.org/r/20251226-qcs615-spin-2-v5-0-354d86460ccb@oss.qualcomm.com
>>
>> Changes in v5:
>> - Rebase on v6.19-rc2
>> - Make the reg list in A612 GPU's binding doc stricter (Krzysztof)
>> - Link to v4: https://lore.kernel.org/r/20251204-qcs615-spin-2-v4-0-f5a00c5b663f@oss.qualcomm.com
>>
>> Changes in v4:
>> - Rebased on top of next-20251204 tag
>> - Added a new patch to simplify gpu dt schema (Krzysztof)
>> - Added a new patch for GPU cooling support (Gaurav)
>> - Updated the gpu/gmu register range in DT to be more accurate
>> - Remove 290Mhz corner for GPU as that is not present in downstream
>> - Link to v3: https://lore.kernel.org/r/20251122-qcs615-spin-2-v3-0-9f4d4c87f51d@oss.qualcomm.com
>>
>> Changes in v3:
>> - Rebased on top of next-20251121 tag
>> - Drop a612 driver support patch as it got picked up
>> - Rename rgmu.yaml -> qcom,adreno-rgmu.yaml (Krzysztof)
>> - Remove reg-names property for rgmu node (Krzysztof)
>> - Use 'gmu' instead of 'rgmu' as node name (Krzysztof)
>> - Describe cx_mem and cx_dgc register ranges (Krzysztof)
>> - A new patch to retrieve gmu core reg resource by id
>> - Link to v2: https://lore.kernel.org/r/20251107-qcs615-spin-2-v2-0-a2d7c4fbf6e6@oss.qualcomm.com
>>
>> Changes in v2:
>> - Rebased on next-20251105
>> - Fix hwcg configuration (Dan)
>> - Reuse a few gmu-wrapper routines (Konrad)
>> - Split out rgmu dt schema (Krzysztof/Dmitry)
>> - Fixes for GPU dt binding doc (Krzysztof)
>> - Removed VDD_CX from rgmu dt node. Will post a separate series to
>> address the gpucc changes (Konrad)
>> - Fix the reg range size for adreno smmu node and reorder the properties (Konrad)
>> - Link to v1: https://lore.kernel.org/r/20251017-qcs615-spin-2-v1-0-0baa44f80905@oss.qualcomm.com
>>
>> ---
>> Akhil P Oommen (3):
>> drm/msm/a6xx: Retrieve gmu core range by index
>> dt-bindings: display/msm: gpu: Simplify conditional schema logic
>> dt-bindings: display/msm: gpu: Document A612 GPU
>>
>> Gaurav Kohli (1):
>> arm64: dts: qcom: talos: Add GPU cooling
>>
>> Jie Zhang (3):
>> dt-bindings: display/msm/rgmu: Document A612 RGMU
>> arm64: dts: qcom: talos: Add gpu and rgmu nodes
>> arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU
>>
>> Qingqing Zhou (1):
>> arm64: dts: qcom: talos: add the GPU SMMU node
>>
>> .../devicetree/bindings/display/msm/gpu.yaml | 89 +++++++++---
>> .../bindings/display/msm/qcom,adreno-rgmu.yaml | 126 +++++++++++++++++
>> MAINTAINERS | 1 +
>> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++
>> arch/arm64/boot/dts/qcom/talos.dtsi | 149 +++++++++++++++++++++
>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 +-
>> 6 files changed, 357 insertions(+), 30 deletions(-)
>> ---
>> base-commit: 2408853dde584f01950a0f976b743739cce30eca
>> change-id: 20251015-qcs615-spin-2-ed45b0deb998
>>
>> Best regards,
>> --
>> Akhil P Oommen <akhilpo@oss.qualcomm.com>
>>
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: usb: parade,ps5511: Disallow unevaluated properties
From: Krzysztof Kozlowski @ 2026-01-16 7:58 UTC (permalink / raw)
To: Rob Herring
Cc: Greg Kroah-Hartman, Krzysztof Kozlowski, Conor Dooley,
Pin-yen Lin, Matthias Kaehlcke, linux-usb, devicetree,
linux-kernel, stable
In-Reply-To: <0d04b5c6-4e4a-41c0-ba14-09c95a6df235@oss.qualcomm.com>
On 16/01/2026 08:55, Krzysztof Kozlowski wrote:
>>
>> Removing this is wrong. This is defining the number of downstream USB
>> ports for this hub.
>>
>> What's wrong here is 'type: object' is missing, so any property that's
>> not a object passes (no, 'properties' doesn't imply it's an object).
>>
>> We should fix dtschema to allow additionalProperties when not a
>> boolean property to coexist with unevaluatedProperties. I'll look into
>> it.
>
> I see your commit. I will send v2 of this.
Ah no, that commit from 13th Jan was for interrupts. So later then :)
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v11 4/4] arm64: dts: qcom: talos-evk: Add support for QCS615 talos evk board
From: Dmitry Baryshkov @ 2026-01-16 7:56 UTC (permalink / raw)
To: tessolveupstream
Cc: Qian Zhang, andersson, konradybcio, robh, krzk+dt, conor+dt,
linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <530e2a7b-52e4-4119-ad54-8ff9e1d4fec0@gmail.com>
On Fri, Jan 16, 2026 at 12:28:22PM +0530, tessolveupstream@gmail.com wrote:
>
>
> On 15-01-2026 18:47, Qian Zhang wrote:
> >
> >
> > On 1/9/2026 5:52 PM, Sudarshan Shetty wrote:
> >> Add the device tree for the QCS615-based Talos EVK platform. The
> >> platform is composed of a System-on-Module following the SMARC
> >> standard, and a Carrier Board.
> >>
> >> The Carrier Board supports several display configurations, HDMI and
> >> LVDS. Both configurations use the same base hardware, with the display
> >> selection controlled by a DIP switch.
> >>
> >> Use a DTBO file, talos-evk-lvds-auo,g133han01.dtso, which defines an
> >> overlay that disables HDMI and adds LVDS. The DTs file talos-evk
> >> can describe the HDMI display configurations.
> >>
> >> The initial device tree includes support for:
> >> - CPU and memory
> >> - UART
> >> - GPIOs
> >> - Regulators
> >> - PMIC
> >> - Early console
> >> - AT24MAC602 EEPROM
> >> - MCP2515 SPI to CAN
> >> - ADV7535 DSI-to-HDMI bridge
> >> - DisplayPort interface
> >> - SN65DSI84ZXHR DSI-to-LVDS bridge
> >> - Wi-Fi/BT
> >>
> >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> >> Signed-off-by: Sudarshan Shetty <tessolveupstream@gmail.com>
> >> ---
> >> arch/arm64/boot/dts/qcom/Makefile | 4 +
> >> .../qcom/talos-evk-lvds-auo,g133han01.dtso | 126 ++++
> >> arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 616 ++++++++++++++++++
> >> arch/arm64/boot/dts/qcom/talos-evk.dts | 139 ++++
> >> 4 files changed, 885 insertions(+)
> >> create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso
> >> create mode 100644 arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
> >> create mode 100644 arch/arm64/boot/dts/qcom/talos-evk.dts
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> >> index 76cf0115a00a..289b651ef0c5 100644
> >> --- a/arch/arm64/boot/dts/qcom/Makefile
> >> +++ b/arch/arm64/boot/dts/qcom/Makefile
> >> @@ -324,6 +324,10 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb
> >> dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb
> >> +dtb-$(CONFIG_ARCH_QCOM) += talos-evk.dtb
> >> +talos-evk-lvds-auo,g133han01-dtbs := \
> >> + talos-evk.dtb talos-evk-lvds-auo,g133han01.dtbo
> >> +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-lvds-auo,g133han01.dtb
> >> x1e001de-devkit-el2-dtbs := x1e001de-devkit.dtb x1-el2.dtbo
> >> dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb x1e001de-devkit-el2.dtb
> >> x1e78100-lenovo-thinkpad-t14s-el2-dtbs := x1e78100-lenovo-thinkpad-t14s.dtb x1-el2.dtbo
> >> diff --git a/arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso b/arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso
> >> new file mode 100644
> >> index 000000000000..ad058cf4cd93
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso
> >> @@ -0,0 +1,126 @@
> >> +// SPDX-License-Identifier: BSD-3-Clause
> >> +/*
> >> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> >> + */
> >> +/dts-v1/;
> >> +/plugin/;
> >> +
> >> +#include <dt-bindings/gpio/gpio.h>
> >> +
> >> +&{/} {
> >> + backlight: backlight {
> >> + compatible = "gpio-backlight";
> >> + gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>,
> >> + <&tlmm 115 GPIO_ACTIVE_HIGH>;
> >> + default-on;
> >> + };
> >> +
> >> + panel-lvds {
> >> + compatible = "auo,g133han01";
> >> +
> >> + ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + /* LVDS A (Odd pixels) */
> >> + port@0 {
> >> + reg = <0>;
> >> + dual-lvds-odd-pixels;
> >> +
> >> + lvds_panel_out_a: endpoint {
> >> + remote-endpoint = <&sn65dsi84_out_a>;
> >> + };
> >> + };
> >> +
> >> + /* LVDS B (Even pixels) */
> >> + port@1 {
> >> + reg = <1>;
> >> + dual-lvds-even-pixels;
> >> +
> >> + lvds_panel_out_b: endpoint {
> >> + remote-endpoint = <&sn65dsi84_out_b>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> +};
> >> +
> >> +&hdmi_connector {
> >> + status = "disabled";
> >> +};
> >> +
> >> +&i2c1 {
> >> + clock-frequency = <400000>;
> >> +
> >> + status = "okay";
> >> +
> >> + hdmi_bridge: bridge@3d {
> >> + status = "disabled";
> >> + };
> >> +
> >> + lvds_bridge: bridge@2c {
> >> + compatible = "ti,sn65dsi84";
> >> + reg = <0x2c>;
> >> + enable-gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
> >> + ti,dsi-lanes = <4>;
> >> + ti,lvds-format = "jeida-24";
> >> + ti,lvds-bpp = <24>;
> >> +
> >> + ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port@0 {
> >> + reg = <0>;
> >> +
> >> + sn65dsi84_in: endpoint {
> >> + data-lanes = <1 2 3 4>;
> >> + remote-endpoint = <&mdss_dsi0_out>;
> >> + };
> >> + };
> >> +
> >> + port@2 {
> >> + reg = <2>;
> >> +
> >> + sn65dsi84_out_a: endpoint {
> >> + data-lanes = <1 2 3 4>;
> >> + remote-endpoint = <&lvds_panel_out_a>;
> >> + };
> >> + };
> >> +
> >> + port@3 {
> >> + reg = <3>;
> >> +
> >> + sn65dsi84_out_b: endpoint {
> >> + data-lanes = <1 2 3 4>;
> >> + remote-endpoint = <&lvds_panel_out_b>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> +};
> >> +
> >> +&mdss_dsi0 {
> >> + vdda-supply = <&vreg_l11a>;
> >> +
> >> + status = "okay";
> >> +};
> >> +
> >> +&mdss_dsi0_out {
> >> + remote-endpoint = <&sn65dsi84_in>;
> >> + data-lanes = <0 1 2 3>;
> >> +};
> >> +
> >> +&tlmm {
> >> + lcd_bklt_en: lcd-bklt-en-state {
> >> + pins = "gpio115";
> >> + function = "gpio";
> >> + bias-disable;
> >> + };
> >> +
> >> + lcd_bklt_pwm: lcd-bklt-pwm-state {
> >> + pins = "gpio59";
> >> + function = "gpio";
> >> + bias-disable;
> >> + };
> >> +};
> >> diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
> >> new file mode 100644
> >> index 000000000000..95ed335bcb08
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
> >> @@ -0,0 +1,616 @@
> >> +// SPDX-License-Identifier: BSD-3-Clause
> >> +/*
> >> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> >> + */
> >> +/dts-v1/;
> >> +
> >> +#include <dt-bindings/gpio/gpio.h>
> >> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> >> +#include "talos.dtsi"
> >> +#include "pm8150.dtsi"
> >> +/ {
> >> + aliases {
> >> + mmc0 = &sdhc_1;
> >> + serial0 = &uart0;
> >> + serial1 = &uart7;
> >> + };
> >> +
> >> + chosen {
> >> + stdout-path = "serial0:115200n8";
> >> + };
> >> +
> >> + clocks {
> >> + can_osc: can-oscillator {
> >> + compatible = "fixed-clock";
> >> + clock-frequency = <20000000>;
> >> + #clock-cells = <0>;
> >> + };
> >> +
> >> + sleep_clk: sleep-clk {
> >> + compatible = "fixed-clock";
> >> + clock-frequency = <32764>;
> >> + #clock-cells = <0>;
> >> + };
> >> +
> >> + xo_board_clk: xo-board-clk {
> >> + compatible = "fixed-clock";
> >> + clock-frequency = <38400000>;
> >> + #clock-cells = <0>;
> >> + };
> >> + };
> >> +
> >> + regulator-usb2-vbus {
> >> + compatible = "regulator-fixed";
> >> + regulator-name = "USB2_VBUS";
> >> + gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
> >> + pinctrl-0 = <&usb2_en>;
> >> + pinctrl-names = "default";
> >> + enable-active-high;
> >> + regulator-always-on;
> >> + };
> >> +
> >> + vreg_conn_1p8: regulator-conn-1p8 {
> >> + compatible = "regulator-fixed";
> >> + regulator-name = "vreg_conn_1p8";
> >> + startup-delay-us = <4000>;
> >> + enable-active-high;
> >> + gpio = <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>;
> >> + };
> >> +
> >> + vreg_conn_pa: regulator-conn-pa {
> >> + compatible = "regulator-fixed";
> >> + regulator-name = "vreg_conn_pa";
> >> + startup-delay-us = <4000>;
> >> + enable-active-high;
> >> + gpio = <&pm8150_gpios 6 GPIO_ACTIVE_HIGH>;
> >> + };
> >> +
> >> + vreg_v3p3_can: regulator-v3p3-can {
> >> + compatible = "regulator-fixed";
> >> + regulator-name = "vreg-v3p3-can";
> >> + regulator-min-microvolt = <3300000>;
> >> + regulator-max-microvolt = <3300000>;
> >> + regulator-boot-on;
> >> + regulator-always-on;
> >> + };
> >> +
> >> + vreg_v5p0_can: regulator-v5p0-can {
> >> + compatible = "regulator-fixed";
> >> + regulator-name = "vreg-v5p0-can";
> >> + regulator-min-microvolt = <5000000>;
> >> + regulator-max-microvolt = <5000000>;
> >> + regulator-boot-on;
> >> + regulator-always-on;
> >> + };
> >> +
> >> + wcn6855-pmu {
> >> + compatible = "qcom,wcn6855-pmu";
> >> +
> >> + pinctrl-0 = <&bt_en_state>, <&wlan_en_state>;
> >> + pinctrl-names = "default";
> >> +
> >> + bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
> >> + wlan-enable-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
> >> +
> >> + vddio-supply = <&vreg_conn_pa>;
> >> + vddaon-supply = <&vreg_s5a>;
> >> + vddpmu-supply = <&vreg_conn_1p8>;
> >> + vddpmumx-supply = <&vreg_conn_1p8>;
> >> + vddpmucx-supply = <&vreg_conn_pa>;
> >> + vddrfa0p95-supply = <&vreg_s5a>;
> >> + vddrfa1p3-supply = <&vreg_s6a>;
> >> + vddrfa1p9-supply = <&vreg_l15a>;
> >> + vddpcie1p3-supply = <&vreg_s6a>;
> >> + vddpcie1p9-supply = <&vreg_l15a>;
> >> +
> >> + regulators {
> >> + vreg_pmu_rfa_cmn: ldo0 {
> >> + regulator-name = "vreg_pmu_rfa_cmn";
> >> + };
> >> +
> >> + vreg_pmu_aon_0p59: ldo1 {
> >> + regulator-name = "vreg_pmu_aon_0p59";
> >> + };
> >> +
> >> + vreg_pmu_wlcx_0p8: ldo2 {
> >> + regulator-name = "vreg_pmu_wlcx_0p8";
> >> + };
> >> +
> >> + vreg_pmu_wlmx_0p85: ldo3 {
> >> + regulator-name = "vreg_pmu_wlmx_0p85";
> >> + };
> >> +
> >> + vreg_pmu_btcmx_0p85: ldo4 {
> >> + regulator-name = "vreg_pmu_btcmx_0p85";
> >> + };
> >> +
> >> + vreg_pmu_rfa_0p8: ldo5 {
> >> + regulator-name = "vreg_pmu_rfa_0p8";
> >> + };
> >> +
> >> + vreg_pmu_rfa_1p2: ldo6 {
> >> + regulator-name = "vreg_pmu_rfa_1p2";
> >> + };
> >> +
> >> + vreg_pmu_rfa_1p7: ldo7 {
> >> + regulator-name = "vreg_pmu_rfa_1p7";
> >> + };
> >> +
> >> + vreg_pmu_pcie_0p9: ldo8 {
> >> + regulator-name = "vreg_pmu_pcie_0p9";
> >> + };
> >> +
> >> + vreg_pmu_pcie_1p8: ldo9 {
> >> + regulator-name = "vreg_pmu_pcie_1p8";
> >> + };
> >> + };
> >> + };
> >> +
> >> + wifi_1p8v: regulator-wifi-1p8v {
> >> + compatible = "regulator-fixed";
> >> + regulator-name = "wifi_1p8v";
> >> + regulator-min-microvolt = <1800000>;
> >> + regulator-max-microvolt = <1800000>;
> >> + gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>;
> > Please check this pin number
> >> + enable-active-high;
> >> + pinctrl-0 = <&wifi_reg_en_pins_state>;
> >> + pinctrl-names = "default";
> >> + regulator-boot-on;
> >> + regulator-always-on;
> >> + };
> >> +
> >> + wifi_3p85v: regulator-wifi-3p85v {
> >> + compatible = "regulator-fixed";
> >> + regulator-name = "wifi_3p85v";
> >> + regulator-min-microvolt = <3850000>;
> >> + regulator-max-microvolt = <3850000>;
> >> + gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>;
> > Please check this pin number
> >> + enable-active-high;
> >> + pinctrl-0 = <&wifi_reg_en_pins_state>;
> >> + pinctrl-names = "default";
> >> + regulator-boot-on;
> >> + regulator-always-on;
> >> + };
> >> +};
> >
> > Are these two node necessary?
> >
>
> On this board, GPIO91 is wired as a common enable for both WiFi
> power rails: WiFi 1.8V and WiFi 3.85V.
> I currently modeled them as two regulator-fixed nodes because these
> are two distinct rails.
> Would you prefer modelling a single regulator node that controls the
> shared GPIO as below:
>
> wifi_en: regulator-wifi-en {
> compatible = "regulator-fixed";
> regulator-name = "wifi_en";
> gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>;
> enable-active-high;
> pinctrl-0 = <&wifi_reg_en_pins_state>;
> pinctrl-names = "default";
> regulator-boot-on;
> regulator-always-on;
> };
What is the voltage of this regulator? What does it represent? What
should be represented in the DT?
BTW: what is powered on by those regulators? I don't see them being
wired to the PMU.
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: usb: parade,ps5511: Disallow unevaluated properties
From: Krzysztof Kozlowski @ 2026-01-16 7:55 UTC (permalink / raw)
To: Rob Herring
Cc: Greg Kroah-Hartman, Krzysztof Kozlowski, Conor Dooley,
Pin-yen Lin, Matthias Kaehlcke, linux-usb, devicetree,
linux-kernel, stable
In-Reply-To: <20260112202040.GA943734-robh@kernel.org>
On 12/01/2026 21:20, Rob Herring wrote:
> On Mon, Jan 12, 2026 at 10:01:50AM +0100, Krzysztof Kozlowski wrote:
>> Review given to v2 [1] of commit fc259b024cb3 ("dt-bindings: usb: Add
>> binding for PS5511 hub controller") asked to use unevaluatedProperties,
>> but this was ignored by the author probably because current dtschema
>> does not allow to use both additionalProperties and
>> unevaluatedProperties. As an effect, this binding does not end with
>> unevaluatedProperties and allows any properties to be added.
>>
>> Fix this by reverting the approach suggested at v2 review and using
>> simpler definition of "reg" constraints.
>>
>> Link: https://lore.kernel.org/r/20250416180023.GB3327258-robh@kernel.org/ [1]
>> Fixes: fc259b024cb3 ("dt-bindings: usb: Add binding for PS5511 hub controller")
>> Cc: <stable@vger.kernel.org>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>> ---
>> .../devicetree/bindings/usb/parade,ps5511.yaml | 12 ++++++------
>> 1 file changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/parade,ps5511.yaml b/Documentation/devicetree/bindings/usb/parade,ps5511.yaml
>> index 10d002f09db8..154d779e507a 100644
>> --- a/Documentation/devicetree/bindings/usb/parade,ps5511.yaml
>> +++ b/Documentation/devicetree/bindings/usb/parade,ps5511.yaml
>> @@ -15,6 +15,10 @@ properties:
>> - usb1da0,5511
>> - usb1da0,55a1
>>
>> + reg:
>> + minimum: 1
>> + maximum: 5
>> +
>
> This 'reg' would be the upstream USB port. We have no idea what its
> constraints are for the value.
Indeed.
>
>> reset-gpios:
>> items:
>> - description: GPIO specifier for RESETB pin.
>> @@ -41,12 +45,6 @@ properties:
>> minimum: 1
>> maximum: 5
>>
>> -additionalProperties:
>> - properties:
>> - reg:
>> - minimum: 1
>> - maximum: 5
>
> Removing this is wrong. This is defining the number of downstream USB
> ports for this hub.
>
> What's wrong here is 'type: object' is missing, so any property that's
> not a object passes (no, 'properties' doesn't imply it's an object).
>
> We should fix dtschema to allow additionalProperties when not a
> boolean property to coexist with unevaluatedProperties. I'll look into
> it.
I see your commit. I will send v2 of this.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v12 3/3] arm64: dts: qcom: talos-evk: Add support for QCS615 talos evk board
From: Dmitry Baryshkov @ 2026-01-16 7:54 UTC (permalink / raw)
To: tessolveupstream
Cc: Jie Gan, andersson, konradybcio, robh, krzk+dt, conor+dt,
linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <128a5f86-dd3f-4e5e-a55f-3c8b5993779b@gmail.com>
On Fri, Jan 16, 2026 at 11:25:50AM +0530, tessolveupstream@gmail.com wrote:
>
>
> On 15-01-2026 07:54, Jie Gan wrote:
> >
> >
> > On 1/14/2026 6:00 PM, Sudarshan Shetty wrote:
> >> Add the device tree for the QCS615-based Talos EVK platform. The
> >> platform is composed of a System-on-Module following the SMARC
> >> standard, and a Carrier Board.
> >>
> >> The Carrier Board supports several display configurations, HDMI and
> >> LVDS. Both configurations use the same base hardware, with the display
> >> selection controlled by a DIP switch.
> >>
> >> Use a DTBO file, talos-evk-lvds-auo,g133han01.dtso, which defines an
> >> overlay that disables HDMI and adds LVDS. The DTs file talos-evk
> >> can describe the HDMI display configurations.
> >>
> >> The initial device tree includes support for:
> >> - CPU and memory
> >> - UART
> >> - GPIOs
> >> - Regulators
> >> - PMIC
> >> - Early console
> >> - AT24MAC602 EEPROM
> >> - MCP2515 SPI to CAN
> >> - ADV7535 DSI-to-HDMI bridge
> >> - DisplayPort interface
> >> - SN65DSI84ZXHR DSI-to-LVDS bridge
> >> - Wi-Fi/BT
> >>
> >> +
> >> +&usb_1 {
> >> + status = "okay";
> >> +};
> >> +
> >> +&usb_1_dwc3 {
> >> + dr_mode = "host";
> >> +};
> >> +
> >> +&usb_hsphy_1 {
> >> + vdd-supply = <&vreg_l5a>;
> >> + vdda-pll-supply = <&vreg_l12a>;
> >> + vdda-phy-dpdm-supply = <&vreg_l13a>;
> >> +
> >> + status = "okay";
> >> +};
> >> +
> >> +&usb_2 {
> >> + status = "okay";
> >> +};
> >> +
> >> +&usb_2_dwc3 {
> >> + dr_mode = "host";
> >> +};
> >
> > Both usb devices have been configured to host mode, do we need adb?
> > The adb only work with usb peripheral mode.
> >
>
> This topic was discussed previously, and the fix was implemented
> based on that discussion.
> For reference, I’m sharing the earlier communication in the
> links below.
>
> https://lore.kernel.org/all/qq4aak33bn3mqxd2edu6zgkkshby63mmitg7zqkly2rj4c2lh7@4s7sndb7e2jr/T/#meaa464a4e6992b36b5d8d41ddc691ee4ea36b1ce
>
> https://lore.kernel.org/all/20251014120223.1914790-1-tessolveupstream@gmail.com/T/#t
Neither of these links is relevant to the question.
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 04/14] wifi: ath10k: snoc: support powering on the device via pwrseq
From: Krzysztof Kozlowski @ 2026-01-16 7:48 UTC (permalink / raw)
To: Jeff Johnson, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, Marcel Holtmann, Luiz Augusto von Dentz,
Jeff Johnson, Bjorn Andersson, Konrad Dybcio,
Manivannan Sadhasivam, Vinod Koul, Balakrishna Godavarthi,
Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, linux-bluetooth,
linux-wireless, ath10k, linux-pm, Bartosz Golaszewski
In-Reply-To: <52b2b799-09e6-40a4-bea8-c7e8bf21cf51@oss.qualcomm.com>
On 15/01/2026 23:30, Jeff Johnson wrote:
> On 1/5/2026 5:01 PM, Dmitry Baryshkov wrote:
>> The WCN39xx family of WiFi/BT chips incorporates a simple PMU, spreading
>> voltages over internal rails. Implement support for using powersequencer
>> for this family of ATH10k devices in addition to using regulators.
>>
>> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>> ---
>> drivers/net/wireless/ath/ath10k/snoc.c | 54 ++++++++++++++++++++++++++++++++--
>> drivers/net/wireless/ath/ath10k/snoc.h | 2 ++
>
> My automation flagged:
> * drivers/net/wireless/ath/ath10k/snoc.c has no QTI copyright
> * drivers/net/wireless/ath/ath10k/snoc.h has no QTI copyright
> * 2 copyright issues
>
> I'll add these manually in my 'pending' branch
>
And why is this a problem? You are not here to impose Qualcomm rules, bu
care about Linux kernel. You cannot add copyrights based on what exactly?
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 2/2] media: staging: Drop starfive-camss from staging
From: Changhuang Liang @ 2026-01-16 7:14 UTC (permalink / raw)
To: Jai Luthra, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Greg Kroah-Hartman,
Philipp Zabel
Cc: Laurent Pinchart, Rishikesh Donadkar, Sakari Ailus,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev
In-Reply-To: <20260116-drop-starfive-camss-v2-2-34df57025921@ideasonboard.com>
> The starfive-camss driver is no longer being worked upon for destaging,
> as confirmed by the maintainer, so drop it.
>
> Link:
> https://lore.kernel.org/all/ZQ0PR01MB13024A92926C415C187D2C18F29F2
> @ZQ0PR01MB1302.CHNPR01.prod.partner.outlook.cn/
> Signed-off-by: Jai Luthra <jai.luthra@ideasonboard.com>
Acked-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Best Regards,
Changhuang
> ---
> Changes in v2:
> - Drop reference to starfive-camss documentation in v4l-drivers.rst
> ---
> Documentation/admin-guide/media/starfive_camss.rst | 72 ---
> .../admin-guide/media/starfive_camss_graph.dot | 12 -
> Documentation/admin-guide/media/v4l-drivers.rst | 1 -
> MAINTAINERS | 8 -
> drivers/staging/media/Kconfig | 2 -
> drivers/staging/media/Makefile | 1 -
> drivers/staging/media/starfive/Kconfig | 5 -
> drivers/staging/media/starfive/Makefile | 2 -
> drivers/staging/media/starfive/camss/Kconfig | 18 -
> drivers/staging/media/starfive/camss/Makefile | 13 -
> drivers/staging/media/starfive/camss/TODO.txt | 4 -
> drivers/staging/media/starfive/camss/stf-camss.c | 438 ---------------
> drivers/staging/media/starfive/camss/stf-camss.h | 134 -----
> drivers/staging/media/starfive/camss/stf-capture.c | 605 ---------------------
> drivers/staging/media/starfive/camss/stf-capture.h | 86 ---
> .../staging/media/starfive/camss/stf-isp-hw-ops.c | 445 ---------------
> drivers/staging/media/starfive/camss/stf-isp.c | 379 -------------
> drivers/staging/media/starfive/camss/stf-isp.h | 428 ---------------
> drivers/staging/media/starfive/camss/stf-video.c | 570 -------------------
> drivers/staging/media/starfive/camss/stf-video.h | 100 ----
> 20 files changed, 3323 deletions(-)
>
> diff --git a/Documentation/admin-guide/media/starfive_camss.rst
> b/Documentation/admin-guide/media/starfive_camss.rst
> deleted file mode 100644
> index
> ca42e9447c47bef136e93fe6fe09dfc551e790ce..00000000000000000000000
> 00000000000000000
> --- a/Documentation/admin-guide/media/starfive_camss.rst
> +++ /dev/null
> @@ -1,72 +0,0 @@
> -.. SPDX-License-Identifier: GPL-2.0
> -
> -.. include:: <isonum.txt>
> -
> -================================
> -Starfive Camera Subsystem driver
> -================================
> -
> -Introduction
> -------------
> -
> -This file documents the driver for the Starfive Camera Subsystem found on
> -Starfive JH7110 SoC. The driver is located under
> drivers/staging/media/starfive/
> -camss.
> -
> -The driver implements V4L2, Media controller and v4l2_subdev interfaces.
> Camera
> -sensor using V4L2 subdev interface in the kernel is supported.
> -
> -The driver has been successfully used on the Gstreamer 1.18.5 with v4l2src
> -plugin.
> -
> -
> -Starfive Camera Subsystem hardware
> -----------------------------------
> -
> -The Starfive Camera Subsystem hardware consists of::
> -
> - |\ +---------------+ +-----------+
> - +----------+ | \ | | |
> |
> - | | | | | | |
> |
> - | MIPI |----->| |----->| ISP |----->| |
> - | | | | | | |
> |
> - +----------+ | | | | | Memory
> |
> - |MUX| +---------------+ | Interface |
> - +----------+ | | |
> |
> - | | | |---------------------------->| |
> - | Parallel |----->| | | |
> - | | | | |
> |
> - +----------+ | / |
> |
> - |/
> +-----------+
> -
> -- MIPI: The MIPI interface, receiving data from a MIPI CSI-2 camera sensor.
> -
> -- Parallel: The parallel interface, receiving data from a parallel sensor.
> -
> -- ISP: The ISP, processing raw Bayer data from an image sensor and producing
> - YUV frames.
> -
> -
> -Topology
> ---------
> -
> -The media controller pipeline graph is as follows:
> -
> -.. _starfive_camss_graph:
> -
> -.. kernel-figure:: starfive_camss_graph.dot
> - :alt: starfive_camss_graph.dot
> - :align: center
> -
> -The driver has 2 video devices:
> -
> -- capture_raw: The capture device, capturing image data directly from a
> sensor.
> -- capture_yuv: The capture device, capturing YUV frame data processed by
> the
> - ISP module
> -
> -The driver has 3 subdevices:
> -
> -- stf_isp: is responsible for all the isp operations, outputs YUV frames.
> -- cdns_csi2rx: a CSI-2 bridge supporting up to 4 CSI lanes in input, and 4
> - different pixel streams in output.
> -- imx219: an image sensor, image data is sent through MIPI CSI-2.
> diff --git a/Documentation/admin-guide/media/starfive_camss_graph.dot
> b/Documentation/admin-guide/media/starfive_camss_graph.dot
> deleted file mode 100644
> index
> 8eff1f161ac7fadb4c1a5c8bacc11567ef948984..00000000000000000000000
> 00000000000000000
> --- a/Documentation/admin-guide/media/starfive_camss_graph.dot
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -digraph board {
> - rankdir=TB
> - n00000001 [label="{{<port0> 0} | stf_isp\n/dev/v4l-subdev0 | {<port1>
> 1}}", shape=Mrecord, style=filled, fillcolor=green]
> - n00000001:port1 -> n00000008 [style=dashed]
> - n00000004 [label="capture_raw\n/dev/video0", shape=box, style=filled,
> fillcolor=yellow]
> - n00000008 [label="capture_yuv\n/dev/video1", shape=box, style=filled,
> fillcolor=yellow]
> - n0000000e [label="{{<port0> 0} | cdns_csi2rx.19800000.csi-bridge\n |
> {<port1> 1 | <port2> 2 | <port3> 3 | <port4> 4}}", shape=Mrecord, style=filled,
> fillcolor=green]
> - n0000000e:port1 -> n00000001:port0 [style=dashed]
> - n0000000e:port1 -> n00000004 [style=dashed]
> - n00000018 [label="{{} | imx219 6-0010\n/dev/v4l-subdev1 | {<port0>
> 0}}", shape=Mrecord, style=filled, fillcolor=green]
> - n00000018:port0 -> n0000000e:port0 [style=bold]
> -}
> diff --git a/Documentation/admin-guide/media/v4l-drivers.rst
> b/Documentation/admin-guide/media/v4l-drivers.rst
> index
> 393f83e8dc4dd86fc73d8a4f23c535bdc886c308..d31da8e0a54f27820699131f
> 786b942e29d6d935 100644
> --- a/Documentation/admin-guide/media/v4l-drivers.rst
> +++ b/Documentation/admin-guide/media/v4l-drivers.rst
> @@ -33,7 +33,6 @@ Video4Linux (V4L) driver-specific documentation
> si470x
> si4713
> si476x
> - starfive_camss
> vimc
> visl
> vivid
> diff --git a/MAINTAINERS b/MAINTAINERS
> index
> 5e19700e9152b103c194003b4421e6bc26022608..206128259c2023e6cd88
> fb342f652addb8fa72fe 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -24847,14 +24847,6 @@ M: Ion Badulescu <ionut@badula.org>
> S: Odd Fixes
> F: drivers/net/ethernet/adaptec/starfire*
>
> -STARFIVE CAMERA SUBSYSTEM DRIVER
> -M: Jack Zhu <jack.zhu@starfivetech.com>
> -M: Changhuang Liang <changhuang.liang@starfivetech.com>
> -L: linux-media@vger.kernel.org
> -S: Maintained
> -F: Documentation/admin-guide/media/starfive_camss.rst
> -F: drivers/staging/media/starfive/camss
> -
> STARFIVE CRYPTO DRIVER
> M: Jia Jie Ho <jiajie.ho@starfivetech.com>
> M: William Qiu <william.qiu@starfivetech.com>
> diff --git a/drivers/staging/media/Kconfig b/drivers/staging/media/Kconfig
> index
> ab250c89cd4d48ec9e0a99a56b121e42fd8f3213..1aa31bddf9703c09d11cbcd
> bf97a94b4be830cd7 100644
> --- a/drivers/staging/media/Kconfig
> +++ b/drivers/staging/media/Kconfig
> @@ -34,8 +34,6 @@ source "drivers/staging/media/max96712/Kconfig"
>
> source "drivers/staging/media/meson/vdec/Kconfig"
>
> -source "drivers/staging/media/starfive/Kconfig"
> -
> source "drivers/staging/media/sunxi/Kconfig"
>
> source "drivers/staging/media/tegra-video/Kconfig"
> diff --git a/drivers/staging/media/Makefile b/drivers/staging/media/Makefile
> index
> 4a073938b2b2d5294dca745f9acac8ed3408cf99..6f78b0edde1e310984ea10b
> 9282a952770e857f3 100644
> --- a/drivers/staging/media/Makefile
> +++ b/drivers/staging/media/Makefile
> @@ -4,7 +4,6 @@ obj-$(CONFIG_INTEL_ATOMISP) += atomisp/
> obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx/
> obj-$(CONFIG_VIDEO_MAX96712) += max96712/
> obj-$(CONFIG_VIDEO_MESON_VDEC) += meson/vdec/
> -obj-$(CONFIG_VIDEO_STARFIVE_CAMSS) += starfive/
> obj-$(CONFIG_VIDEO_SUNXI) += sunxi/
> obj-$(CONFIG_VIDEO_TEGRA) += tegra-video/
> obj-$(CONFIG_VIDEO_IPU3_IMGU) += ipu3/
> diff --git a/drivers/staging/media/starfive/Kconfig
> b/drivers/staging/media/starfive/Kconfig
> deleted file mode 100644
> index
> 34727cf560722893a0562d91d832189d2ab331c6..000000000000000000000
> 0000000000000000000
> --- a/drivers/staging/media/starfive/Kconfig
> +++ /dev/null
> @@ -1,5 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0-only
> -
> -comment "StarFive media platform drivers"
> -
> -source "drivers/staging/media/starfive/camss/Kconfig"
> diff --git a/drivers/staging/media/starfive/Makefile
> b/drivers/staging/media/starfive/Makefile
> deleted file mode 100644
> index
> 4639fa1bca325e958f52f481edfe1949115e53ea..00000000000000000000000
> 00000000000000000
> --- a/drivers/staging/media/starfive/Makefile
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0-only
> -obj-y += camss/
> diff --git a/drivers/staging/media/starfive/camss/Kconfig
> b/drivers/staging/media/starfive/camss/Kconfig
> deleted file mode 100644
> index
> 9ea5708fe40955e2db57a2cc8c7ad39c4cbe5604..0000000000000000000000
> 000000000000000000
> --- a/drivers/staging/media/starfive/camss/Kconfig
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0-only
> -config VIDEO_STARFIVE_CAMSS
> - tristate "Starfive Camera Subsystem driver"
> - depends on V4L_PLATFORM_DRIVERS
> - depends on VIDEO_DEV && OF
> - depends on HAS_DMA
> - depends on PM
> - depends on ARCH_STARFIVE || COMPILE_TEST
> - select MEDIA_CONTROLLER
> - select VIDEO_V4L2_SUBDEV_API
> - select VIDEOBUF2_DMA_CONTIG
> - select V4L2_FWNODE
> - help
> - Enable this to support for the Starfive Camera subsystem
> - found on Starfive JH7110 SoC.
> -
> - To compile this driver as a module, choose M here: the
> - module will be called starfive-camss.
> diff --git a/drivers/staging/media/starfive/camss/Makefile
> b/drivers/staging/media/starfive/camss/Makefile
> deleted file mode 100644
> index
> 005790202e7b8ac02d60f53f3ca7b42c7ff4b780..00000000000000000000000
> 00000000000000000
> --- a/drivers/staging/media/starfive/camss/Makefile
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0
> -#
> -# Makefile for StarFive Camera Subsystem driver
> -#
> -
> -starfive-camss-objs += \
> - stf-camss.o \
> - stf-capture.o \
> - stf-isp.o \
> - stf-isp-hw-ops.o \
> - stf-video.o
> -
> -obj-$(CONFIG_VIDEO_STARFIVE_CAMSS) += starfive-camss.o
> diff --git a/drivers/staging/media/starfive/camss/TODO.txt
> b/drivers/staging/media/starfive/camss/TODO.txt
> deleted file mode 100644
> index
> 7d459f4f09d005d28572644d9c77dddcd2d70b48..0000000000000000000000
> 000000000000000000
> --- a/drivers/staging/media/starfive/camss/TODO.txt
> +++ /dev/null
> @@ -1,4 +0,0 @@
> -Unstaging requirements:
> -- Add userspace support which demonstrates the ability to receive statistics
> and
> - adapt hardware modules configuration accordingly;
> -- Add documentation for description of the statistics data structures;
> diff --git a/drivers/staging/media/starfive/camss/stf-camss.c
> b/drivers/staging/media/starfive/camss/stf-camss.c
> deleted file mode 100644
> index
> 259aaad010d2f02b620ce7ac98517c75134566bb..0000000000000000000000
> 000000000000000000
> --- a/drivers/staging/media/starfive/camss/stf-camss.c
> +++ /dev/null
> @@ -1,438 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * stf_camss.c
> - *
> - * Starfive Camera Subsystem driver
> - *
> - * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
> - *
> - * Author: Jack Zhu <jack.zhu@starfivetech.com>
> - * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
> - *
> - */
> -#include <linux/module.h>
> -#include <linux/of.h>
> -#include <linux/of_graph.h>
> -#include <linux/platform_device.h>
> -#include <linux/pm_runtime.h>
> -#include <linux/videodev2.h>
> -#include <media/v4l2-fwnode.h>
> -#include <media/v4l2-mc.h>
> -
> -#include "stf-camss.h"
> -
> -static const char * const stfcamss_clocks[] = {
> - "wrapper_clk_c",
> - "ispcore_2x",
> - "isp_axi",
> -};
> -
> -static const char * const stfcamss_resets[] = {
> - "wrapper_p",
> - "wrapper_c",
> - "axiwr",
> - "isp_top_n",
> - "isp_top_axi",
> -};
> -
> -static const struct stf_isr_data stf_isrs[] = {
> - {"wr_irq", stf_wr_irq_handler},
> - {"isp_irq", stf_isp_irq_handler},
> - {"line_irq", stf_line_irq_handler},
> -};
> -
> -static int stfcamss_get_mem_res(struct stfcamss *stfcamss)
> -{
> - struct platform_device *pdev = to_platform_device(stfcamss->dev);
> -
> - stfcamss->syscon_base =
> - devm_platform_ioremap_resource_byname(pdev, "syscon");
> - if (IS_ERR(stfcamss->syscon_base))
> - return PTR_ERR(stfcamss->syscon_base);
> -
> - stfcamss->isp_base = devm_platform_ioremap_resource_byname(pdev,
> "isp");
> - if (IS_ERR(stfcamss->isp_base))
> - return PTR_ERR(stfcamss->isp_base);
> -
> - return 0;
> -}
> -
> -/*
> - * stfcamss_of_parse_endpoint_node - Parse port endpoint node
> - * @dev: Device
> - * @node: Device node to be parsed
> - * @csd: Parsed data from port endpoint node
> - *
> - * Return 0 on success or a negative error code on failure
> - */
> -static int stfcamss_of_parse_endpoint_node(struct stfcamss *stfcamss,
> - struct device_node *node,
> - struct stfcamss_async_subdev *csd)
> -{
> - struct v4l2_fwnode_endpoint vep = { { 0 } };
> - int ret;
> -
> - ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &vep);
> - if (ret) {
> - dev_err(stfcamss->dev, "endpoint not defined at %pOF\n", node);
> - return ret;
> - }
> -
> - csd->port = vep.base.port;
> -
> - return 0;
> -}
> -
> -/*
> - * stfcamss_of_parse_ports - Parse ports node
> - * @stfcamss: STFCAMSS device
> - *
> - * Return number of "port" nodes found in "ports" node
> - */
> -static int stfcamss_of_parse_ports(struct stfcamss *stfcamss)
> -{
> - struct device_node *node = NULL;
> - int ret, num_subdevs = 0;
> -
> - for_each_endpoint_of_node(stfcamss->dev->of_node, node) {
> - struct stfcamss_async_subdev *csd;
> -
> - if (!of_device_is_available(node))
> - continue;
> -
> - csd = v4l2_async_nf_add_fwnode_remote(&stfcamss->notifier,
> - of_fwnode_handle(node),
> - struct stfcamss_async_subdev);
> - if (IS_ERR(csd)) {
> - ret = PTR_ERR(csd);
> - dev_err(stfcamss->dev, "failed to add async notifier\n");
> - goto err_cleanup;
> - }
> -
> - ret = stfcamss_of_parse_endpoint_node(stfcamss, node, csd);
> - if (ret)
> - goto err_cleanup;
> -
> - num_subdevs++;
> - }
> -
> - return num_subdevs;
> -
> -err_cleanup:
> - of_node_put(node);
> - return ret;
> -}
> -
> -static int stfcamss_register_devs(struct stfcamss *stfcamss)
> -{
> - struct stf_capture *cap_yuv =
> &stfcamss->captures[STF_CAPTURE_YUV];
> - struct stf_isp_dev *isp_dev = &stfcamss->isp_dev;
> - int ret;
> -
> - ret = stf_isp_register(isp_dev, &stfcamss->v4l2_dev);
> - if (ret < 0) {
> - dev_err(stfcamss->dev,
> - "failed to register stf isp%d entity: %d\n", 0, ret);
> - return ret;
> - }
> -
> - ret = stf_capture_register(stfcamss, &stfcamss->v4l2_dev);
> - if (ret < 0) {
> - dev_err(stfcamss->dev,
> - "failed to register capture: %d\n", ret);
> - goto err_isp_unregister;
> - }
> -
> - ret = media_create_pad_link(&isp_dev->subdev.entity,
> STF_ISP_PAD_SRC,
> - &cap_yuv->video.vdev.entity, 0, 0);
> - if (ret)
> - goto err_cap_unregister;
> -
> - cap_yuv->video.source_subdev = &isp_dev->subdev;
> -
> - return ret;
> -
> -err_cap_unregister:
> - stf_capture_unregister(stfcamss);
> -err_isp_unregister:
> - stf_isp_unregister(&stfcamss->isp_dev);
> -
> - return ret;
> -}
> -
> -static void stfcamss_unregister_devs(struct stfcamss *stfcamss)
> -{
> - struct stf_capture *cap_yuv =
> &stfcamss->captures[STF_CAPTURE_YUV];
> - struct stf_isp_dev *isp_dev = &stfcamss->isp_dev;
> -
> - media_entity_remove_links(&isp_dev->subdev.entity);
> - media_entity_remove_links(&cap_yuv->video.vdev.entity);
> -
> - stf_isp_unregister(&stfcamss->isp_dev);
> - stf_capture_unregister(stfcamss);
> -}
> -
> -static int stfcamss_subdev_notifier_bound(struct v4l2_async_notifier *async,
> - struct v4l2_subdev *subdev,
> - struct v4l2_async_connection *asc)
> -{
> - struct stfcamss *stfcamss =
> - container_of(async, struct stfcamss, notifier);
> - struct stfcamss_async_subdev *csd =
> - container_of(asc, struct stfcamss_async_subdev, asd);
> - enum stf_port_num port = csd->port;
> - struct stf_isp_dev *isp_dev = &stfcamss->isp_dev;
> - struct stf_capture *cap_raw =
> &stfcamss->captures[STF_CAPTURE_RAW];
> - struct media_pad *pad;
> - int ret;
> -
> - if (port == STF_PORT_CSI2RX) {
> - pad = &isp_dev->pads[STF_ISP_PAD_SINK];
> - } else {
> - dev_err(stfcamss->dev, "not support port %d\n", port);
> - return -EPERM;
> - }
> -
> - ret = v4l2_create_fwnode_links_to_pad(subdev, pad, 0);
> - if (ret)
> - return ret;
> -
> - ret = media_create_pad_link(&subdev->entity, 1,
> - &cap_raw->video.vdev.entity, 0, 0);
> - if (ret)
> - return ret;
> -
> - isp_dev->source_subdev = subdev;
> - cap_raw->video.source_subdev = subdev;
> -
> - return 0;
> -}
> -
> -static int stfcamss_subdev_notifier_complete(struct v4l2_async_notifier
> *ntf)
> -{
> - struct stfcamss *stfcamss =
> - container_of(ntf, struct stfcamss, notifier);
> -
> - return v4l2_device_register_subdev_nodes(&stfcamss->v4l2_dev);
> -}
> -
> -static const struct v4l2_async_notifier_operations
> -stfcamss_subdev_notifier_ops = {
> - .bound = stfcamss_subdev_notifier_bound,
> - .complete = stfcamss_subdev_notifier_complete,
> -};
> -
> -static void stfcamss_mc_init(struct platform_device *pdev,
> - struct stfcamss *stfcamss)
> -{
> - stfcamss->media_dev.dev = stfcamss->dev;
> - strscpy(stfcamss->media_dev.model, "Starfive Camera Subsystem",
> - sizeof(stfcamss->media_dev.model));
> - media_device_init(&stfcamss->media_dev);
> -
> - stfcamss->v4l2_dev.mdev = &stfcamss->media_dev;
> -}
> -
> -/*
> - * stfcamss_probe - Probe STFCAMSS platform device
> - * @pdev: Pointer to STFCAMSS platform device
> - *
> - * Return 0 on success or a negative error code on failure
> - */
> -static int stfcamss_probe(struct platform_device *pdev)
> -{
> - struct stfcamss *stfcamss;
> - struct device *dev = &pdev->dev;
> - int ret, num_subdevs;
> - unsigned int i;
> -
> - stfcamss = devm_kzalloc(dev, sizeof(*stfcamss), GFP_KERNEL);
> - if (!stfcamss)
> - return -ENOMEM;
> -
> - stfcamss->dev = dev;
> -
> - for (i = 0; i < ARRAY_SIZE(stf_isrs); ++i) {
> - int irq;
> -
> - irq = platform_get_irq(pdev, i);
> - if (irq < 0)
> - return irq;
> -
> - ret = devm_request_irq(stfcamss->dev, irq, stf_isrs[i].isr, 0,
> - stf_isrs[i].name, stfcamss);
> - if (ret) {
> - dev_err(dev, "request irq failed: %d\n", ret);
> - return ret;
> - }
> - }
> -
> - stfcamss->nclks = ARRAY_SIZE(stfcamss->sys_clk);
> - for (i = 0; i < stfcamss->nclks; ++i)
> - stfcamss->sys_clk[i].id = stfcamss_clocks[i];
> - ret = devm_clk_bulk_get(dev, stfcamss->nclks, stfcamss->sys_clk);
> - if (ret) {
> - dev_err(dev, "Failed to get clk controls\n");
> - return ret;
> - }
> -
> - stfcamss->nrsts = ARRAY_SIZE(stfcamss->sys_rst);
> - for (i = 0; i < stfcamss->nrsts; ++i)
> - stfcamss->sys_rst[i].id = stfcamss_resets[i];
> - ret = devm_reset_control_bulk_get_shared(dev, stfcamss->nrsts,
> - stfcamss->sys_rst);
> - if (ret) {
> - dev_err(dev, "Failed to get reset controls\n");
> - return ret;
> - }
> -
> - ret = stfcamss_get_mem_res(stfcamss);
> - if (ret) {
> - dev_err(dev, "Could not map registers\n");
> - return ret;
> - }
> -
> - platform_set_drvdata(pdev, stfcamss);
> -
> - v4l2_async_nf_init(&stfcamss->notifier, &stfcamss->v4l2_dev);
> -
> - num_subdevs = stfcamss_of_parse_ports(stfcamss);
> - if (num_subdevs < 0) {
> - ret = -ENODEV;
> - dev_err(dev, "Failed to get sub devices: %d\n", ret);
> - goto err_cleanup_notifier;
> - }
> -
> - ret = stf_isp_init(stfcamss);
> - if (ret < 0) {
> - dev_err(dev, "Failed to init isp: %d\n", ret);
> - goto err_cleanup_notifier;
> - }
> -
> - stfcamss_mc_init(pdev, stfcamss);
> -
> - ret = v4l2_device_register(stfcamss->dev, &stfcamss->v4l2_dev);
> - if (ret < 0) {
> - dev_err(dev, "Failed to register V4L2 device: %d\n", ret);
> - goto err_cleanup_media_device;
> - }
> -
> - ret = media_device_register(&stfcamss->media_dev);
> - if (ret) {
> - dev_err(dev, "Failed to register media device: %d\n", ret);
> - goto err_unregister_device;
> - }
> -
> - ret = stfcamss_register_devs(stfcamss);
> - if (ret < 0) {
> - dev_err(dev, "Failed to register subdevice: %d\n", ret);
> - goto err_unregister_media_dev;
> - }
> -
> - pm_runtime_enable(dev);
> -
> - stfcamss->notifier.ops = &stfcamss_subdev_notifier_ops;
> - ret = v4l2_async_nf_register(&stfcamss->notifier);
> - if (ret) {
> - dev_err(dev, "Failed to register async subdev nodes: %d\n",
> - ret);
> - pm_runtime_disable(dev);
> - goto err_unregister_subdevs;
> - }
> -
> - return 0;
> -
> -err_unregister_subdevs:
> - stfcamss_unregister_devs(stfcamss);
> -err_unregister_media_dev:
> - media_device_unregister(&stfcamss->media_dev);
> -err_unregister_device:
> - v4l2_device_unregister(&stfcamss->v4l2_dev);
> -err_cleanup_media_device:
> - media_device_cleanup(&stfcamss->media_dev);
> -err_cleanup_notifier:
> - v4l2_async_nf_cleanup(&stfcamss->notifier);
> - return ret;
> -}
> -
> -/*
> - * stfcamss_remove - Remove STFCAMSS platform device
> - * @pdev: Pointer to STFCAMSS platform device
> - */
> -static void stfcamss_remove(struct platform_device *pdev)
> -{
> - struct stfcamss *stfcamss = platform_get_drvdata(pdev);
> -
> - stfcamss_unregister_devs(stfcamss);
> - v4l2_device_unregister(&stfcamss->v4l2_dev);
> - media_device_cleanup(&stfcamss->media_dev);
> - v4l2_async_nf_cleanup(&stfcamss->notifier);
> - pm_runtime_disable(&pdev->dev);
> -}
> -
> -static const struct of_device_id stfcamss_of_match[] = {
> - { .compatible = "starfive,jh7110-camss" },
> - { /* sentinel */ },
> -};
> -
> -MODULE_DEVICE_TABLE(of, stfcamss_of_match);
> -
> -static int __maybe_unused stfcamss_runtime_suspend(struct device *dev)
> -{
> - struct stfcamss *stfcamss = dev_get_drvdata(dev);
> - int ret;
> -
> - ret = reset_control_bulk_assert(stfcamss->nrsts, stfcamss->sys_rst);
> - if (ret) {
> - dev_err(dev, "reset assert failed\n");
> - return ret;
> - }
> -
> - clk_bulk_disable_unprepare(stfcamss->nclks, stfcamss->sys_clk);
> -
> - return 0;
> -}
> -
> -static int __maybe_unused stfcamss_runtime_resume(struct device *dev)
> -{
> - struct stfcamss *stfcamss = dev_get_drvdata(dev);
> - int ret;
> -
> - ret = clk_bulk_prepare_enable(stfcamss->nclks, stfcamss->sys_clk);
> - if (ret) {
> - dev_err(dev, "clock prepare enable failed\n");
> - return ret;
> - }
> -
> - ret = reset_control_bulk_deassert(stfcamss->nrsts, stfcamss->sys_rst);
> - if (ret < 0) {
> - dev_err(dev, "cannot deassert resets\n");
> - clk_bulk_disable_unprepare(stfcamss->nclks, stfcamss->sys_clk);
> - return ret;
> - }
> -
> - return 0;
> -}
> -
> -static const struct dev_pm_ops stfcamss_pm_ops = {
> - SET_RUNTIME_PM_OPS(stfcamss_runtime_suspend,
> - stfcamss_runtime_resume,
> - NULL)
> -};
> -
> -static struct platform_driver stfcamss_driver = {
> - .probe = stfcamss_probe,
> - .remove = stfcamss_remove,
> - .driver = {
> - .name = "starfive-camss",
> - .pm = &stfcamss_pm_ops,
> - .of_match_table = stfcamss_of_match,
> - },
> -};
> -
> -module_platform_driver(stfcamss_driver);
> -
> -MODULE_AUTHOR("Jack Zhu <jack.zhu@starfivetech.com>");
> -MODULE_AUTHOR("Changhuang Liang
> <changhuang.liang@starfivetech.com>");
> -MODULE_DESCRIPTION("StarFive Camera Subsystem driver");
> -MODULE_LICENSE("GPL");
> diff --git a/drivers/staging/media/starfive/camss/stf-camss.h
> b/drivers/staging/media/starfive/camss/stf-camss.h
> deleted file mode 100644
> index
> e2b0cfb437bdb00336cd6fe6662769b65e2adb53..0000000000000000000000
> 000000000000000000
> --- a/drivers/staging/media/starfive/camss/stf-camss.h
> +++ /dev/null
> @@ -1,134 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * stf_camss.h
> - *
> - * Starfive Camera Subsystem driver
> - *
> - * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
> - */
> -
> -#ifndef STF_CAMSS_H
> -#define STF_CAMSS_H
> -
> -#include <linux/clk.h>
> -#include <linux/delay.h>
> -#include <linux/reset.h>
> -#include <media/media-device.h>
> -#include <media/media-entity.h>
> -#include <media/v4l2-async.h>
> -#include <media/v4l2-device.h>
> -
> -#include "stf-isp.h"
> -#include "stf-capture.h"
> -
> -enum stf_port_num {
> - STF_PORT_DVP = 0,
> - STF_PORT_CSI2RX
> -};
> -
> -enum stf_clk {
> - STF_CLK_WRAPPER_CLK_C = 0,
> - STF_CLK_ISPCORE_2X,
> - STF_CLK_ISP_AXI,
> - STF_CLK_NUM
> -};
> -
> -enum stf_rst {
> - STF_RST_WRAPPER_P = 0,
> - STF_RST_WRAPPER_C,
> - STF_RST_AXIWR,
> - STF_RST_ISP_TOP_N,
> - STF_RST_ISP_TOP_AXI,
> - STF_RST_NUM
> -};
> -
> -struct stf_isr_data {
> - const char *name;
> - irqreturn_t (*isr)(int irq, void *priv);
> -};
> -
> -struct stfcamss {
> - struct v4l2_device v4l2_dev;
> - struct media_device media_dev;
> - struct media_pipeline pipe;
> - struct device *dev;
> - struct stf_isp_dev isp_dev;
> - struct stf_capture captures[STF_CAPTURE_NUM];
> - struct v4l2_async_notifier notifier;
> - void __iomem *syscon_base;
> - void __iomem *isp_base;
> - struct clk_bulk_data sys_clk[STF_CLK_NUM];
> - int nclks;
> - struct reset_control_bulk_data sys_rst[STF_RST_NUM];
> - int nrsts;
> -};
> -
> -struct stfcamss_async_subdev {
> - struct v4l2_async_connection asd; /* must be first */
> - enum stf_port_num port;
> -};
> -
> -static inline u32 stf_isp_reg_read(struct stfcamss *stfcamss, u32 reg)
> -{
> - return ioread32(stfcamss->isp_base + reg);
> -}
> -
> -static inline void stf_isp_reg_write(struct stfcamss *stfcamss,
> - u32 reg, u32 val)
> -{
> - iowrite32(val, stfcamss->isp_base + reg);
> -}
> -
> -static inline void stf_isp_reg_write_delay(struct stfcamss *stfcamss,
> - u32 reg, u32 val, u32 delay)
> -{
> - iowrite32(val, stfcamss->isp_base + reg);
> - usleep_range(1000 * delay, 1000 * delay + 100);
> -}
> -
> -static inline void stf_isp_reg_set_bit(struct stfcamss *stfcamss,
> - u32 reg, u32 mask, u32 val)
> -{
> - u32 value;
> -
> - value = ioread32(stfcamss->isp_base + reg) & ~mask;
> - val &= mask;
> - val |= value;
> - iowrite32(val, stfcamss->isp_base + reg);
> -}
> -
> -static inline void stf_isp_reg_set(struct stfcamss *stfcamss, u32 reg, u32
> mask)
> -{
> - iowrite32(ioread32(stfcamss->isp_base + reg) | mask,
> - stfcamss->isp_base + reg);
> -}
> -
> -static inline u32 stf_syscon_reg_read(struct stfcamss *stfcamss, u32 reg)
> -{
> - return ioread32(stfcamss->syscon_base + reg);
> -}
> -
> -static inline void stf_syscon_reg_write(struct stfcamss *stfcamss,
> - u32 reg, u32 val)
> -{
> - iowrite32(val, stfcamss->syscon_base + reg);
> -}
> -
> -static inline void stf_syscon_reg_set_bit(struct stfcamss *stfcamss,
> - u32 reg, u32 bit_mask)
> -{
> - u32 value;
> -
> - value = ioread32(stfcamss->syscon_base + reg);
> - iowrite32(value | bit_mask, stfcamss->syscon_base + reg);
> -}
> -
> -static inline void stf_syscon_reg_clear_bit(struct stfcamss *stfcamss,
> - u32 reg, u32 bit_mask)
> -{
> - u32 value;
> -
> - value = ioread32(stfcamss->syscon_base + reg);
> - iowrite32(value & ~bit_mask, stfcamss->syscon_base + reg);
> -}
> -#endif /* STF_CAMSS_H */
> diff --git a/drivers/staging/media/starfive/camss/stf-capture.c
> b/drivers/staging/media/starfive/camss/stf-capture.c
> deleted file mode 100644
> index
> e15d2e97eb0b6ceaf6412563a2243293dd656308..000000000000000000000
> 0000000000000000000
> --- a/drivers/staging/media/starfive/camss/stf-capture.c
> +++ /dev/null
> @@ -1,605 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * stf_capture.c
> - *
> - * StarFive Camera Subsystem - capture device
> - *
> - * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
> - */
> -
> -#include "stf-camss.h"
> -
> -static const char * const stf_cap_names[] = {
> - "capture_raw",
> - "capture_yuv",
> -};
> -
> -static const struct stfcamss_format_info stf_wr_fmts[] = {
> - {
> - .code = MEDIA_BUS_FMT_SRGGB10_1X10,
> - .pixelformat = V4L2_PIX_FMT_SRGGB10,
> - .planes = 1,
> - .vsub = { 1 },
> - .bpp = 16,
> - },
> - {
> - .code = MEDIA_BUS_FMT_SGRBG10_1X10,
> - .pixelformat = V4L2_PIX_FMT_SGRBG10,
> - .planes = 1,
> - .vsub = { 1 },
> - .bpp = 16,
> - },
> - {
> - .code = MEDIA_BUS_FMT_SGBRG10_1X10,
> - .pixelformat = V4L2_PIX_FMT_SGBRG10,
> - .planes = 1,
> - .vsub = { 1 },
> - .bpp = 16,
> - },
> - {
> - .code = MEDIA_BUS_FMT_SBGGR10_1X10,
> - .pixelformat = V4L2_PIX_FMT_SBGGR10,
> - .planes = 1,
> - .vsub = { 1 },
> - .bpp = 16,
> - },
> -};
> -
> -static const struct stfcamss_format_info stf_isp_fmts[] = {
> - {
> - .code = MEDIA_BUS_FMT_YUYV8_1_5X8,
> - .pixelformat = V4L2_PIX_FMT_NV12,
> - .planes = 2,
> - .vsub = { 1, 2 },
> - .bpp = 8,
> - },
> -};
> -
> -static inline struct stf_capture *to_stf_capture(struct stfcamss_video *video)
> -{
> - return container_of(video, struct stf_capture, video);
> -}
> -
> -static void stf_set_raw_addr(struct stfcamss *stfcamss, dma_addr_t addr)
> -{
> - stf_syscon_reg_write(stfcamss, VIN_START_ADDR_O, (long)addr);
> - stf_syscon_reg_write(stfcamss, VIN_START_ADDR_N, (long)addr);
> -}
> -
> -static void stf_set_yuv_addr(struct stfcamss *stfcamss,
> - dma_addr_t y_addr, dma_addr_t uv_addr)
> -{
> - stf_isp_reg_write(stfcamss, ISP_REG_Y_PLANE_START_ADDR, y_addr);
> - stf_isp_reg_write(stfcamss, ISP_REG_UV_PLANE_START_ADDR,
> uv_addr);
> -}
> -
> -static void stf_init_addrs(struct stfcamss_video *video)
> -{
> - struct stf_capture *cap = to_stf_capture(video);
> - struct stf_v_buf *output = &cap->buffers;
> - dma_addr_t addr0, addr1;
> -
> - output->active_buf = 0;
> -
> - if (!output->buf[0])
> - return;
> -
> - addr0 = output->buf[0]->addr[0];
> - addr1 = output->buf[0]->addr[1];
> -
> - if (cap->type == STF_CAPTURE_RAW)
> - stf_set_raw_addr(video->stfcamss, addr0);
> - else if (cap->type == STF_CAPTURE_YUV)
> - stf_set_yuv_addr(video->stfcamss, addr0, addr1);
> -}
> -
> -static struct stfcamss_buffer *stf_buf_get_pending(struct stf_v_buf *output)
> -{
> - struct stfcamss_buffer *buffer = NULL;
> -
> - if (!list_empty(&output->pending_bufs)) {
> - buffer = list_first_entry(&output->pending_bufs,
> - struct stfcamss_buffer,
> - queue);
> - list_del(&buffer->queue);
> - }
> -
> - return buffer;
> -}
> -
> -static void stf_cap_s_cfg(struct stfcamss_video *video)
> -{
> - struct stf_capture *cap = to_stf_capture(video);
> - struct stf_v_buf *output = &cap->buffers;
> - unsigned long flags;
> -
> - spin_lock_irqsave(&output->lock, flags);
> -
> - output->state = STF_OUTPUT_IDLE;
> - output->buf[0] = stf_buf_get_pending(output);
> -
> - if (!output->buf[0] && output->buf[1]) {
> - output->buf[0] = output->buf[1];
> - output->buf[1] = NULL;
> - }
> -
> - if (output->buf[0])
> - output->state = STF_OUTPUT_SINGLE;
> -
> - output->sequence = 0;
> - stf_init_addrs(video);
> -
> - spin_unlock_irqrestore(&output->lock, flags);
> -}
> -
> -static int stf_cap_s_cleanup(struct stfcamss_video *video)
> -{
> - struct stf_capture *cap = to_stf_capture(video);
> - struct stf_v_buf *output = &cap->buffers;
> - unsigned long flags;
> -
> - spin_lock_irqsave(&output->lock, flags);
> -
> - output->state = STF_OUTPUT_OFF;
> -
> - spin_unlock_irqrestore(&output->lock, flags);
> -
> - return 0;
> -}
> -
> -static void stf_wr_data_en(struct stfcamss_video *video)
> -{
> - struct stf_capture *cap = to_stf_capture(video);
> - struct stfcamss *stfcamss = cap->video.stfcamss;
> -
> - stf_syscon_reg_set_bit(stfcamss, VIN_CHANNEL_SEL_EN,
> U0_VIN_AXIWR0_EN);
> -}
> -
> -static void stf_wr_irq_enable(struct stfcamss_video *video)
> -{
> - struct stf_capture *cap = to_stf_capture(video);
> - struct stfcamss *stfcamss = cap->video.stfcamss;
> -
> - stf_syscon_reg_clear_bit(stfcamss, VIN_INRT_PIX_CFG,
> U0_VIN_INTR_M);
> -}
> -
> -static void stf_wr_irq_disable(struct stfcamss_video *video)
> -{
> - struct stf_capture *cap = to_stf_capture(video);
> - struct stfcamss *stfcamss = cap->video.stfcamss;
> -
> - stf_syscon_reg_set_bit(stfcamss, VIN_INRT_PIX_CFG,
> U0_VIN_INTR_CLEAN);
> - stf_syscon_reg_clear_bit(stfcamss, VIN_INRT_PIX_CFG,
> U0_VIN_INTR_CLEAN);
> - stf_syscon_reg_set_bit(stfcamss, VIN_INRT_PIX_CFG, U0_VIN_INTR_M);
> -}
> -
> -static void stf_channel_set(struct stfcamss_video *video)
> -{
> - struct stf_capture *cap = to_stf_capture(video);
> - struct stfcamss *stfcamss = cap->video.stfcamss;
> - u32 val;
> -
> - if (cap->type == STF_CAPTURE_RAW) {
> - const struct v4l2_pix_format *pix = &video->active_fmt.fmt.pix;
> -
> - val = stf_syscon_reg_read(stfcamss, VIN_CHANNEL_SEL_EN);
> - val &= ~U0_VIN_CHANNEL_SEL_MASK;
> - val |= CHANNEL(0);
> - stf_syscon_reg_write(stfcamss, VIN_CHANNEL_SEL_EN, val);
> -
> - val = stf_syscon_reg_read(stfcamss, VIN_INRT_PIX_CFG);
> - val &= ~U0_VIN_PIX_CT_MASK;
> - val |= PIX_CT(1);
> -
> - val &= ~U0_VIN_PIXEL_HEIGH_BIT_SEL_MAKS;
> - val |= PIXEL_HEIGH_BIT_SEL(0);
> -
> - val &= ~U0_VIN_PIX_CNT_END_MASK;
> - val |= PIX_CNT_END(pix->width / 4 - 1);
> -
> - stf_syscon_reg_write(stfcamss, VIN_INRT_PIX_CFG, val);
> - } else if (cap->type == STF_CAPTURE_YUV) {
> - val = stf_syscon_reg_read(stfcamss, VIN_CFG_REG);
> - val &= ~U0_VIN_MIPI_BYTE_EN_ISP0_MASK;
> - val |= U0_VIN_MIPI_BYTE_EN_ISP0(0);
> -
> - val &= ~U0_VIN_MIPI_CHANNEL_SEL0_MASK;
> - val |= U0_VIN_MIPI_CHANNEL_SEL0(0);
> -
> - val &= ~U0_VIN_PIX_NUM_MASK;
> - val |= U0_VIN_PIX_NUM(0);
> -
> - val &= ~U0_VIN_P_I_MIPI_HAEDER_EN0_MASK;
> - val |= U0_VIN_P_I_MIPI_HAEDER_EN0(1);
> -
> - stf_syscon_reg_write(stfcamss, VIN_CFG_REG, val);
> - }
> -}
> -
> -static void stf_capture_start(struct stfcamss_video *video)
> -{
> - struct stf_capture *cap = to_stf_capture(video);
> -
> - stf_channel_set(video);
> - if (cap->type == STF_CAPTURE_RAW) {
> - stf_wr_irq_enable(video);
> - stf_wr_data_en(video);
> - }
> -
> - stf_cap_s_cfg(video);
> -}
> -
> -static void stf_capture_stop(struct stfcamss_video *video)
> -{
> - struct stf_capture *cap = to_stf_capture(video);
> -
> - if (cap->type == STF_CAPTURE_RAW)
> - stf_wr_irq_disable(video);
> -
> - stf_cap_s_cleanup(video);
> -}
> -
> -static void stf_capture_init(struct stfcamss *stfcamss, struct stf_capture
> *cap)
> -{
> - cap->buffers.state = STF_OUTPUT_OFF;
> - cap->buffers.buf[0] = NULL;
> - cap->buffers.buf[1] = NULL;
> - cap->buffers.active_buf = 0;
> - atomic_set(&cap->buffers.frame_skip, 4);
> - INIT_LIST_HEAD(&cap->buffers.pending_bufs);
> - INIT_LIST_HEAD(&cap->buffers.ready_bufs);
> - spin_lock_init(&cap->buffers.lock);
> -
> - cap->video.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
> - cap->video.stfcamss = stfcamss;
> - cap->video.bpl_alignment = 16 * 8;
> -
> - if (cap->type == STF_CAPTURE_RAW) {
> - cap->video.formats = stf_wr_fmts;
> - cap->video.nformats = ARRAY_SIZE(stf_wr_fmts);
> - cap->video.bpl_alignment = 8;
> - } else if (cap->type == STF_CAPTURE_YUV) {
> - cap->video.formats = stf_isp_fmts;
> - cap->video.nformats = ARRAY_SIZE(stf_isp_fmts);
> - cap->video.bpl_alignment = 1;
> - }
> -}
> -
> -static void stf_buf_add_ready(struct stf_v_buf *output,
> - struct stfcamss_buffer *buffer)
> -{
> - INIT_LIST_HEAD(&buffer->queue);
> - list_add_tail(&buffer->queue, &output->ready_bufs);
> -}
> -
> -static struct stfcamss_buffer *stf_buf_get_ready(struct stf_v_buf *output)
> -{
> - struct stfcamss_buffer *buffer = NULL;
> -
> - if (!list_empty(&output->ready_bufs)) {
> - buffer = list_first_entry(&output->ready_bufs,
> - struct stfcamss_buffer,
> - queue);
> - list_del(&buffer->queue);
> - }
> -
> - return buffer;
> -}
> -
> -static void stf_buf_add_pending(struct stf_v_buf *output,
> - struct stfcamss_buffer *buffer)
> -{
> - INIT_LIST_HEAD(&buffer->queue);
> - list_add_tail(&buffer->queue, &output->pending_bufs);
> -}
> -
> -static void stf_buf_update_on_last(struct stf_v_buf *output)
> -{
> - switch (output->state) {
> - case STF_OUTPUT_CONTINUOUS:
> - output->state = STF_OUTPUT_SINGLE;
> - output->active_buf = !output->active_buf;
> - break;
> - case STF_OUTPUT_SINGLE:
> - output->state = STF_OUTPUT_STOPPING;
> - break;
> - default:
> - break;
> - }
> -}
> -
> -static void stf_buf_update_on_next(struct stf_v_buf *output)
> -{
> - switch (output->state) {
> - case STF_OUTPUT_CONTINUOUS:
> - output->active_buf = !output->active_buf;
> - break;
> - case STF_OUTPUT_SINGLE:
> - default:
> - break;
> - }
> -}
> -
> -static void stf_buf_update_on_new(struct stfcamss_video *video,
> - struct stfcamss_buffer *new_buf)
> -{
> - struct stf_capture *cap = to_stf_capture(video);
> - struct stf_v_buf *output = &cap->buffers;
> -
> - switch (output->state) {
> - case STF_OUTPUT_SINGLE:
> - stf_buf_add_pending(output, new_buf);
> - break;
> - case STF_OUTPUT_IDLE:
> - if (!output->buf[0]) {
> - output->buf[0] = new_buf;
> - stf_init_addrs(video);
> - output->state = STF_OUTPUT_SINGLE;
> - } else {
> - stf_buf_add_pending(output, new_buf);
> - }
> - break;
> - case STF_OUTPUT_STOPPING:
> - if (output->last_buffer) {
> - output->buf[output->active_buf] = output->last_buffer;
> - output->last_buffer = NULL;
> - }
> -
> - output->state = STF_OUTPUT_SINGLE;
> - stf_buf_add_pending(output, new_buf);
> - break;
> - case STF_OUTPUT_CONTINUOUS:
> - default:
> - stf_buf_add_pending(output, new_buf);
> - break;
> - }
> -}
> -
> -static void stf_buf_flush(struct stf_v_buf *output, enum vb2_buffer_state
> state)
> -{
> - struct stfcamss_buffer *buf;
> - struct stfcamss_buffer *t;
> -
> - list_for_each_entry_safe(buf, t, &output->pending_bufs, queue) {
> - vb2_buffer_done(&buf->vb.vb2_buf, state);
> - list_del(&buf->queue);
> - }
> - list_for_each_entry_safe(buf, t, &output->ready_bufs, queue) {
> - vb2_buffer_done(&buf->vb.vb2_buf, state);
> - list_del(&buf->queue);
> - }
> -}
> -
> -static void stf_buf_done(struct stf_v_buf *output)
> -{
> - struct stfcamss_buffer *ready_buf;
> - u64 ts = ktime_get_ns();
> - unsigned long flags;
> -
> - if (output->state == STF_OUTPUT_OFF ||
> - output->state == STF_OUTPUT_RESERVED)
> - return;
> -
> - spin_lock_irqsave(&output->lock, flags);
> -
> - while ((ready_buf = stf_buf_get_ready(output))) {
> - ready_buf->vb.vb2_buf.timestamp = ts;
> - ready_buf->vb.sequence = output->sequence++;
> -
> - vb2_buffer_done(&ready_buf->vb.vb2_buf,
> VB2_BUF_STATE_DONE);
> - }
> -
> - spin_unlock_irqrestore(&output->lock, flags);
> -}
> -
> -static void stf_change_buffer(struct stf_v_buf *output)
> -{
> - struct stf_capture *cap = container_of(output, struct stf_capture,
> - buffers);
> - struct stfcamss *stfcamss = cap->video.stfcamss;
> - struct stfcamss_buffer *ready_buf;
> - dma_addr_t *new_addr;
> - unsigned long flags;
> - u32 active_index;
> -
> - if (output->state == STF_OUTPUT_OFF ||
> - output->state == STF_OUTPUT_STOPPING ||
> - output->state == STF_OUTPUT_RESERVED ||
> - output->state == STF_OUTPUT_IDLE)
> - return;
> -
> - spin_lock_irqsave(&output->lock, flags);
> -
> - active_index = output->active_buf;
> -
> - ready_buf = output->buf[active_index];
> - if (!ready_buf) {
> - dev_dbg(stfcamss->dev, "missing ready buf %d %d.\n",
> - active_index, output->state);
> - active_index = !active_index;
> - ready_buf = output->buf[active_index];
> - if (!ready_buf) {
> - dev_dbg(stfcamss->dev,
> - "missing ready buf2 %d %d.\n",
> - active_index, output->state);
> - goto out_unlock;
> - }
> - }
> -
> - /* Get next buffer */
> - output->buf[active_index] = stf_buf_get_pending(output);
> - if (!output->buf[active_index]) {
> - new_addr = ready_buf->addr;
> - stf_buf_update_on_last(output);
> - } else {
> - new_addr = output->buf[active_index]->addr;
> - stf_buf_update_on_next(output);
> - }
> -
> - if (output->state == STF_OUTPUT_STOPPING) {
> - output->last_buffer = ready_buf;
> - } else {
> - if (cap->type == STF_CAPTURE_RAW)
> - stf_set_raw_addr(stfcamss, new_addr[0]);
> - else if (cap->type == STF_CAPTURE_YUV)
> - stf_set_yuv_addr(stfcamss, new_addr[0], new_addr[1]);
> -
> - stf_buf_add_ready(output, ready_buf);
> - }
> -
> -out_unlock:
> - spin_unlock_irqrestore(&output->lock, flags);
> -}
> -
> -irqreturn_t stf_wr_irq_handler(int irq, void *priv)
> -{
> - struct stfcamss *stfcamss = priv;
> - struct stf_capture *cap = &stfcamss->captures[STF_CAPTURE_RAW];
> -
> - if (atomic_dec_if_positive(&cap->buffers.frame_skip) < 0) {
> - stf_change_buffer(&cap->buffers);
> - stf_buf_done(&cap->buffers);
> - }
> -
> - stf_syscon_reg_set_bit(stfcamss, VIN_INRT_PIX_CFG,
> U0_VIN_INTR_CLEAN);
> - stf_syscon_reg_clear_bit(stfcamss, VIN_INRT_PIX_CFG,
> U0_VIN_INTR_CLEAN);
> -
> - return IRQ_HANDLED;
> -}
> -
> -irqreturn_t stf_isp_irq_handler(int irq, void *priv)
> -{
> - struct stfcamss *stfcamss = priv;
> - struct stf_capture *cap = &stfcamss->captures[STF_CAPTURE_YUV];
> - u32 status;
> -
> - status = stf_isp_reg_read(stfcamss, ISP_REG_ISP_CTRL_0);
> - if (status & ISPC_ISP) {
> - if (status & ISPC_ENUO)
> - stf_buf_done(&cap->buffers);
> -
> - stf_isp_reg_write(stfcamss, ISP_REG_ISP_CTRL_0,
> - (status & ~ISPC_INT_ALL_MASK) |
> - ISPC_ISP | ISPC_CSI | ISPC_SC);
> - }
> -
> - return IRQ_HANDLED;
> -}
> -
> -irqreturn_t stf_line_irq_handler(int irq, void *priv)
> -{
> - struct stfcamss *stfcamss = priv;
> - struct stf_capture *cap = &stfcamss->captures[STF_CAPTURE_YUV];
> - u32 status;
> -
> - status = stf_isp_reg_read(stfcamss, ISP_REG_ISP_CTRL_0);
> - if (status & ISPC_LINE) {
> - if (atomic_dec_if_positive(&cap->buffers.frame_skip) < 0) {
> - if ((status & ISPC_ENUO))
> - stf_change_buffer(&cap->buffers);
> - }
> -
> - stf_isp_reg_set_bit(stfcamss, ISP_REG_CSIINTS,
> - CSI_INTS_MASK, CSI_INTS(0x3));
> - stf_isp_reg_set_bit(stfcamss, ISP_REG_IESHD,
> - SHAD_UP_M | SHAD_UP_EN, 0x3);
> -
> - stf_isp_reg_write(stfcamss, ISP_REG_ISP_CTRL_0,
> - (status & ~ISPC_INT_ALL_MASK) | ISPC_LINE);
> - }
> -
> - return IRQ_HANDLED;
> -}
> -
> -static int stf_queue_buffer(struct stfcamss_video *video,
> - struct stfcamss_buffer *buf)
> -{
> - struct stf_capture *cap = to_stf_capture(video);
> - struct stf_v_buf *v_bufs = &cap->buffers;
> - unsigned long flags;
> -
> - spin_lock_irqsave(&v_bufs->lock, flags);
> - stf_buf_update_on_new(video, buf);
> - spin_unlock_irqrestore(&v_bufs->lock, flags);
> -
> - return 0;
> -}
> -
> -static int stf_flush_buffers(struct stfcamss_video *video,
> - enum vb2_buffer_state state)
> -{
> - struct stf_capture *cap = to_stf_capture(video);
> - struct stf_v_buf *v_bufs = &cap->buffers;
> - unsigned long flags;
> - unsigned int i;
> -
> - spin_lock_irqsave(&v_bufs->lock, flags);
> -
> - stf_buf_flush(v_bufs, state);
> -
> - for (i = 0; i < ARRAY_SIZE(v_bufs->buf); i++) {
> - if (v_bufs->buf[i])
> - vb2_buffer_done(&v_bufs->buf[i]->vb.vb2_buf, state);
> -
> - v_bufs->buf[i] = NULL;
> - }
> -
> - if (v_bufs->last_buffer) {
> - vb2_buffer_done(&v_bufs->last_buffer->vb.vb2_buf, state);
> - v_bufs->last_buffer = NULL;
> - }
> -
> - spin_unlock_irqrestore(&v_bufs->lock, flags);
> - return 0;
> -}
> -
> -static const struct stfcamss_video_ops stf_capture_ops = {
> - .queue_buffer = stf_queue_buffer,
> - .flush_buffers = stf_flush_buffers,
> - .start_streaming = stf_capture_start,
> - .stop_streaming = stf_capture_stop,
> -};
> -
> -static void stf_capture_unregister_one(struct stf_capture *cap)
> -{
> - if (!video_is_registered(&cap->video.vdev))
> - return;
> -
> - media_entity_cleanup(&cap->video.vdev.entity);
> - vb2_video_unregister_device(&cap->video.vdev);
> -}
> -
> -void stf_capture_unregister(struct stfcamss *stfcamss)
> -{
> - struct stf_capture *cap_raw =
> &stfcamss->captures[STF_CAPTURE_RAW];
> - struct stf_capture *cap_yuv =
> &stfcamss->captures[STF_CAPTURE_YUV];
> -
> - stf_capture_unregister_one(cap_raw);
> - stf_capture_unregister_one(cap_yuv);
> -}
> -
> -int stf_capture_register(struct stfcamss *stfcamss,
> - struct v4l2_device *v4l2_dev)
> -{
> - unsigned int i;
> - int ret;
> -
> - for (i = 0; i < ARRAY_SIZE(stfcamss->captures); i++) {
> - struct stf_capture *capture = &stfcamss->captures[i];
> -
> - capture->type = i;
> - capture->video.ops = &stf_capture_ops;
> - stf_capture_init(stfcamss, capture);
> -
> - ret = stf_video_register(&capture->video, v4l2_dev,
> - stf_cap_names[i]);
> - if (ret < 0) {
> - dev_err(stfcamss->dev,
> - "Failed to register video node: %d\n", ret);
> - stf_capture_unregister(stfcamss);
> - return ret;
> - }
> - }
> -
> - return 0;
> -}
> diff --git a/drivers/staging/media/starfive/camss/stf-capture.h
> b/drivers/staging/media/starfive/camss/stf-capture.h
> deleted file mode 100644
> index
> 2f9740b7e500a9521108b6461ebe16c96ab641d1..000000000000000000000
> 0000000000000000000
> --- a/drivers/staging/media/starfive/camss/stf-capture.h
> +++ /dev/null
> @@ -1,86 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * stf_capture.h
> - *
> - * Starfive Camera Subsystem driver
> - *
> - * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
> - */
> -
> -#ifndef STF_CAPTURE_H
> -#define STF_CAPTURE_H
> -
> -#include "stf-video.h"
> -
> -#define VIN_CHANNEL_SEL_EN 0x14
> -#define VIN_START_ADDR_N 0x18
> -#define VIN_INRT_PIX_CFG 0x1c
> -#define VIN_START_ADDR_O 0x20
> -#define VIN_CFG_REG 0x24
> -
> -#define U0_VIN_CNFG_AXI_DVP_EN BIT(2)
> -
> -#define U0_VIN_CHANNEL_SEL_MASK GENMASK(3, 0)
> -#define U0_VIN_AXIWR0_EN BIT(4)
> -#define CHANNEL(x) ((x) << 0)
> -
> -#define U0_VIN_INTR_CLEAN BIT(0)
> -#define U0_VIN_INTR_M BIT(1)
> -#define U0_VIN_PIX_CNT_END_MASK GENMASK(12, 2)
> -#define U0_VIN_PIX_CT_MASK GENMASK(14, 13)
> -#define U0_VIN_PIXEL_HEIGH_BIT_SEL_MAKS GENMASK(16, 15)
> -
> -#define PIX_CNT_END(x) ((x) << 2)
> -#define PIX_CT(x) ((x) << 13)
> -#define PIXEL_HEIGH_BIT_SEL(x) ((x) << 15)
> -
> -#define U0_VIN_CNFG_DVP_HS_POS BIT(1)
> -#define U0_VIN_CNFG_DVP_SWAP_EN BIT(2)
> -#define U0_VIN_CNFG_DVP_VS_POS BIT(3)
> -#define U0_VIN_CNFG_GEN_EN_AXIRD BIT(4)
> -#define U0_VIN_CNFG_ISP_DVP_EN0 BIT(5)
> -#define U0_VIN_MIPI_BYTE_EN_ISP0(n) ((n) << 6)
> -#define U0_VIN_MIPI_CHANNEL_SEL0(n) ((n) << 8)
> -#define U0_VIN_P_I_MIPI_HAEDER_EN0(n) ((n) << 12)
> -#define U0_VIN_PIX_NUM(n) ((n) << 13)
> -#define U0_VIN_MIPI_BYTE_EN_ISP0_MASK GENMASK(7, 6)
> -#define U0_VIN_MIPI_CHANNEL_SEL0_MASK GENMASK(11, 8)
> -#define U0_VIN_P_I_MIPI_HAEDER_EN0_MASK BIT(12)
> -#define U0_VIN_PIX_NUM_MASK GENMASK(16, 13)
> -
> -enum stf_v_state {
> - STF_OUTPUT_OFF,
> - STF_OUTPUT_RESERVED,
> - STF_OUTPUT_SINGLE,
> - STF_OUTPUT_CONTINUOUS,
> - STF_OUTPUT_IDLE,
> - STF_OUTPUT_STOPPING
> -};
> -
> -struct stf_v_buf {
> - int active_buf;
> - struct stfcamss_buffer *buf[2];
> - struct stfcamss_buffer *last_buffer;
> - struct list_head pending_bufs;
> - struct list_head ready_bufs;
> - enum stf_v_state state;
> - unsigned int sequence;
> - /* protects the above member variables */
> - spinlock_t lock;
> - atomic_t frame_skip;
> -};
> -
> -struct stf_capture {
> - struct stfcamss_video video;
> - struct stf_v_buf buffers;
> - enum stf_capture_type type;
> -};
> -
> -irqreturn_t stf_wr_irq_handler(int irq, void *priv);
> -irqreturn_t stf_isp_irq_handler(int irq, void *priv);
> -irqreturn_t stf_line_irq_handler(int irq, void *priv);
> -int stf_capture_register(struct stfcamss *stfcamss,
> - struct v4l2_device *v4l2_dev);
> -void stf_capture_unregister(struct stfcamss *stfcamss);
> -
> -#endif
> diff --git a/drivers/staging/media/starfive/camss/stf-isp-hw-ops.c
> b/drivers/staging/media/starfive/camss/stf-isp-hw-ops.c
> deleted file mode 100644
> index
> c34631ff94227134d960423c4b84ef17df7c164b..00000000000000000000000
> 00000000000000000
> --- a/drivers/staging/media/starfive/camss/stf-isp-hw-ops.c
> +++ /dev/null
> @@ -1,445 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * stf_isp_hw_ops.c
> - *
> - * Register interface file for StarFive ISP driver
> - *
> - * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
> - *
> - */
> -
> -#include "stf-camss.h"
> -
> -static void stf_isp_config_obc(struct stfcamss *stfcamss)
> -{
> - u32 reg_val, reg_add;
> -
> - stf_isp_reg_write(stfcamss, ISP_REG_OBC_CFG, OBC_W_H(11) |
> OBC_W_W(11));
> -
> - reg_val = GAIN_D_POINT(0x40) | GAIN_C_POINT(0x40) |
> - GAIN_B_POINT(0x40) | GAIN_A_POINT(0x40);
> - for (reg_add = ISP_REG_OBCG_CFG_0; reg_add <=
> ISP_REG_OBCG_CFG_3;) {
> - stf_isp_reg_write(stfcamss, reg_add, reg_val);
> - reg_add += 4;
> - }
> -
> - reg_val = OFFSET_D_POINT(0) | OFFSET_C_POINT(0) |
> - OFFSET_B_POINT(0) | OFFSET_A_POINT(0);
> - for (reg_add = ISP_REG_OBCO_CFG_0; reg_add <=
> ISP_REG_OBCO_CFG_3;) {
> - stf_isp_reg_write(stfcamss, reg_add, reg_val);
> - reg_add += 4;
> - }
> -}
> -
> -static void stf_isp_config_oecf(struct stfcamss *stfcamss)
> -{
> - u32 reg_add, par_val;
> - u16 par_h, par_l;
> -
> - par_h = 0x10; par_l = 0;
> - par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
> - for (reg_add = ISP_REG_OECF_X0_CFG0; reg_add <=
> ISP_REG_OECF_Y3_CFG0;) {
> - stf_isp_reg_write(stfcamss, reg_add, par_val);
> - reg_add += 0x20;
> - }
> -
> - par_h = 0x40; par_l = 0x20;
> - par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
> - for (reg_add = ISP_REG_OECF_X0_CFG1; reg_add <=
> ISP_REG_OECF_Y3_CFG1;) {
> - stf_isp_reg_write(stfcamss, reg_add, par_val);
> - reg_add += 0x20;
> - }
> -
> - par_h = 0x80; par_l = 0x60;
> - par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
> - for (reg_add = ISP_REG_OECF_X0_CFG2; reg_add <=
> ISP_REG_OECF_Y3_CFG2;) {
> - stf_isp_reg_write(stfcamss, reg_add, par_val);
> - reg_add += 0x20;
> - }
> -
> - par_h = 0xc0; par_l = 0xa0;
> - par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
> - for (reg_add = ISP_REG_OECF_X0_CFG3; reg_add <=
> ISP_REG_OECF_Y3_CFG3;) {
> - stf_isp_reg_write(stfcamss, reg_add, par_val);
> - reg_add += 0x20;
> - }
> -
> - par_h = 0x100; par_l = 0xe0;
> - par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
> - for (reg_add = ISP_REG_OECF_X0_CFG4; reg_add <=
> ISP_REG_OECF_Y3_CFG4;) {
> - stf_isp_reg_write(stfcamss, reg_add, par_val);
> - reg_add += 0x20;
> - }
> -
> - par_h = 0x200; par_l = 0x180;
> - par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
> - for (reg_add = ISP_REG_OECF_X0_CFG5; reg_add <=
> ISP_REG_OECF_Y3_CFG5;) {
> - stf_isp_reg_write(stfcamss, reg_add, par_val);
> - reg_add += 0x20;
> - }
> -
> - par_h = 0x300; par_l = 0x280;
> - par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
> - for (reg_add = ISP_REG_OECF_X0_CFG6; reg_add <=
> ISP_REG_OECF_Y3_CFG6;) {
> - stf_isp_reg_write(stfcamss, reg_add, par_val);
> - reg_add += 0x20;
> - }
> -
> - par_h = 0x3fe; par_l = 0x380;
> - par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
> - for (reg_add = ISP_REG_OECF_X0_CFG7; reg_add <=
> ISP_REG_OECF_Y3_CFG7;) {
> - stf_isp_reg_write(stfcamss, reg_add, par_val);
> - reg_add += 0x20;
> - }
> -
> - par_h = 0x80; par_l = 0x80;
> - par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l);
> - for (reg_add = ISP_REG_OECF_S0_CFG0; reg_add <=
> ISP_REG_OECF_S3_CFG7;) {
> - stf_isp_reg_write(stfcamss, reg_add, par_val);
> - reg_add += 4;
> - }
> -}
> -
> -static void stf_isp_config_lccf(struct stfcamss *stfcamss)
> -{
> - u32 reg_add;
> -
> - stf_isp_reg_write(stfcamss, ISP_REG_LCCF_CFG_0,
> - Y_DISTANCE(0x21C) | X_DISTANCE(0x3C0));
> - stf_isp_reg_write(stfcamss, ISP_REG_LCCF_CFG_1,
> LCCF_MAX_DIS(0xb));
> -
> - for (reg_add = ISP_REG_LCCF_CFG_2; reg_add <= ISP_REG_LCCF_CFG_5;)
> {
> - stf_isp_reg_write(stfcamss, reg_add,
> - LCCF_F2_PAR(0x0) | LCCF_F1_PAR(0x0));
> - reg_add += 4;
> - }
> -}
> -
> -static void stf_isp_config_awb(struct stfcamss *stfcamss)
> -{
> - u32 reg_val, reg_add;
> - u16 symbol_h, symbol_l;
> -
> - symbol_h = 0x0; symbol_l = 0x0;
> - reg_val = AWB_X_SYMBOL_H(symbol_h) |
> AWB_X_SYMBOL_L(symbol_l);
> -
> - for (reg_add = ISP_REG_AWB_X0_CFG_0; reg_add <=
> ISP_REG_AWB_X3_CFG_1;) {
> - stf_isp_reg_write(stfcamss, reg_add, reg_val);
> - reg_add += 4;
> - }
> -
> - symbol_h = 0x0, symbol_l = 0x0;
> - reg_val = AWB_Y_SYMBOL_H(symbol_h) |
> AWB_Y_SYMBOL_L(symbol_l);
> -
> - for (reg_add = ISP_REG_AWB_Y0_CFG_0; reg_add <=
> ISP_REG_AWB_Y3_CFG_1;) {
> - stf_isp_reg_write(stfcamss, reg_add, reg_val);
> - reg_add += 4;
> - }
> -
> - symbol_h = 0x80, symbol_l = 0x80;
> - reg_val = AWB_S_SYMBOL_H(symbol_h) |
> AWB_S_SYMBOL_L(symbol_l);
> -
> - for (reg_add = ISP_REG_AWB_S0_CFG_0; reg_add <=
> ISP_REG_AWB_S3_CFG_1;) {
> - stf_isp_reg_write(stfcamss, reg_add, reg_val);
> - reg_add += 4;
> - }
> -}
> -
> -static void stf_isp_config_grgb(struct stfcamss *stfcamss)
> -{
> - stf_isp_reg_write(stfcamss, ISP_REG_ICTC,
> - GF_MODE(1) | MAXGT(0x140) | MINGT(0x40));
> - stf_isp_reg_write(stfcamss, ISP_REG_IDBC, BADGT(0x200) |
> BADXT(0x200));
> -}
> -
> -static void stf_isp_config_cfa(struct stfcamss *stfcamss)
> -{
> - stf_isp_reg_write(stfcamss, ISP_REG_RAW_FORMAT_CFG,
> - SMY13(0) | SMY12(1) | SMY11(0) | SMY10(1) | SMY3(2) |
> - SMY2(3) | SMY1(2) | SMY0(3));
> - stf_isp_reg_write(stfcamss, ISP_REG_ICFAM, CROSS_COV(3) | HV_W(2));
> -}
> -
> -static void stf_isp_config_ccm(struct stfcamss *stfcamss)
> -{
> - u32 reg_add;
> -
> - stf_isp_reg_write(stfcamss, ISP_REG_ICAMD_0, DNRM_F(6) |
> CCM_M_DAT(0));
> -
> - for (reg_add = ISP_REG_ICAMD_12; reg_add <= ISP_REG_ICAMD_20;) {
> - stf_isp_reg_write(stfcamss, reg_add, CCM_M_DAT(0x80));
> - reg_add += 0x10;
> - }
> -
> - stf_isp_reg_write(stfcamss, ISP_REG_ICAMD_24, CCM_M_DAT(0x700));
> - stf_isp_reg_write(stfcamss, ISP_REG_ICAMD_25, CCM_M_DAT(0x200));
> -}
> -
> -static void stf_isp_config_gamma(struct stfcamss *stfcamss)
> -{
> - u32 reg_val, reg_add;
> - u16 gamma_slope_v, gamma_v;
> -
> - gamma_slope_v = 0x2400; gamma_v = 0x0;
> - reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v);
> - stf_isp_reg_write(stfcamss, ISP_REG_GAMMA_VAL0, reg_val);
> -
> - gamma_slope_v = 0x800; gamma_v = 0x20;
> - for (reg_add = ISP_REG_GAMMA_VAL1; reg_add <=
> ISP_REG_GAMMA_VAL7;) {
> - reg_val = GAMMA_S_VAL(gamma_slope_v) |
> GAMMA_VAL(gamma_v);
> - stf_isp_reg_write(stfcamss, reg_add, reg_val);
> - reg_add += 4;
> - gamma_v += 0x20;
> - }
> -
> - gamma_v = 0x100;
> - for (reg_add = ISP_REG_GAMMA_VAL8; reg_add <=
> ISP_REG_GAMMA_VAL13;) {
> - reg_val = GAMMA_S_VAL(gamma_slope_v) |
> GAMMA_VAL(gamma_v);
> - stf_isp_reg_write(stfcamss, reg_add, reg_val);
> - reg_add += 4;
> - gamma_v += 0x80;
> - }
> -
> - gamma_v = 0x3fe;
> - reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v);
> - stf_isp_reg_write(stfcamss, ISP_REG_GAMMA_VAL14, reg_val);
> -}
> -
> -static void stf_isp_config_r2y(struct stfcamss *stfcamss)
> -{
> - stf_isp_reg_write(stfcamss, ISP_REG_R2Y_0, 0x4C);
> - stf_isp_reg_write(stfcamss, ISP_REG_R2Y_1, 0x97);
> - stf_isp_reg_write(stfcamss, ISP_REG_R2Y_2, 0x1d);
> - stf_isp_reg_write(stfcamss, ISP_REG_R2Y_3, 0x1d5);
> - stf_isp_reg_write(stfcamss, ISP_REG_R2Y_4, 0x1ac);
> - stf_isp_reg_write(stfcamss, ISP_REG_R2Y_5, 0x80);
> - stf_isp_reg_write(stfcamss, ISP_REG_R2Y_6, 0x80);
> - stf_isp_reg_write(stfcamss, ISP_REG_R2Y_7, 0x194);
> - stf_isp_reg_write(stfcamss, ISP_REG_R2Y_8, 0x1ec);
> -}
> -
> -static void stf_isp_config_y_curve(struct stfcamss *stfcamss)
> -{
> - u32 reg_add;
> - u16 y_curve;
> -
> - y_curve = 0x0;
> - for (reg_add = ISP_REG_YCURVE_0; reg_add <= ISP_REG_YCURVE_63;) {
> - stf_isp_reg_write(stfcamss, reg_add, y_curve);
> - reg_add += 4;
> - y_curve += 0x10;
> - }
> -}
> -
> -static void stf_isp_config_sharpen(struct stfcamss *sc)
> -{
> - u32 reg_add;
> -
> - stf_isp_reg_write(sc, ISP_REG_SHARPEN0, S_DELTA(0x7) |
> S_WEIGHT(0xf));
> - stf_isp_reg_write(sc, ISP_REG_SHARPEN1, S_DELTA(0x18) |
> S_WEIGHT(0xf));
> - stf_isp_reg_write(sc, ISP_REG_SHARPEN2, S_DELTA(0x80) |
> S_WEIGHT(0xf));
> - stf_isp_reg_write(sc, ISP_REG_SHARPEN3, S_DELTA(0x100) |
> S_WEIGHT(0xf));
> - stf_isp_reg_write(sc, ISP_REG_SHARPEN4, S_DELTA(0x10) |
> S_WEIGHT(0xf));
> - stf_isp_reg_write(sc, ISP_REG_SHARPEN5, S_DELTA(0x60) |
> S_WEIGHT(0xf));
> - stf_isp_reg_write(sc, ISP_REG_SHARPEN6, S_DELTA(0x100) |
> S_WEIGHT(0xf));
> - stf_isp_reg_write(sc, ISP_REG_SHARPEN7, S_DELTA(0x190) |
> S_WEIGHT(0xf));
> - stf_isp_reg_write(sc, ISP_REG_SHARPEN8, S_DELTA(0x0) |
> S_WEIGHT(0xf));
> -
> - for (reg_add = ISP_REG_SHARPEN9; reg_add <= ISP_REG_SHARPEN14;) {
> - stf_isp_reg_write(sc, reg_add, S_WEIGHT(0xf));
> - reg_add += 4;
> - }
> -
> - for (reg_add = ISP_REG_SHARPEN_FS0; reg_add <=
> ISP_REG_SHARPEN_FS5;) {
> - stf_isp_reg_write(sc, reg_add, S_FACTOR(0x10) | S_SLOPE(0x0));
> - reg_add += 4;
> - }
> -
> - stf_isp_reg_write(sc, ISP_REG_SHARPEN_WN,
> - PDIRF(0x8) | NDIRF(0x8) | WSUM(0xd7c));
> - stf_isp_reg_write(sc, ISP_REG_IUVS1, UVDIFF2(0xC0) | UVDIFF1(0x40));
> - stf_isp_reg_write(sc, ISP_REG_IUVS2, UVF(0xff) | UVSLOPE(0x0));
> - stf_isp_reg_write(sc, ISP_REG_IUVCKS1,
> - UVCKDIFF2(0xa0) | UVCKDIFF1(0x40));
> -}
> -
> -static void stf_isp_config_dnyuv(struct stfcamss *stfcamss)
> -{
> - u32 reg_val;
> -
> - reg_val = YUVSW5(7) | YUVSW4(7) | YUVSW3(7) | YUVSW2(7) |
> - YUVSW1(7) | YUVSW0(7);
> - stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YSWR0, reg_val);
> - stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CSWR0, reg_val);
> -
> - reg_val = YUVSW3(7) | YUVSW2(7) | YUVSW1(7) | YUVSW0(7);
> - stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YSWR1, reg_val);
> - stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CSWR1, reg_val);
> -
> - reg_val = CURVE_D_H(0x60) | CURVE_D_L(0x40);
> - stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR0, reg_val);
> - stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR0, reg_val);
> -
> - reg_val = CURVE_D_H(0xd8) | CURVE_D_L(0x90);
> - stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR1, reg_val);
> - stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR1, reg_val);
> -
> - reg_val = CURVE_D_H(0x1e6) | CURVE_D_L(0x144);
> - stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR2, reg_val);
> - stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR2, reg_val);
> -}
> -
> -static void stf_isp_config_sat(struct stfcamss *stfcamss)
> -{
> - stf_isp_reg_write(stfcamss, ISP_REG_CS_GAIN, CMAD(0x0) |
> CMAB(0x100));
> - stf_isp_reg_write(stfcamss, ISP_REG_CS_THRESHOLD, CMD(0x1f) |
> CMB(0x1));
> - stf_isp_reg_write(stfcamss, ISP_REG_CS_OFFSET, VOFF(0x0) |
> UOFF(0x0));
> - stf_isp_reg_write(stfcamss, ISP_REG_CS_HUE_F, SIN(0x0) | COS(0x100));
> - stf_isp_reg_write(stfcamss, ISP_REG_CS_SCALE, 0x8);
> - stf_isp_reg_write(stfcamss, ISP_REG_YADJ0, YOIR(0x401) | YIMIN(0x1));
> - stf_isp_reg_write(stfcamss, ISP_REG_YADJ1, YOMAX(0x3ff) |
> YOMIN(0x1));
> -}
> -
> -int stf_isp_reset(struct stf_isp_dev *isp_dev)
> -{
> - stf_isp_reg_set_bit(isp_dev->stfcamss, ISP_REG_ISP_CTRL_0,
> - ISPC_RST_MASK, ISPC_RST);
> - stf_isp_reg_set_bit(isp_dev->stfcamss, ISP_REG_ISP_CTRL_0,
> - ISPC_RST_MASK, 0);
> -
> - return 0;
> -}
> -
> -void stf_isp_init_cfg(struct stf_isp_dev *isp_dev)
> -{
> - stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_DC_CFG_1,
> DC_AXI_ID(0x0));
> - stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_DEC_CFG,
> - DEC_V_KEEP(0x0) |
> - DEC_V_PERIOD(0x0) |
> - DEC_H_KEEP(0x0) |
> - DEC_H_PERIOD(0x0));
> -
> - stf_isp_config_obc(isp_dev->stfcamss);
> - stf_isp_config_oecf(isp_dev->stfcamss);
> - stf_isp_config_lccf(isp_dev->stfcamss);
> - stf_isp_config_awb(isp_dev->stfcamss);
> - stf_isp_config_grgb(isp_dev->stfcamss);
> - stf_isp_config_cfa(isp_dev->stfcamss);
> - stf_isp_config_ccm(isp_dev->stfcamss);
> - stf_isp_config_gamma(isp_dev->stfcamss);
> - stf_isp_config_r2y(isp_dev->stfcamss);
> - stf_isp_config_y_curve(isp_dev->stfcamss);
> - stf_isp_config_sharpen(isp_dev->stfcamss);
> - stf_isp_config_dnyuv(isp_dev->stfcamss);
> - stf_isp_config_sat(isp_dev->stfcamss);
> -
> - stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_CSI_MODULE_CFG,
> - CSI_DUMP_EN | CSI_SC_EN | CSI_AWB_EN |
> - CSI_LCCF_EN | CSI_OECF_EN | CSI_OBC_EN |
> CSI_DEC_EN);
> - stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_ISP_CTRL_1,
> - CTRL_SAT(1) | CTRL_DBC | CTRL_CTC | CTRL_YHIST |
> - CTRL_YCURVE | CTRL_BIYUV | CTRL_SCE | CTRL_EE |
> - CTRL_CCE | CTRL_RGE | CTRL_CME | CTRL_AE | CTRL_CE);
> -}
> -
> -static void stf_isp_config_crop(struct stfcamss *stfcamss,
> - struct v4l2_rect *crop)
> -{
> - u32 bpp = stfcamss->isp_dev.current_fmt->bpp;
> - u32 val;
> -
> - val = VSTART_CAP(crop->top) | HSTART_CAP(crop->left);
> - stf_isp_reg_write(stfcamss, ISP_REG_PIC_CAPTURE_START_CFG, val);
> -
> - val = VEND_CAP(crop->height + crop->top - 1) |
> - HEND_CAP(crop->width + crop->left - 1);
> - stf_isp_reg_write(stfcamss, ISP_REG_PIC_CAPTURE_END_CFG, val);
> -
> - val = H_ACT_CAP(crop->height) | W_ACT_CAP(crop->width);
> - stf_isp_reg_write(stfcamss, ISP_REG_PIPELINE_XY_SIZE, val);
> -
> - val = ALIGN(crop->width * bpp / 8,
> STFCAMSS_FRAME_WIDTH_ALIGN_8);
> - stf_isp_reg_write(stfcamss, ISP_REG_STRIDE, val);
> -}
> -
> -static void stf_isp_config_raw_fmt(struct stfcamss *stfcamss, u32 mcode)
> -{
> - u32 val, val1;
> -
> - switch (mcode) {
> - case MEDIA_BUS_FMT_SRGGB10_1X10:
> - case MEDIA_BUS_FMT_SRGGB8_1X8:
> - /* 3 2 3 2 1 0 1 0 B Gb B Gb Gr R Gr R */
> - val = SMY13(3) | SMY12(2) | SMY11(3) | SMY10(2) |
> - SMY3(1) | SMY2(0) | SMY1(1) | SMY0(0);
> - val1 = CTRL_SAT(0x0);
> - break;
> - case MEDIA_BUS_FMT_SGRBG10_1X10:
> - case MEDIA_BUS_FMT_SGRBG8_1X8:
> - /* 2 3 2 3 0 1 0 1, Gb B Gb B R Gr R Gr */
> - val = SMY13(2) | SMY12(3) | SMY11(2) | SMY10(3) |
> - SMY3(0) | SMY2(1) | SMY1(0) | SMY0(1);
> - val1 = CTRL_SAT(0x2);
> - break;
> - case MEDIA_BUS_FMT_SGBRG10_1X10:
> - case MEDIA_BUS_FMT_SGBRG8_1X8:
> - /* 1 0 1 0 3 2 3 2, Gr R Gr R B Gb B Gb */
> - val = SMY13(1) | SMY12(0) | SMY11(1) | SMY10(0) |
> - SMY3(3) | SMY2(2) | SMY1(3) | SMY0(2);
> - val1 = CTRL_SAT(0x3);
> - break;
> - case MEDIA_BUS_FMT_SBGGR10_1X10:
> - case MEDIA_BUS_FMT_SBGGR8_1X8:
> - /* 0 1 0 1 2 3 2 3 R Gr R Gr Gb B Gb B */
> - val = SMY13(0) | SMY12(1) | SMY11(0) | SMY10(1) |
> - SMY3(2) | SMY2(3) | SMY1(2) | SMY0(3);
> - val1 = CTRL_SAT(0x1);
> - break;
> - default:
> - val = SMY13(0) | SMY12(1) | SMY11(0) | SMY10(1) |
> - SMY3(2) | SMY2(3) | SMY1(2) | SMY0(3);
> - val1 = CTRL_SAT(0x1);
> - break;
> - }
> - stf_isp_reg_write(stfcamss, ISP_REG_RAW_FORMAT_CFG, val);
> - stf_isp_reg_set_bit(stfcamss, ISP_REG_ISP_CTRL_1, CTRL_SAT_MASK,
> val1);
> -}
> -
> -void stf_isp_settings(struct stf_isp_dev *isp_dev,
> - struct v4l2_rect *crop, u32 mcode)
> -{
> - struct stfcamss *stfcamss = isp_dev->stfcamss;
> -
> - stf_isp_config_crop(stfcamss, crop);
> - stf_isp_config_raw_fmt(stfcamss, mcode);
> -
> - stf_isp_reg_set_bit(stfcamss, ISP_REG_DUMP_CFG_1,
> - DUMP_BURST_LEN_MASK | DUMP_SD_MASK,
> - DUMP_BURST_LEN(3));
> -
> - stf_isp_reg_write(stfcamss, ISP_REG_ITIIWSR,
> - ITI_HSIZE(IMAGE_MAX_HEIGH) |
> - ITI_WSIZE(IMAGE_MAX_WIDTH));
> - stf_isp_reg_write(stfcamss, ISP_REG_ITIDWLSR, 0x960);
> - stf_isp_reg_write(stfcamss, ISP_REG_ITIDRLSR, 0x960);
> - stf_isp_reg_write(stfcamss, ISP_REG_SENSOR, IMAGER_SEL(1));
> -}
> -
> -void stf_isp_stream_set(struct stf_isp_dev *isp_dev)
> -{
> - struct stfcamss *stfcamss = isp_dev->stfcamss;
> -
> - stf_isp_reg_write_delay(stfcamss, ISP_REG_ISP_CTRL_0,
> - ISPC_ENUO | ISPC_ENLS | ISPC_RST, 10);
> - stf_isp_reg_write_delay(stfcamss, ISP_REG_ISP_CTRL_0,
> - ISPC_ENUO | ISPC_ENLS, 10);
> - stf_isp_reg_write(stfcamss, ISP_REG_IESHD, SHAD_UP_M);
> - stf_isp_reg_write_delay(stfcamss, ISP_REG_ISP_CTRL_0,
> - ISPC_ENUO | ISPC_ENLS | ISPC_EN, 10);
> - stf_isp_reg_write_delay(stfcamss, ISP_REG_CSIINTS,
> - CSI_INTS(1) | CSI_SHA_M(4), 10);
> - stf_isp_reg_write_delay(stfcamss, ISP_REG_CSIINTS,
> - CSI_INTS(2) | CSI_SHA_M(4), 10);
> - stf_isp_reg_write_delay(stfcamss,
> ISP_REG_CSI_INPUT_EN_AND_STATUS,
> - CSI_EN_S, 10);
> -}
> diff --git a/drivers/staging/media/starfive/camss/stf-isp.c
> b/drivers/staging/media/starfive/camss/stf-isp.c
> deleted file mode 100644
> index
> df7a903fbb1b0a8d88fcd2224a2b0ee8304fefe4..00000000000000000000000
> 00000000000000000
> --- a/drivers/staging/media/starfive/camss/stf-isp.c
> +++ /dev/null
> @@ -1,379 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * stf_isp.c
> - *
> - * StarFive Camera Subsystem - ISP Module
> - *
> - * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
> - */
> -#include <media/v4l2-rect.h>
> -
> -#include "stf-camss.h"
> -
> -static int isp_set_selection(struct v4l2_subdev *sd,
> - struct v4l2_subdev_state *state,
> - struct v4l2_subdev_selection *sel);
> -
> -static const struct stf_isp_format isp_formats_sink[] = {
> - { MEDIA_BUS_FMT_SRGGB10_1X10, 10 },
> - { MEDIA_BUS_FMT_SGRBG10_1X10, 10 },
> - { MEDIA_BUS_FMT_SGBRG10_1X10, 10 },
> - { MEDIA_BUS_FMT_SBGGR10_1X10, 10 },
> -};
> -
> -static const struct stf_isp_format isp_formats_source[] = {
> - { MEDIA_BUS_FMT_YUYV8_1_5X8, 8 },
> -};
> -
> -static const struct stf_isp_format_table isp_formats_st7110[] = {
> - { isp_formats_sink, ARRAY_SIZE(isp_formats_sink) },
> - { isp_formats_source, ARRAY_SIZE(isp_formats_source) },
> -};
> -
> -static const struct stf_isp_format *
> -stf_g_fmt_by_mcode(const struct stf_isp_format_table *fmt_table, u32
> mcode)
> -{
> - unsigned int i;
> -
> - for (i = 0; i < fmt_table->nfmts; i++) {
> - if (fmt_table->fmts[i].code == mcode)
> - return &fmt_table->fmts[i];
> - }
> -
> - return NULL;
> -}
> -
> -int stf_isp_init(struct stfcamss *stfcamss)
> -{
> - struct stf_isp_dev *isp_dev = &stfcamss->isp_dev;
> -
> - isp_dev->stfcamss = stfcamss;
> - isp_dev->formats = isp_formats_st7110;
> - isp_dev->nformats = ARRAY_SIZE(isp_formats_st7110);
> - isp_dev->current_fmt = &isp_formats_source[0];
> -
> - return 0;
> -}
> -
> -static int isp_set_stream(struct v4l2_subdev *sd, int enable)
> -{
> - struct stf_isp_dev *isp_dev = v4l2_get_subdevdata(sd);
> - struct v4l2_subdev_state *sd_state;
> - struct v4l2_mbus_framefmt *fmt;
> - struct v4l2_rect *crop;
> -
> - sd_state = v4l2_subdev_lock_and_get_active_state(sd);
> - fmt = v4l2_subdev_state_get_format(sd_state, STF_ISP_PAD_SINK);
> - crop = v4l2_subdev_state_get_crop(sd_state, STF_ISP_PAD_SRC);
> -
> - if (enable) {
> - stf_isp_reset(isp_dev);
> - stf_isp_init_cfg(isp_dev);
> - stf_isp_settings(isp_dev, crop, fmt->code);
> - stf_isp_stream_set(isp_dev);
> - }
> -
> - v4l2_subdev_call(isp_dev->source_subdev, video, s_stream, enable);
> -
> - v4l2_subdev_unlock_state(sd_state);
> - return 0;
> -}
> -
> -static void isp_try_format(struct stf_isp_dev *isp_dev,
> - struct v4l2_subdev_state *state,
> - unsigned int pad,
> - struct v4l2_mbus_framefmt *fmt)
> -{
> - const struct stf_isp_format_table *formats;
> -
> - if (pad >= STF_ISP_PAD_MAX) {
> - fmt->colorspace = V4L2_COLORSPACE_SRGB;
> - return;
> - }
> -
> - formats = &isp_dev->formats[pad];
> -
> - fmt->width = clamp_t(u32, fmt->width,
> STFCAMSS_FRAME_MIN_WIDTH,
> - STFCAMSS_FRAME_MAX_WIDTH);
> - fmt->height = clamp_t(u32, fmt->height,
> STFCAMSS_FRAME_MIN_HEIGHT,
> - STFCAMSS_FRAME_MAX_HEIGHT);
> - fmt->height &= ~0x1;
> - fmt->field = V4L2_FIELD_NONE;
> - fmt->colorspace = V4L2_COLORSPACE_SRGB;
> - fmt->flags = 0;
> -
> - if (!stf_g_fmt_by_mcode(formats, fmt->code))
> - fmt->code = formats->fmts[0].code;
> -}
> -
> -static int isp_enum_mbus_code(struct v4l2_subdev *sd,
> - struct v4l2_subdev_state *state,
> - struct v4l2_subdev_mbus_code_enum *code)
> -{
> - struct stf_isp_dev *isp_dev = v4l2_get_subdevdata(sd);
> - const struct stf_isp_format_table *formats;
> -
> - if (code->pad == STF_ISP_PAD_SINK) {
> - if (code->index >= ARRAY_SIZE(isp_formats_sink))
> - return -EINVAL;
> -
> - formats = &isp_dev->formats[code->pad];
> - code->code = formats->fmts[code->index].code;
> - } else {
> - struct v4l2_mbus_framefmt *sink_fmt;
> -
> - if (code->index >= ARRAY_SIZE(isp_formats_source))
> - return -EINVAL;
> -
> - sink_fmt = v4l2_subdev_state_get_format(state,
> - STF_ISP_PAD_SRC);
> -
> - code->code = sink_fmt->code;
> - if (!code->code)
> - return -EINVAL;
> - }
> - code->flags = 0;
> -
> - return 0;
> -}
> -
> -static int isp_set_format(struct v4l2_subdev *sd,
> - struct v4l2_subdev_state *state,
> - struct v4l2_subdev_format *fmt)
> -{
> - struct stf_isp_dev *isp_dev = v4l2_get_subdevdata(sd);
> - struct v4l2_mbus_framefmt *format;
> -
> - format = v4l2_subdev_state_get_format(state, fmt->pad);
> - if (!format)
> - return -EINVAL;
> -
> - isp_try_format(isp_dev, state, fmt->pad, &fmt->format);
> - *format = fmt->format;
> -
> - isp_dev->current_fmt =
> stf_g_fmt_by_mcode(&isp_dev->formats[fmt->pad],
> - fmt->format.code);
> -
> - /* Propagate to in crop */
> - if (fmt->pad == STF_ISP_PAD_SINK) {
> - struct v4l2_subdev_selection sel = { 0 };
> -
> - /* Reset sink pad compose selection */
> - sel.which = fmt->which;
> - sel.pad = STF_ISP_PAD_SINK;
> - sel.target = V4L2_SEL_TGT_CROP;
> - sel.r.width = fmt->format.width;
> - sel.r.height = fmt->format.height;
> - isp_set_selection(sd, state, &sel);
> - }
> -
> - return 0;
> -}
> -
> -static const struct v4l2_rect stf_frame_min_crop = {
> - .width = STFCAMSS_FRAME_MIN_WIDTH,
> - .height = STFCAMSS_FRAME_MIN_HEIGHT,
> - .top = 0,
> - .left = 0,
> -};
> -
> -static void isp_try_crop(struct stf_isp_dev *isp_dev,
> - struct v4l2_subdev_state *state,
> - struct v4l2_rect *crop)
> -{
> - struct v4l2_mbus_framefmt *fmt =
> - v4l2_subdev_state_get_format(state, STF_ISP_PAD_SINK);
> -
> - const struct v4l2_rect bounds = {
> - .width = fmt->width,
> - .height = fmt->height,
> - .left = 0,
> - .top = 0,
> - };
> -
> - v4l2_rect_set_min_size(crop, &stf_frame_min_crop);
> - v4l2_rect_map_inside(crop, &bounds);
> -}
> -
> -static int isp_get_selection(struct v4l2_subdev *sd,
> - struct v4l2_subdev_state *state,
> - struct v4l2_subdev_selection *sel)
> -{
> - struct v4l2_subdev_format fmt = { 0 };
> - struct v4l2_rect *rect;
> -
> - switch (sel->target) {
> - case V4L2_SEL_TGT_CROP_BOUNDS:
> - if (sel->pad == STF_ISP_PAD_SINK) {
> - fmt.format = *v4l2_subdev_state_get_format(state,
> - sel->pad);
> - sel->r.left = 0;
> - sel->r.top = 0;
> - sel->r.width = fmt.format.width;
> - sel->r.height = fmt.format.height;
> - } else if (sel->pad == STF_ISP_PAD_SRC) {
> - rect = v4l2_subdev_state_get_crop(state, sel->pad);
> - sel->r = *rect;
> - }
> - break;
> -
> - case V4L2_SEL_TGT_CROP:
> - rect = v4l2_subdev_state_get_crop(state, sel->pad);
> - if (!rect)
> - return -EINVAL;
> -
> - sel->r = *rect;
> - break;
> -
> - default:
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -
> -static int isp_set_selection(struct v4l2_subdev *sd,
> - struct v4l2_subdev_state *state,
> - struct v4l2_subdev_selection *sel)
> -{
> - struct stf_isp_dev *isp_dev = v4l2_get_subdevdata(sd);
> - struct v4l2_rect *rect;
> -
> - if (sel->target != V4L2_SEL_TGT_CROP)
> - return -EINVAL;
> -
> - if (sel->target == V4L2_SEL_TGT_CROP &&
> - sel->pad == STF_ISP_PAD_SINK) {
> - struct v4l2_subdev_selection crop = { 0 };
> -
> - rect = v4l2_subdev_state_get_crop(state, sel->pad);
> - if (!rect)
> - return -EINVAL;
> -
> - isp_try_crop(isp_dev, state, &sel->r);
> - *rect = sel->r;
> -
> - /* Reset source crop selection */
> - crop.which = sel->which;
> - crop.pad = STF_ISP_PAD_SRC;
> - crop.target = V4L2_SEL_TGT_CROP;
> - crop.r = *rect;
> - isp_set_selection(sd, state, &crop);
> - } else if (sel->target == V4L2_SEL_TGT_CROP &&
> - sel->pad == STF_ISP_PAD_SRC) {
> - struct v4l2_subdev_format fmt = { 0 };
> -
> - rect = v4l2_subdev_state_get_crop(state, sel->pad);
> - if (!rect)
> - return -EINVAL;
> -
> - isp_try_crop(isp_dev, state, &sel->r);
> - *rect = sel->r;
> -
> - /* Reset source pad format width and height */
> - fmt.which = sel->which;
> - fmt.pad = STF_ISP_PAD_SRC;
> - fmt.format.width = rect->width;
> - fmt.format.height = rect->height;
> - isp_set_format(sd, state, &fmt);
> - }
> -
> - dev_dbg(isp_dev->stfcamss->dev, "pad: %d sel(%d,%d)/%ux%u\n",
> - sel->pad, sel->r.left, sel->r.top, sel->r.width, sel->r.height);
> -
> - return 0;
> -}
> -
> -static int isp_init_formats(struct v4l2_subdev *sd,
> - struct v4l2_subdev_state *sd_state)
> -{
> - struct v4l2_subdev_format format = {
> - .pad = STF_ISP_PAD_SINK,
> - .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> - .format = {
> - .code = MEDIA_BUS_FMT_SRGGB10_1X10,
> - .width = 1920,
> - .height = 1080
> - }
> - };
> -
> - return isp_set_format(sd, sd_state, &format);
> -}
> -
> -static const struct v4l2_subdev_video_ops isp_video_ops = {
> - .s_stream = isp_set_stream,
> -};
> -
> -static const struct v4l2_subdev_pad_ops isp_pad_ops = {
> - .enum_mbus_code = isp_enum_mbus_code,
> - .get_fmt = v4l2_subdev_get_fmt,
> - .set_fmt = isp_set_format,
> - .get_selection = isp_get_selection,
> - .set_selection = isp_set_selection,
> -};
> -
> -static const struct v4l2_subdev_ops isp_v4l2_ops = {
> - .video = &isp_video_ops,
> - .pad = &isp_pad_ops,
> -};
> -
> -static const struct v4l2_subdev_internal_ops isp_internal_ops = {
> - .init_state = isp_init_formats,
> -};
> -
> -static const struct media_entity_operations isp_media_ops = {
> - .link_validate = v4l2_subdev_link_validate,
> -};
> -
> -int stf_isp_register(struct stf_isp_dev *isp_dev, struct v4l2_device
> *v4l2_dev)
> -{
> - struct v4l2_subdev *sd = &isp_dev->subdev;
> - struct media_pad *pads = isp_dev->pads;
> - int ret;
> -
> - v4l2_subdev_init(sd, &isp_v4l2_ops);
> - sd->internal_ops = &isp_internal_ops;
> - sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
> - snprintf(sd->name, ARRAY_SIZE(sd->name), "stf_isp");
> - v4l2_set_subdevdata(sd, isp_dev);
> -
> - pads[STF_ISP_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
> - pads[STF_ISP_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
> -
> - sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_ISP;
> - sd->entity.ops = &isp_media_ops;
> - ret = media_entity_pads_init(&sd->entity, STF_ISP_PAD_MAX, pads);
> - if (ret) {
> - dev_err(isp_dev->stfcamss->dev,
> - "Failed to init media entity: %d\n", ret);
> - return ret;
> - }
> -
> - ret = v4l2_subdev_init_finalize(sd);
> - if (ret)
> - goto err_entity_cleanup;
> -
> - ret = v4l2_device_register_subdev(v4l2_dev, sd);
> - if (ret) {
> - dev_err(isp_dev->stfcamss->dev,
> - "Failed to register subdev: %d\n", ret);
> - goto err_subdev_cleanup;
> - }
> -
> - return 0;
> -
> -err_subdev_cleanup:
> - v4l2_subdev_cleanup(sd);
> -err_entity_cleanup:
> - media_entity_cleanup(&sd->entity);
> - return ret;
> -}
> -
> -int stf_isp_unregister(struct stf_isp_dev *isp_dev)
> -{
> - v4l2_device_unregister_subdev(&isp_dev->subdev);
> - v4l2_subdev_cleanup(&isp_dev->subdev);
> - media_entity_cleanup(&isp_dev->subdev.entity);
> -
> - return 0;
> -}
> diff --git a/drivers/staging/media/starfive/camss/stf-isp.h
> b/drivers/staging/media/starfive/camss/stf-isp.h
> deleted file mode 100644
> index
> 955cbb048363793912a737ac048fa34fc3ff93cd..00000000000000000000000
> 00000000000000000
> --- a/drivers/staging/media/starfive/camss/stf-isp.h
> +++ /dev/null
> @@ -1,428 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * stf_isp.h
> - *
> - * StarFive Camera Subsystem - ISP Module
> - *
> - * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
> - */
> -
> -#ifndef STF_ISP_H
> -#define STF_ISP_H
> -
> -#include <media/v4l2-subdev.h>
> -
> -#include "stf-video.h"
> -
> -#define ISP_RAW_DATA_BITS 12
> -#define SCALER_RATIO_MAX 1
> -#define STF_ISP_REG_OFFSET_MAX 0x0fff
> -#define STF_ISP_REG_DELAY_MAX 100
> -
> -/* isp registers */
> -#define ISP_REG_CSI_INPUT_EN_AND_STATUS 0x000
> -#define CSI_SCD_ERR BIT(6)
> -#define CSI_ITU656_ERR BIT(4)
> -#define CSI_ITU656_F BIT(3)
> -#define CSI_SCD_DONE BIT(2)
> -#define CSI_BUSY_S BIT(1)
> -#define CSI_EN_S BIT(0)
> -
> -#define ISP_REG_CSIINTS 0x008
> -#define CSI_INTS(n) ((n) << 16)
> -#define CSI_SHA_M(n) ((n) << 0)
> -#define CSI_INTS_MASK GENMASK(17, 16)
> -
> -#define ISP_REG_CSI_MODULE_CFG 0x010
> -#define CSI_DUMP_EN BIT(19)
> -#define CSI_VS_EN BIT(18)
> -#define CSI_SC_EN BIT(17)
> -#define CSI_OBA_EN BIT(16)
> -#define CSI_AWB_EN BIT(7)
> -#define CSI_LCCF_EN BIT(6)
> -#define CSI_OECFHM_EN BIT(5)
> -#define CSI_OECF_EN BIT(4)
> -#define CSI_LCBQ_EN BIT(3)
> -#define CSI_OBC_EN BIT(2)
> -#define CSI_DEC_EN BIT(1)
> -#define CSI_DC_EN BIT(0)
> -
> -#define ISP_REG_SENSOR 0x014
> -#define DVP_SYNC_POL(n) ((n) << 2)
> -#define ITU656_EN(n) ((n) << 1)
> -#define IMAGER_SEL(n) ((n) << 0)
> -
> -#define ISP_REG_RAW_FORMAT_CFG 0x018
> -#define SMY13(n) ((n) << 14)
> -#define SMY12(n) ((n) << 12)
> -#define SMY11(n) ((n) << 10)
> -#define SMY10(n) ((n) << 8)
> -#define SMY3(n) ((n) << 6)
> -#define SMY2(n) ((n) << 4)
> -#define SMY1(n) ((n) << 2)
> -#define SMY0(n) ((n) << 0)
> -
> -#define ISP_REG_PIC_CAPTURE_START_CFG 0x01c
> -#define VSTART_CAP(n) ((n) << 16)
> -#define HSTART_CAP(n) ((n) << 0)
> -
> -#define ISP_REG_PIC_CAPTURE_END_CFG 0x020
> -#define VEND_CAP(n) ((n) << 16)
> -#define HEND_CAP(n) ((n) << 0)
> -
> -#define ISP_REG_DUMP_CFG_0 0x024
> -#define ISP_REG_DUMP_CFG_1 0x028
> -#define DUMP_ID(n) ((n) << 24)
> -#define DUMP_SHT(n) ((n) << 20)
> -#define DUMP_BURST_LEN(n) ((n) << 16)
> -#define DUMP_SD(n) ((n) << 0)
> -#define DUMP_BURST_LEN_MASK GENMASK(17, 16)
> -#define DUMP_SD_MASK GENMASK(15, 0)
> -
> -#define ISP_REG_DEC_CFG 0x030
> -#define DEC_V_KEEP(n) ((n) << 24)
> -#define DEC_V_PERIOD(n) ((n) << 16)
> -#define DEC_H_KEEP(n) ((n) << 8)
> -#define DEC_H_PERIOD(n) ((n) << 0)
> -
> -#define ISP_REG_OBC_CFG 0x034
> -#define OBC_W_H(y) ((y) << 4)
> -#define OBC_W_W(x) ((x) << 0)
> -
> -#define ISP_REG_DC_CFG_1 0x044
> -#define DC_AXI_ID(n) ((n) << 0)
> -
> -#define ISP_REG_LCCF_CFG_0 0x050
> -#define Y_DISTANCE(y) ((y) << 16)
> -#define X_DISTANCE(x) ((x) << 0)
> -
> -#define ISP_REG_LCCF_CFG_1 0x058
> -#define LCCF_MAX_DIS(n) ((n) << 0)
> -
> -#define ISP_REG_LCBQ_CFG_0 0x074
> -#define H_LCBQ(y) ((y) << 12)
> -#define W_LCBQ(x) ((x) << 8)
> -
> -#define ISP_REG_LCBQ_CFG_1 0x07c
> -#define Y_COOR(y) ((y) << 16)
> -#define X_COOR(x) ((x) << 0)
> -
> -#define ISP_REG_LCCF_CFG_2 0x0e0
> -#define ISP_REG_LCCF_CFG_3 0x0e4
> -#define ISP_REG_LCCF_CFG_4 0x0e8
> -#define ISP_REG_LCCF_CFG_5 0x0ec
> -#define LCCF_F2_PAR(n) ((n) << 16)
> -#define LCCF_F1_PAR(n) ((n) << 0)
> -
> -#define ISP_REG_OECF_X0_CFG0 0x100
> -#define ISP_REG_OECF_X0_CFG1 0x104
> -#define ISP_REG_OECF_X0_CFG2 0x108
> -#define ISP_REG_OECF_X0_CFG3 0x10c
> -#define ISP_REG_OECF_X0_CFG4 0x110
> -#define ISP_REG_OECF_X0_CFG5 0x114
> -#define ISP_REG_OECF_X0_CFG6 0x118
> -#define ISP_REG_OECF_X0_CFG7 0x11c
> -
> -#define ISP_REG_OECF_Y3_CFG0 0x1e0
> -#define ISP_REG_OECF_Y3_CFG1 0x1e4
> -#define ISP_REG_OECF_Y3_CFG2 0x1e8
> -#define ISP_REG_OECF_Y3_CFG3 0x1ec
> -#define ISP_REG_OECF_Y3_CFG4 0x1f0
> -#define ISP_REG_OECF_Y3_CFG5 0x1f4
> -#define ISP_REG_OECF_Y3_CFG6 0x1f8
> -#define ISP_REG_OECF_Y3_CFG7 0x1fc
> -
> -#define ISP_REG_OECF_S0_CFG0 0x200
> -#define ISP_REG_OECF_S3_CFG7 0x27c
> -#define OCEF_PAR_H(n) ((n) << 16)
> -#define OCEF_PAR_L(n) ((n) << 0)
> -
> -#define ISP_REG_AWB_X0_CFG_0 0x280
> -#define ISP_REG_AWB_X0_CFG_1 0x284
> -#define ISP_REG_AWB_X1_CFG_0 0x288
> -#define ISP_REG_AWB_X1_CFG_1 0x28c
> -#define ISP_REG_AWB_X2_CFG_0 0x290
> -#define ISP_REG_AWB_X2_CFG_1 0x294
> -#define ISP_REG_AWB_X3_CFG_0 0x298
> -#define ISP_REG_AWB_X3_CFG_1 0x29c
> -#define AWB_X_SYMBOL_H(n) ((n) << 16)
> -#define AWB_X_SYMBOL_L(n) ((n) << 0)
> -
> -#define ISP_REG_AWB_Y0_CFG_0 0x2a0
> -#define ISP_REG_AWB_Y0_CFG_1 0x2a4
> -#define ISP_REG_AWB_Y1_CFG_0 0x2a8
> -#define ISP_REG_AWB_Y1_CFG_1 0x2ac
> -#define ISP_REG_AWB_Y2_CFG_0 0x2b0
> -#define ISP_REG_AWB_Y2_CFG_1 0x2b4
> -#define ISP_REG_AWB_Y3_CFG_0 0x2b8
> -#define ISP_REG_AWB_Y3_CFG_1 0x2bc
> -#define AWB_Y_SYMBOL_H(n) ((n) << 16)
> -#define AWB_Y_SYMBOL_L(n) ((n) << 0)
> -
> -#define ISP_REG_AWB_S0_CFG_0 0x2c0
> -#define ISP_REG_AWB_S0_CFG_1 0x2c4
> -#define ISP_REG_AWB_S1_CFG_0 0x2c8
> -#define ISP_REG_AWB_S1_CFG_1 0x2cc
> -#define ISP_REG_AWB_S2_CFG_0 0x2d0
> -#define ISP_REG_AWB_S2_CFG_1 0x2d4
> -#define ISP_REG_AWB_S3_CFG_0 0x2d8
> -#define ISP_REG_AWB_S3_CFG_1 0x2dc
> -#define AWB_S_SYMBOL_H(n) ((n) << 16)
> -#define AWB_S_SYMBOL_L(n) ((n) << 0)
> -
> -#define ISP_REG_OBCG_CFG_0 0x2e0
> -#define ISP_REG_OBCG_CFG_1 0x2e4
> -#define ISP_REG_OBCG_CFG_2 0x2e8
> -#define ISP_REG_OBCG_CFG_3 0x2ec
> -#define ISP_REG_OBCO_CFG_0 0x2f0
> -#define ISP_REG_OBCO_CFG_1 0x2f4
> -#define ISP_REG_OBCO_CFG_2 0x2f8
> -#define ISP_REG_OBCO_CFG_3 0x2fc
> -#define GAIN_D_POINT(x) ((x) << 24)
> -#define GAIN_C_POINT(x) ((x) << 16)
> -#define GAIN_B_POINT(x) ((x) << 8)
> -#define GAIN_A_POINT(x) ((x) << 0)
> -#define OFFSET_D_POINT(x) ((x) << 24)
> -#define OFFSET_C_POINT(x) ((x) << 16)
> -#define OFFSET_B_POINT(x) ((x) << 8)
> -#define OFFSET_A_POINT(x) ((x) << 0)
> -
> -#define ISP_REG_ISP_CTRL_0 0xa00
> -#define ISPC_LINE BIT(27)
> -#define ISPC_SC BIT(26)
> -#define ISPC_CSI BIT(25)
> -#define ISPC_ISP BIT(24)
> -#define ISPC_ENUO BIT(20)
> -#define ISPC_ENLS BIT(17)
> -#define ISPC_ENSS1 BIT(12)
> -#define ISPC_ENSS0 BIT(11)
> -#define ISPC_RST BIT(1)
> -#define ISPC_EN BIT(0)
> -#define ISPC_RST_MASK BIT(1)
> -#define ISPC_INT_ALL_MASK GENMASK(27, 24)
> -
> -#define ISP_REG_ISP_CTRL_1 0xa08
> -#define CTRL_SAT(n) ((n) << 28)
> -#define CTRL_DBC BIT(22)
> -#define CTRL_CTC BIT(21)
> -#define CTRL_YHIST BIT(20)
> -#define CTRL_YCURVE BIT(19)
> -#define CTRL_CTM BIT(18)
> -#define CTRL_BIYUV BIT(17)
> -#define CTRL_SCE BIT(8)
> -#define CTRL_EE BIT(7)
> -#define CTRL_CCE BIT(5)
> -#define CTRL_RGE BIT(4)
> -#define CTRL_CME BIT(3)
> -#define CTRL_AE BIT(2)
> -#define CTRL_CE BIT(1)
> -#define CTRL_SAT_MASK GENMASK(31, 28)
> -
> -#define ISP_REG_PIPELINE_XY_SIZE 0xa0c
> -#define H_ACT_CAP(n) ((n) << 16)
> -#define W_ACT_CAP(n) ((n) << 0)
> -
> -#define ISP_REG_ICTC 0xa10
> -#define GF_MODE(n) ((n) << 30)
> -#define MAXGT(n) ((n) << 16)
> -#define MINGT(n) ((n) << 0)
> -
> -#define ISP_REG_IDBC 0xa14
> -#define BADGT(n) ((n) << 16)
> -#define BADXT(n) ((n) << 0)
> -
> -#define ISP_REG_ICFAM 0xa1c
> -#define CROSS_COV(n) ((n) << 4)
> -#define HV_W(n) ((n) << 0)
> -
> -#define ISP_REG_CS_GAIN 0xa30
> -#define CMAD(n) ((n) << 16)
> -#define CMAB(n) ((n) << 0)
> -
> -#define ISP_REG_CS_THRESHOLD 0xa34
> -#define CMD(n) ((n) << 16)
> -#define CMB(n) ((n) << 0)
> -
> -#define ISP_REG_CS_OFFSET 0xa38
> -#define VOFF(n) ((n) << 16)
> -#define UOFF(n) ((n) << 0)
> -
> -#define ISP_REG_CS_HUE_F 0xa3c
> -#define SIN(n) ((n) << 16)
> -#define COS(n) ((n) << 0)
> -
> -#define ISP_REG_CS_SCALE 0xa40
> -
> -#define ISP_REG_IESHD 0xa50
> -#define SHAD_UP_M BIT(1)
> -#define SHAD_UP_EN BIT(0)
> -
> -#define ISP_REG_YADJ0 0xa54
> -#define YOIR(n) ((n) << 16)
> -#define YIMIN(n) ((n) << 0)
> -
> -#define ISP_REG_YADJ1 0xa58
> -#define YOMAX(n) ((n) << 16)
> -#define YOMIN(n) ((n) << 0)
> -
> -#define ISP_REG_Y_PLANE_START_ADDR 0xa80
> -#define ISP_REG_UV_PLANE_START_ADDR 0xa84
> -#define ISP_REG_STRIDE 0xa88
> -
> -#define ISP_REG_ITIIWSR 0xb20
> -#define ITI_HSIZE(n) ((n) << 16)
> -#define ITI_WSIZE(n) ((n) << 0)
> -
> -#define ISP_REG_ITIDWLSR 0xb24
> -#define ISP_REG_ITIPDFR 0xb38
> -#define ISP_REG_ITIDRLSR 0xb3C
> -
> -#define ISP_REG_DNYUV_YSWR0 0xc00
> -#define ISP_REG_DNYUV_YSWR1 0xc04
> -#define ISP_REG_DNYUV_CSWR0 0xc08
> -#define ISP_REG_DNYUV_CSWR1 0xc0c
> -#define YUVSW5(n) ((n) << 20)
> -#define YUVSW4(n) ((n) << 16)
> -#define YUVSW3(n) ((n) << 12)
> -#define YUVSW2(n) ((n) << 8)
> -#define YUVSW1(n) ((n) << 4)
> -#define YUVSW0(n) ((n) << 0)
> -
> -#define ISP_REG_DNYUV_YDR0 0xc10
> -#define ISP_REG_DNYUV_YDR1 0xc14
> -#define ISP_REG_DNYUV_YDR2 0xc18
> -#define ISP_REG_DNYUV_CDR0 0xc1c
> -#define ISP_REG_DNYUV_CDR1 0xc20
> -#define ISP_REG_DNYUV_CDR2 0xc24
> -#define CURVE_D_H(n) ((n) << 16)
> -#define CURVE_D_L(n) ((n) << 0)
> -
> -#define ISP_REG_ICAMD_0 0xc40
> -#define ISP_REG_ICAMD_12 0xc70
> -#define ISP_REG_ICAMD_20 0xc90
> -#define ISP_REG_ICAMD_24 0xca0
> -#define ISP_REG_ICAMD_25 0xca4
> -#define DNRM_F(n) ((n) << 16)
> -#define CCM_M_DAT(n) ((n) << 0)
> -
> -#define ISP_REG_GAMMA_VAL0 0xe00
> -#define ISP_REG_GAMMA_VAL1 0xe04
> -#define ISP_REG_GAMMA_VAL2 0xe08
> -#define ISP_REG_GAMMA_VAL3 0xe0c
> -#define ISP_REG_GAMMA_VAL4 0xe10
> -#define ISP_REG_GAMMA_VAL5 0xe14
> -#define ISP_REG_GAMMA_VAL6 0xe18
> -#define ISP_REG_GAMMA_VAL7 0xe1c
> -#define ISP_REG_GAMMA_VAL8 0xe20
> -#define ISP_REG_GAMMA_VAL9 0xe24
> -#define ISP_REG_GAMMA_VAL10 0xe28
> -#define ISP_REG_GAMMA_VAL11 0xe2c
> -#define ISP_REG_GAMMA_VAL12 0xe30
> -#define ISP_REG_GAMMA_VAL13 0xe34
> -#define ISP_REG_GAMMA_VAL14 0xe38
> -#define GAMMA_S_VAL(n) ((n) << 16)
> -#define GAMMA_VAL(n) ((n) << 0)
> -
> -#define ISP_REG_R2Y_0 0xe40
> -#define ISP_REG_R2Y_1 0xe44
> -#define ISP_REG_R2Y_2 0xe48
> -#define ISP_REG_R2Y_3 0xe4c
> -#define ISP_REG_R2Y_4 0xe50
> -#define ISP_REG_R2Y_5 0xe54
> -#define ISP_REG_R2Y_6 0xe58
> -#define ISP_REG_R2Y_7 0xe5c
> -#define ISP_REG_R2Y_8 0xe60
> -
> -#define ISP_REG_SHARPEN0 0xe80
> -#define ISP_REG_SHARPEN1 0xe84
> -#define ISP_REG_SHARPEN2 0xe88
> -#define ISP_REG_SHARPEN3 0xe8c
> -#define ISP_REG_SHARPEN4 0xe90
> -#define ISP_REG_SHARPEN5 0xe94
> -#define ISP_REG_SHARPEN6 0xe98
> -#define ISP_REG_SHARPEN7 0xe9c
> -#define ISP_REG_SHARPEN8 0xea0
> -#define ISP_REG_SHARPEN9 0xea4
> -#define ISP_REG_SHARPEN10 0xea8
> -#define ISP_REG_SHARPEN11 0xeac
> -#define ISP_REG_SHARPEN12 0xeb0
> -#define ISP_REG_SHARPEN13 0xeb4
> -#define ISP_REG_SHARPEN14 0xeb8
> -#define S_DELTA(n) ((n) << 16)
> -#define S_WEIGHT(n) ((n) << 8)
> -
> -#define ISP_REG_SHARPEN_FS0 0xebc
> -#define ISP_REG_SHARPEN_FS1 0xec0
> -#define ISP_REG_SHARPEN_FS2 0xec4
> -#define ISP_REG_SHARPEN_FS3 0xec8
> -#define ISP_REG_SHARPEN_FS4 0xecc
> -#define ISP_REG_SHARPEN_FS5 0xed0
> -#define S_FACTOR(n) ((n) << 24)
> -#define S_SLOPE(n) ((n) << 0)
> -
> -#define ISP_REG_SHARPEN_WN 0xed4
> -#define PDIRF(n) ((n) << 28)
> -#define NDIRF(n) ((n) << 24)
> -#define WSUM(n) ((n) << 0)
> -
> -#define ISP_REG_IUVS1 0xed8
> -#define UVDIFF2(n) ((n) << 16)
> -#define UVDIFF1(n) ((n) << 0)
> -
> -#define ISP_REG_IUVS2 0xedc
> -#define UVF(n) ((n) << 24)
> -#define UVSLOPE(n) ((n) << 0)
> -
> -#define ISP_REG_IUVCKS1 0xee0
> -#define UVCKDIFF2(n) ((n) << 16)
> -#define UVCKDIFF1(n) ((n) << 0)
> -
> -#define ISP_REG_IUVCKS2 0xee4
> -
> -#define ISP_REG_ISHRPET 0xee8
> -#define TH(n) ((n) << 8)
> -#define EN(n) ((n) << 0)
> -
> -#define ISP_REG_YCURVE_0 0xf00
> -#define ISP_REG_YCURVE_63 0xffc
> -
> -#define IMAGE_MAX_WIDTH 1920
> -#define IMAGE_MAX_HEIGH 1080
> -
> -/* pad id for media framework */
> -enum stf_isp_pad_id {
> - STF_ISP_PAD_SINK = 0,
> - STF_ISP_PAD_SRC,
> - STF_ISP_PAD_MAX
> -};
> -
> -struct stf_isp_format {
> - u32 code;
> - u8 bpp;
> -};
> -
> -struct stf_isp_format_table {
> - const struct stf_isp_format *fmts;
> - int nfmts;
> -};
> -
> -struct stf_isp_dev {
> - struct stfcamss *stfcamss;
> - struct v4l2_subdev subdev;
> - struct media_pad pads[STF_ISP_PAD_MAX];
> - const struct stf_isp_format_table *formats;
> - unsigned int nformats;
> - struct v4l2_subdev *source_subdev;
> - const struct stf_isp_format *current_fmt;
> -};
> -
> -int stf_isp_reset(struct stf_isp_dev *isp_dev);
> -void stf_isp_init_cfg(struct stf_isp_dev *isp_dev);
> -void stf_isp_settings(struct stf_isp_dev *isp_dev,
> - struct v4l2_rect *crop, u32 mcode);
> -void stf_isp_stream_set(struct stf_isp_dev *isp_dev);
> -int stf_isp_init(struct stfcamss *stfcamss);
> -int stf_isp_register(struct stf_isp_dev *isp_dev, struct v4l2_device
> *v4l2_dev);
> -int stf_isp_unregister(struct stf_isp_dev *isp_dev);
> -
> -#endif /* STF_ISP_H */
> diff --git a/drivers/staging/media/starfive/camss/stf-video.c
> b/drivers/staging/media/starfive/camss/stf-video.c
> deleted file mode 100644
> index
> a0420eb6a0aa034fb0b1468951d84c8fe7bb1b56..0000000000000000000000
> 000000000000000000
> --- a/drivers/staging/media/starfive/camss/stf-video.c
> +++ /dev/null
> @@ -1,570 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * stf_video.c
> - *
> - * StarFive Camera Subsystem - V4L2 device node
> - *
> - * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
> - */
> -
> -#include <linux/pm_runtime.h>
> -#include <media/v4l2-ctrls.h>
> -#include <media/v4l2-event.h>
> -#include <media/v4l2-mc.h>
> -#include <media/videobuf2-dma-contig.h>
> -
> -#include "stf-camss.h"
> -#include "stf-video.h"
> -
> -/* -----------------------------------------------------------------------------
> - * Helper functions
> - */
> -
> -static inline struct stfcamss_buffer *
> -to_stfcamss_buffer(struct vb2_v4l2_buffer *vbuf)
> -{
> - return container_of(vbuf, struct stfcamss_buffer, vb);
> -}
> -
> -static const struct stfcamss_format_info *
> -video_g_fi_by_index(struct stfcamss_video *video, int index)
> -{
> - if (index >= video->nformats)
> - return NULL;
> -
> - return &video->formats[index];
> -}
> -
> -static const struct stfcamss_format_info *
> -video_g_fi_by_mcode(struct stfcamss_video *video, u32 mcode)
> -{
> - unsigned int i;
> -
> - for (i = 0; i < video->nformats; i++) {
> - if (video->formats[i].code == mcode)
> - return &video->formats[i];
> - }
> -
> - return NULL;
> -}
> -
> -static const struct stfcamss_format_info *
> -video_g_fi_by_pfmt(struct stfcamss_video *video, u32 pixelformat)
> -{
> - unsigned int i;
> -
> - for (i = 0; i < video->nformats; i++) {
> - if (video->formats[i].pixelformat == pixelformat)
> - return &video->formats[i];
> - }
> -
> - return NULL;
> -}
> -
> -static int __video_try_fmt(struct stfcamss_video *video, struct v4l2_format
> *f)
> -{
> - struct v4l2_pix_format *pix = &f->fmt.pix;
> - const struct stfcamss_format_info *fi;
> - u32 width, height;
> - u32 bpl;
> - unsigned int i;
> -
> - fi = video_g_fi_by_pfmt(video, pix->pixelformat);
> - if (!fi)
> - fi = &video->formats[0]; /* default format */
> -
> - width = pix->width;
> - height = pix->height;
> -
> - memset(pix, 0, sizeof(*pix));
> -
> - pix->pixelformat = fi->pixelformat;
> - pix->width = clamp_t(u32, width, STFCAMSS_FRAME_MIN_WIDTH,
> - STFCAMSS_FRAME_MAX_WIDTH);
> - pix->height = clamp_t(u32, height, STFCAMSS_FRAME_MIN_HEIGHT,
> - STFCAMSS_FRAME_MAX_HEIGHT);
> - bpl = pix->width * fi->bpp / 8;
> - bpl = ALIGN(bpl, video->bpl_alignment);
> - pix->bytesperline = bpl;
> -
> - for (i = 0; i < fi->planes; ++i)
> - pix->sizeimage += bpl * pix->height / fi->vsub[i];
> -
> - pix->field = V4L2_FIELD_NONE;
> - pix->colorspace = V4L2_COLORSPACE_SRGB;
> - pix->flags = 0;
> - pix->ycbcr_enc =
> - V4L2_MAP_YCBCR_ENC_DEFAULT(pix->colorspace);
> - pix->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
> - pix->colorspace,
> - pix->ycbcr_enc);
> - pix->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix->colorspace);
> -
> - return 0;
> -}
> -
> -static int stf_video_init_format(struct stfcamss_video *video)
> -{
> - int ret;
> - struct v4l2_format format = {
> - .type = video->type,
> - .fmt.pix = {
> - .width = 1920,
> - .height = 1080,
> - .pixelformat = V4L2_PIX_FMT_NV12,
> - },
> - };
> -
> - ret = __video_try_fmt(video, &format);
> -
> - if (ret < 0)
> - return ret;
> -
> - video->active_fmt = format;
> -
> - return 0;
> -}
> -
> -/* -----------------------------------------------------------------------------
> - * Video queue operations
> - */
> -
> -static int video_queue_setup(struct vb2_queue *q,
> - unsigned int *num_buffers,
> - unsigned int *num_planes,
> - unsigned int sizes[],
> - struct device *alloc_devs[])
> -{
> - struct stfcamss_video *video = vb2_get_drv_priv(q);
> - const struct v4l2_pix_format *format = &video->active_fmt.fmt.pix;
> -
> - if (*num_planes) {
> - if (*num_planes != 1)
> - return -EINVAL;
> -
> - if (sizes[0] < format->sizeimage)
> - return -EINVAL;
> - } else {
> - *num_planes = 1;
> - sizes[0] = format->sizeimage;
> - }
> -
> - if (!sizes[0]) {
> - dev_dbg(video->stfcamss->dev,
> - "%s: error size is zero.\n", __func__);
> - return -EINVAL;
> - }
> -
> - dev_dbg(video->stfcamss->dev, "planes = %d, size = %d\n",
> - *num_planes, sizes[0]);
> -
> - return 0;
> -}
> -
> -static int video_buf_init(struct vb2_buffer *vb)
> -{
> - struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
> - struct stfcamss_video *video = vb2_get_drv_priv(vb->vb2_queue);
> - struct stfcamss_buffer *buffer = to_stfcamss_buffer(vbuf);
> - const struct v4l2_pix_format *fmt = &video->active_fmt.fmt.pix;
> - dma_addr_t *paddr;
> -
> - paddr = vb2_plane_cookie(vb, 0);
> - buffer->addr[0] = *paddr;
> -
> - if (fmt->pixelformat == V4L2_PIX_FMT_NV12)
> - buffer->addr[1] =
> - buffer->addr[0] + fmt->bytesperline * fmt->height;
> -
> - return 0;
> -}
> -
> -static int video_buf_prepare(struct vb2_buffer *vb)
> -{
> - struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
> - struct stfcamss_video *video = vb2_get_drv_priv(vb->vb2_queue);
> - const struct v4l2_pix_format *fmt = &video->active_fmt.fmt.pix;
> -
> - if (fmt->sizeimage > vb2_plane_size(vb, 0)) {
> - dev_dbg(video->stfcamss->dev,
> - "sizeimage = %u, plane size = %u\n",
> - fmt->sizeimage, (unsigned int)vb2_plane_size(vb, 0));
> - return -EINVAL;
> - }
> - vb2_set_plane_payload(vb, 0, fmt->sizeimage);
> -
> - vbuf->field = V4L2_FIELD_NONE;
> -
> - return 0;
> -}
> -
> -static void video_buf_queue(struct vb2_buffer *vb)
> -{
> - struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
> - struct stfcamss_video *video = vb2_get_drv_priv(vb->vb2_queue);
> - struct stfcamss_buffer *buffer = to_stfcamss_buffer(vbuf);
> -
> - video->ops->queue_buffer(video, buffer);
> -}
> -
> -static int video_get_subdev_format(struct stfcamss_video *video,
> - struct v4l2_subdev_format *fmt)
> -{
> - struct v4l2_subdev *subdev;
> - struct media_pad *pad;
> - struct media_entity *entity;
> - int ret;
> -
> - entity = &video->vdev.entity;
> - while (1) {
> - pad = &entity->pads[0];
> - if (!(pad->flags & MEDIA_PAD_FL_SINK))
> - break;
> -
> - pad = media_pad_remote_pad_first(pad);
> - if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
> - break;
> -
> - entity = pad->entity;
> - subdev = media_entity_to_v4l2_subdev(entity);
> -
> - fmt->pad = pad->index;
> -
> - ret = v4l2_subdev_call_state_active(subdev, pad, get_fmt, fmt);
> - if (ret < 0 && ret != -ENOIOCTLCMD)
> - return ret;
> - else if (!ret)
> - break;
> - }
> -
> - return 0;
> -}
> -
> -static int stf_video_check_format(struct stfcamss_video *video)
> -{
> - struct v4l2_pix_format *pix = &video->active_fmt.fmt.pix;
> - const struct stfcamss_format_info *fi;
> - int ret;
> - struct v4l2_subdev_format sd_fmt = {
> - .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> - };
> -
> - ret = video_get_subdev_format(video, &sd_fmt);
> - if (ret < 0)
> - return ret;
> -
> - fi = video_g_fi_by_mcode(video, sd_fmt.format.code);
> - if (!fi)
> - return -EINVAL;
> -
> - if (pix->pixelformat != fi->pixelformat ||
> - pix->height != sd_fmt.format.height ||
> - pix->width != sd_fmt.format.width ||
> - pix->field != sd_fmt.format.field)
> - return -EPIPE;
> -
> - return 0;
> -}
> -
> -static int video_start_streaming(struct vb2_queue *q, unsigned int count)
> -{
> - struct stfcamss_video *video = vb2_get_drv_priv(q);
> - struct video_device *vdev = &video->vdev;
> - int ret;
> -
> - ret = video_device_pipeline_start(vdev, &video->stfcamss->pipe);
> - if (ret < 0) {
> - dev_err(video->stfcamss->dev,
> - "Failed to media_pipeline_start: %d\n", ret);
> - goto err_ret_buffers;
> - }
> -
> - ret = pm_runtime_resume_and_get(video->stfcamss->dev);
> - if (ret < 0) {
> - dev_err(video->stfcamss->dev, "power up failed %d\n", ret);
> - goto err_pipeline_stop;
> - }
> -
> - video->ops->start_streaming(video);
> -
> - ret = v4l2_subdev_call(video->source_subdev, video, s_stream, true);
> - if (ret) {
> - dev_err(video->stfcamss->dev, "stream on failed\n");
> - goto err_pm_put;
> - }
> -
> - return 0;
> -
> -err_pm_put:
> - pm_runtime_put(video->stfcamss->dev);
> -err_pipeline_stop:
> - video_device_pipeline_stop(vdev);
> -err_ret_buffers:
> - video->ops->flush_buffers(video, VB2_BUF_STATE_QUEUED);
> - return ret;
> -}
> -
> -static void video_stop_streaming(struct vb2_queue *q)
> -{
> - struct stfcamss_video *video = vb2_get_drv_priv(q);
> - struct video_device *vdev = &video->vdev;
> -
> - video->ops->stop_streaming(video);
> -
> - v4l2_subdev_call(video->source_subdev, video, s_stream, false);
> -
> - pm_runtime_put(video->stfcamss->dev);
> -
> - video_device_pipeline_stop(vdev);
> - video->ops->flush_buffers(video, VB2_BUF_STATE_ERROR);
> -}
> -
> -static const struct vb2_ops stf_video_vb2_q_ops = {
> - .queue_setup = video_queue_setup,
> - .buf_init = video_buf_init,
> - .buf_prepare = video_buf_prepare,
> - .buf_queue = video_buf_queue,
> - .start_streaming = video_start_streaming,
> - .stop_streaming = video_stop_streaming,
> -};
> -
> -/* -----------------------------------------------------------------------------
> - * V4L2 ioctls
> - */
> -
> -static int video_querycap(struct file *file, void *fh,
> - struct v4l2_capability *cap)
> -{
> - strscpy(cap->driver, "starfive-camss", sizeof(cap->driver));
> - strscpy(cap->card, "Starfive Camera Subsystem", sizeof(cap->card));
> -
> - return 0;
> -}
> -
> -static int video_enum_fmt(struct file *file, void *fh, struct v4l2_fmtdesc *f)
> -{
> - struct stfcamss_video *video = video_drvdata(file);
> - const struct stfcamss_format_info *fi;
> -
> - if (f->index >= video->nformats)
> - return -EINVAL;
> -
> - if (f->mbus_code) {
> - /* Each entry in formats[] table has unique mbus_code */
> - if (f->index > 0)
> - return -EINVAL;
> -
> - fi = video_g_fi_by_mcode(video, f->mbus_code);
> - } else {
> - fi = video_g_fi_by_index(video, f->index);
> - }
> -
> - if (!fi)
> - return -EINVAL;
> -
> - f->pixelformat = fi->pixelformat;
> -
> - return 0;
> -}
> -
> -static int video_enum_framesizes(struct file *file, void *fh,
> - struct v4l2_frmsizeenum *fsize)
> -{
> - struct stfcamss_video *video = video_drvdata(file);
> - unsigned int i;
> -
> - if (fsize->index)
> - return -EINVAL;
> -
> - for (i = 0; i < video->nformats; i++) {
> - if (video->formats[i].pixelformat == fsize->pixel_format)
> - break;
> - }
> -
> - if (i == video->nformats)
> - return -EINVAL;
> -
> - fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
> - fsize->stepwise.min_width = STFCAMSS_FRAME_MIN_WIDTH;
> - fsize->stepwise.max_width = STFCAMSS_FRAME_MAX_WIDTH;
> - fsize->stepwise.min_height = STFCAMSS_FRAME_MIN_HEIGHT;
> - fsize->stepwise.max_height = STFCAMSS_FRAME_MAX_HEIGHT;
> - fsize->stepwise.step_width = 1;
> - fsize->stepwise.step_height = 1;
> -
> - return 0;
> -}
> -
> -static int video_g_fmt(struct file *file, void *fh, struct v4l2_format *f)
> -{
> - struct stfcamss_video *video = video_drvdata(file);
> -
> - *f = video->active_fmt;
> -
> - return 0;
> -}
> -
> -static int video_s_fmt(struct file *file, void *fh, struct v4l2_format *f)
> -{
> - struct stfcamss_video *video = video_drvdata(file);
> - int ret;
> -
> - if (vb2_is_busy(&video->vb2_q))
> - return -EBUSY;
> -
> - ret = __video_try_fmt(video, f);
> - if (ret < 0)
> - return ret;
> -
> - video->active_fmt = *f;
> -
> - return 0;
> -}
> -
> -static int video_try_fmt(struct file *file, void *fh, struct v4l2_format *f)
> -{
> - struct stfcamss_video *video = video_drvdata(file);
> -
> - return __video_try_fmt(video, f);
> -}
> -
> -static const struct v4l2_ioctl_ops stf_vid_ioctl_ops = {
> - .vidioc_querycap = video_querycap,
> - .vidioc_enum_fmt_vid_cap = video_enum_fmt,
> - .vidioc_enum_framesizes = video_enum_framesizes,
> - .vidioc_g_fmt_vid_cap = video_g_fmt,
> - .vidioc_s_fmt_vid_cap = video_s_fmt,
> - .vidioc_try_fmt_vid_cap = video_try_fmt,
> - .vidioc_reqbufs = vb2_ioctl_reqbufs,
> - .vidioc_querybuf = vb2_ioctl_querybuf,
> - .vidioc_qbuf = vb2_ioctl_qbuf,
> - .vidioc_expbuf = vb2_ioctl_expbuf,
> - .vidioc_dqbuf = vb2_ioctl_dqbuf,
> - .vidioc_create_bufs = vb2_ioctl_create_bufs,
> - .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
> - .vidioc_streamon = vb2_ioctl_streamon,
> - .vidioc_streamoff = vb2_ioctl_streamoff,
> -};
> -
> -/* -----------------------------------------------------------------------------
> - * V4L2 file operations
> - */
> -
> -static const struct v4l2_file_operations stf_vid_fops = {
> - .owner = THIS_MODULE,
> - .unlocked_ioctl = video_ioctl2,
> - .open = v4l2_fh_open,
> - .release = vb2_fop_release,
> - .poll = vb2_fop_poll,
> - .mmap = vb2_fop_mmap,
> - .read = vb2_fop_read,
> -};
> -
> -/* -----------------------------------------------------------------------------
> - * STFCAMSS video core
> - */
> -
> -static int stf_link_validate(struct media_link *link)
> -{
> - struct video_device *vdev =
> - media_entity_to_video_device(link->sink->entity);
> - struct stfcamss_video *video = video_get_drvdata(vdev);
> - int ret;
> -
> - ret = stf_video_check_format(video);
> -
> - return ret;
> -}
> -
> -static const struct media_entity_operations stf_media_ops = {
> - .link_validate = stf_link_validate,
> -};
> -
> -static void stf_video_release(struct video_device *vdev)
> -{
> - struct stfcamss_video *video = video_get_drvdata(vdev);
> -
> - media_entity_cleanup(&vdev->entity);
> -
> - mutex_destroy(&video->q_lock);
> - mutex_destroy(&video->lock);
> -}
> -
> -int stf_video_register(struct stfcamss_video *video,
> - struct v4l2_device *v4l2_dev, const char *name)
> -{
> - struct video_device *vdev = &video->vdev;
> - struct vb2_queue *q;
> - struct media_pad *pad = &video->pad;
> - int ret;
> -
> - mutex_init(&video->q_lock);
> - mutex_init(&video->lock);
> -
> - q = &video->vb2_q;
> - q->drv_priv = video;
> - q->mem_ops = &vb2_dma_contig_memops;
> - q->ops = &stf_video_vb2_q_ops;
> - q->type = video->type;
> - q->io_modes = VB2_DMABUF | VB2_MMAP;
> - q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> - q->buf_struct_size = sizeof(struct stfcamss_buffer);
> - q->dev = video->stfcamss->dev;
> - q->lock = &video->q_lock;
> - q->min_queued_buffers = STFCAMSS_MIN_BUFFERS;
> - ret = vb2_queue_init(q);
> - if (ret < 0) {
> - dev_err(video->stfcamss->dev,
> - "Failed to init vb2 queue: %d\n", ret);
> - goto err_mutex_destroy;
> - }
> -
> - pad->flags = MEDIA_PAD_FL_SINK;
> - ret = media_entity_pads_init(&vdev->entity, 1, pad);
> - if (ret < 0) {
> - dev_err(video->stfcamss->dev,
> - "Failed to init video entity: %d\n", ret);
> - goto err_mutex_destroy;
> - }
> -
> - ret = stf_video_init_format(video);
> - if (ret < 0) {
> - dev_err(video->stfcamss->dev,
> - "Failed to init format: %d\n", ret);
> - goto err_media_cleanup;
> - }
> -
> - vdev->fops = &stf_vid_fops;
> - vdev->ioctl_ops = &stf_vid_ioctl_ops;
> - vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE |
> V4L2_CAP_STREAMING;
> - vdev->entity.ops = &stf_media_ops;
> - vdev->vfl_dir = VFL_DIR_RX;
> - vdev->release = stf_video_release;
> - vdev->v4l2_dev = v4l2_dev;
> - vdev->queue = &video->vb2_q;
> - vdev->lock = &video->lock;
> - strscpy(vdev->name, name, sizeof(vdev->name));
> -
> - video_set_drvdata(vdev, video);
> -
> - ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
> - if (ret < 0) {
> - dev_err(video->stfcamss->dev,
> - "Failed to register video device: %d\n", ret);
> - goto err_media_cleanup;
> - }
> -
> - return 0;
> -
> -err_media_cleanup:
> - media_entity_cleanup(&vdev->entity);
> -err_mutex_destroy:
> - mutex_destroy(&video->lock);
> - mutex_destroy(&video->q_lock);
> - return ret;
> -}
> -
> -void stf_video_unregister(struct stfcamss_video *video)
> -{
> - vb2_video_unregister_device(&video->vdev);
> -}
> diff --git a/drivers/staging/media/starfive/camss/stf-video.h
> b/drivers/staging/media/starfive/camss/stf-video.h
> deleted file mode 100644
> index
> 8052b77e3ad83a16b283d497daed154ad3f2a542..000000000000000000000
> 0000000000000000000
> --- a/drivers/staging/media/starfive/camss/stf-video.h
> +++ /dev/null
> @@ -1,100 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/*
> - * stf_video.h
> - *
> - * StarFive Camera Subsystem - V4L2 device node
> - *
> - * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
> - */
> -
> -#ifndef STF_VIDEO_H
> -#define STF_VIDEO_H
> -
> -#include <linux/list.h>
> -#include <linux/mutex.h>
> -#include <linux/videodev2.h>
> -#include <media/v4l2-dev.h>
> -#include <media/v4l2-fh.h>
> -#include <media/v4l2-ioctl.h>
> -#include <media/videobuf2-v4l2.h>
> -
> -#define STFCAMSS_FRAME_MIN_WIDTH 64
> -#define STFCAMSS_FRAME_MAX_WIDTH 1920
> -#define STFCAMSS_FRAME_MIN_HEIGHT 64
> -#define STFCAMSS_FRAME_MAX_HEIGHT 1080
> -#define STFCAMSS_FRAME_WIDTH_ALIGN_8 8
> -#define STFCAMSS_FRAME_WIDTH_ALIGN_128 128
> -#define STFCAMSS_MIN_BUFFERS 2
> -
> -#define STFCAMSS_MAX_ENTITY_NAME_LEN 27
> -
> -enum stf_v_line_id {
> - STF_V_LINE_WR = 0,
> - STF_V_LINE_ISP,
> - STF_V_LINE_MAX,
> -};
> -
> -enum stf_capture_type {
> - STF_CAPTURE_RAW = 0,
> - STF_CAPTURE_YUV,
> - STF_CAPTURE_NUM,
> -};
> -
> -struct stfcamss_buffer {
> - struct vb2_v4l2_buffer vb;
> - dma_addr_t addr[2];
> - struct list_head queue;
> -};
> -
> -struct fract {
> - u8 numerator;
> - u8 denominator;
> -};
> -
> -/*
> - * struct stfcamss_format_info - ISP media bus format information
> - * @code: V4L2 media bus format code
> - * @pixelformat: V4L2 pixel format FCC identifier
> - * @planes: Number of planes
> - * @vsub: Vertical subsampling (for each plane)
> - * @bpp: Bits per pixel when stored in memory (for each plane)
> - */
> -struct stfcamss_format_info {
> - u32 code;
> - u32 pixelformat;
> - u8 planes;
> - u8 vsub[3];
> - u8 bpp;
> -};
> -
> -struct stfcamss_video {
> - struct stfcamss *stfcamss;
> - struct vb2_queue vb2_q;
> - struct video_device vdev;
> - struct media_pad pad;
> - struct v4l2_format active_fmt;
> - enum v4l2_buf_type type;
> - const struct stfcamss_video_ops *ops;
> - struct mutex lock; /* serialize device access */
> - struct mutex q_lock; /* protects the queue */
> - unsigned int bpl_alignment;
> - const struct stfcamss_format_info *formats;
> - unsigned int nformats;
> - struct v4l2_subdev *source_subdev;
> -};
> -
> -struct stfcamss_video_ops {
> - int (*queue_buffer)(struct stfcamss_video *video,
> - struct stfcamss_buffer *buf);
> - int (*flush_buffers)(struct stfcamss_video *video,
> - enum vb2_buffer_state state);
> - void (*start_streaming)(struct stfcamss_video *video);
> - void (*stop_streaming)(struct stfcamss_video *video);
> -};
> -
> -int stf_video_register(struct stfcamss_video *video,
> - struct v4l2_device *v4l2_dev, const char *name);
> -
> -void stf_video_unregister(struct stfcamss_video *video);
> -
> -#endif /* STF_VIDEO_H */
>
> --
> 2.52.0
^ permalink raw reply
* Re: [PATCH v3 1/3] dt-bindings: hwmon: ti,tmp108: Add P3T1035,P3T2030
From: Krzysztof Kozlowski @ 2026-01-16 7:22 UTC (permalink / raw)
To: Mayank Mahajan, linux, corbet, robh, krzk+dt, conor+dt,
linux-hwmon, devicetree, linux-doc, linux-kernel
Cc: priyanka.jain, vikash.bansal
In-Reply-To: <20260115111418.1851-1-mayankmahajan.x@nxp.com>
On 15/01/2026 12:14, Mayank Mahajan wrote:
> Document the NXP P3T1035 and P3T2030 compatibles in TMP108.
>
> Signed-off-by: Mayank Mahajan <mayankmahajan.x@nxp.com>
> ---
> V1 -> V2:
> - No changes in v2.
> V2 -> V3:
> - Add P3T1035 fallback for P3T2030 as they are functionally identical.
> - Add comment in the description explaining the use of P3T2030.
>
> .../devicetree/bindings/hwmon/ti,tmp108.yaml | 24 ++++++++++++-------
> 1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/hwmon/ti,tmp108.yaml b/Documentation/devicetree/bindings/hwmon/ti,tmp108.yaml
> index a6f9319e068d..1f540c623de6 100644
> --- a/Documentation/devicetree/bindings/hwmon/ti,tmp108.yaml
> +++ b/Documentation/devicetree/bindings/hwmon/ti,tmp108.yaml
> @@ -4,27 +4,35 @@
> $id: http://devicetree.org/schemas/hwmon/ti,tmp108.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: TMP108/P3T1085(NXP) temperature sensor
> +title: TMP108/P3T1035/P3T1085/P3T2030 temperature sensor
>
> maintainers:
> - Krzysztof Kozlowski <krzk@kernel.org>
>
> description: |
> - The TMP108/P3T1085(NXP) is a digital-output temperature sensor with a
> - dynamically-programmable limit window, and under- and overtemperature
> - alert functions.
> + The TMP108 or NXP P3T Family (P3T1035, P3T1085 and P3T2030) is a digital-
> + output temperature sensor with a dynamically-programmable limit window,
> + and under- and over-temperature alert functions.
>
> - P3T1085(NXP) support I3C.
> + NXP P3T Family (P3T1035, P3T1085 and P3T2030) supports I3C.
>
> Datasheets:
> https://www.ti.com/product/TMP108
> https://www.nxp.com/docs/en/data-sheet/P3T1085UK.pdf
> + https://www.nxp.com/docs/en/data-sheet/P3T1035XUK_P3T2030XUK.pdf
> +
> + P3T2030 is functionally identical to P3T1035. Hence, device tree nodes that
> + use the P3T2030 must provide a fallback compatible string of "nxp,p3t1035"
Drop the sentence. Schema already tells that. Never repeat the schema in
free text. It's like adding comments to code:
ptr = kzalloc()
/* Check for null pointer after allocation */
if (!ptr)
return -ENOMEM
This is worse coding. Write concise, clearly readable code.
With this fixed:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
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