Re: [PATCH v2 5/9] ARM: dts: omap: dm816x: Correct speed for sysclk5

["Ettore Chimenti" <ettore.chimenti@linaro.org>]

Hi Andreas,

On Sun Nov 1, 2026 at 10:29 PM CET, Andreas Kemnade wrote:
> On Wed, 28 Oct 2026 17:06:06 +0100
> Ettore Chimenti <ettore.chimenti@linaro.org> wrote:
>
>> From: Andrew Goodbody <andrew.goodbody@linaro.org>
>> 
>> The default code for setting up the clocks results in sysclk5 running at
>> 1.6GHz whereas it is expected to run at half that ie 813MHz. Force the
>> divider to be /2 to achieve the 813MHz speed.
>> 
>> Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
>> Signed-off-by: Ettore Chimenti <ettore.chimenti@linaro.org>
>> ---
>>  arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi
>> index 76ebc6c3c3e5..cb990773b098 100644
>> --- a/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi
>> +++ b/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi
>> @@ -144,7 +144,7 @@ sysclk5_ck: sysclk5_ck@310 {
>>  		#clock-cells = <0>;
>>  		compatible = "ti,divider-clock";
>>  		clocks = <&sysclk4_ck>;
>> -		ti,max-div = <1>;
>> +		ti,dividers = <2>;
>
> so this changes register value  0 is intepreted as divider 1
> to divider 2. Sounds strange. It just changes the interpretation of the
> register values, not the setting. Maybe checkout the register value from
> user space with tools like devmem. The original interpretation was right.
> So this change does not make any sense. I think sysclk5 still runs at
> 1.6Ghz, but it is displayed as 813Mhz.
>
> I would expect some assigned-clocks / assigned-clock-rates pair somewhere
> in this patch instead.
>

We tested on EVM with devmem and this patch correctly sets bit 0 to 1
(which is /2 in the manual).

However, should ti,max-div in this case be <2> (and all the other clocks
that supports two dividers)? 

I tested to set `ti,max-div = <2>;` and it seems to correctly set the /2
divider as well, but without specifying any assigned-clock{s,-rates}, so
I'm missing the rationale of how the divider is selected.

I'll drop this patch from the series for now, I think it needs more
investigation to figure out why it behaves like this.

Thanks,
Ettore