回覆: [PATCH 2/8] i3c: mipi-i3c-hci: Support address-indexed DAT slots

[Billy Tsai <billy_tsai@aspeedtech.com>]

> > HCI v1's DEV_INDEX allocation is sequential: the driver picks any free
> > DAT slot, with no relationship between the slot number and the
> > device's I3C address. ASPEED's I3C controllers have long needed to
> > support more devices than the standard 5-bit DEV_INDEX field
> > (addresses 0-31) allows, so they use a layout where the DAT slot
> > number is itself the device's address, requiring DEV_INDEX to widen
> > to 7 bits (addresses 0-127).

> Does ASPEED work if use 5bit DEV_INDEX?

No, it's about how the DAT itself is addressed. On AST2700, the
controller derives a device's I3C address directly from its DAT slot
number; there is no separate address field/register per entry.

I2C devices on the same bus make this concrete: their addresses are
fixed by the device or board configuration, not assigned by our
controller, so we cannot restrict them to addresses below 0x20. The
same is true for I3C devices that only support SETAASA: their dynamic
address is their existing static address, again fixed by the device
or board rather than something our controller assigns. With a 5-bit
DEV_INDEX, only slots 0-31 exist, so any such device landing at 0x20
or above simply cannot be placed in the DAT, regardless of how many
other devices are on the bus. Dynamically-assigned I3C addresses
aren't guaranteed to land under 32 either. DEV_INDEX has to cover the
full address range this DAT layout can produce, hence 7 bits.

Billy