Re: [PATCH v6 1/2] dt-bindings: pwm: dwc: add optional reset

[Krzysztof Kozlowski <krzk@kernel.org>]

On 29/04/2026 11:30, Xuyang Dong wrote:
>>>>>  
>>>>> +allOf:
>>>>> +  - $ref: pwm.yaml#
>>>>> +
>>>>> +  - if:
>>>>> +      properties:
>>>>> +        compatible:
>>>>> +          contains:
>>>>> +            const: eswin,eic7700-pwm
>>>>
>>>> Same problem as v3 which I commented. I do not understand why your new
>>>> device has also 1 reset.
>>>>
>>>> Your commit msg MUST explain why 1 reset is valid.
>>>>
>>>
>>> Hi Krzysztof,
>>>
>>> Although the PWM IP supports two clock domains, each requiring a reset, 
>>> the EIC7700 implementation uses the same clock domain for both clock 
>>> signals. Therefore, the eic7700-pwm only supports one reset.
>>>
>>
>> If we speak about eic7700, explain why it has two resets now, according
>> to schema, even though you say it has not.
>>
>> But I was speaking about dw-apb-timers-pwm, which has one reset as well!
>> Why you are not having proper constraints? Please read writing bindings
>> document.
>>
> 
> Hi Krzysztof,
> 
> Let me clarify the reset signals.
>   - snps,dw-apb-timers-pwm2: IP spec has 2 optional reset signals (one per
> clock domain), SoC vendor decides whether to wire them — so maxItems: 2, 
> optional in required.

Two reset signals but what is exactly optional? Each of them? Only the
first? Binding does not allow the first to be optional.

>   - eswin,eic7700-pwm: SoC physically ties both signals to one reset — so
> exactly 1, required.

Then two would not be right and you need to restrict that.

Krzysztof