[PATCH v2 0/3] clk: qcom: add MSM8x60 LPASS Clock Controller

[Herman van Hazendonk <github.com@herrie.org>]

Hi all,

Self-review (with Sashiko AI assist) caught five issues in v1 before
maintainer review reached them. v1:

  https://lore.kernel.org/linux-arm-msm/cover.1780148149.git.github.com@herrie.org/

v2 changes:

  - NEW patch 1/3: extend Documentation/devicetree/bindings/clock/
    qcom,lcc.yaml with the three MSM8x60 family compatibles
    (qcom,lcc-msm8260, qcom,lcc-msm8660, qcom,lcc-apq8060) and add
    them to the existing apq8064/msm8960 conditional block. Without
    this, board DTs using the new compatibles fail dt_binding_check.

  - patch 2/3: dt-bindings clock-ID header for lcc-msm8660,
    unchanged from v1.

  - patch 3/3: LCC driver. Five fixes folded in:

      * CLK_AIF_OSR_DIV macro: divider width was 8, which made the
        bit-divider field span bits 10 through 17 on the _ns
        register. On MSM8x60 BIT(15) (BIT_DIV branch enable) and
        BIT(17) (OSR branch enable) sit inside that range, so any
        clk_regmap_div read-modify-write would clobber both branch
        gates. Width 4 (bits 10 through 13) matches the standalone
        mi2s div clock and the legacy downstream Samsung MSM8660 /
        webOS clock-8x60.c register layout. Added a block comment
        documenting the verified bit assignments and the rationale
        for the width change.

      * Match table: add qcom,lcc-msm8260 alongside the existing
        qcom,lcc-msm8660 and qcom,lcc-apq8060. MSM8x60 covers all
        three variants.

      * clk_tbl_pcm_393: add the 27 MHz PXO fallback entry that
        clk_tbl_pcm_540 already carries, so the 393 plan can also
        fall back to the board PXO source.

      * lcc_msm8660_probe(): check the return value of regmap_read()
        on PLL4 L. v1 ignored it, so a regmap failure would have
        left val as uninitialised stack memory and steered the rest
        of probe down a random branch. Use dev_err_probe() on
        failure.

      * lcc_msm8660_probe(): assign the freq_tbl pointers on the
        static clk_rcg structs unconditionally on both PLL4 plans
        instead of mutating-on-540 / leaving-mutated-on-393. The
        driver is effectively singleton today, but explicit
        assignment also restores the defaults if the driver is ever
        rebound on a system whose PLL4 has been reprogrammed.

Thanks,
Herman

Herman van Hazendonk (3):
  dt-bindings: clock: qcom,lcc: add MSM8x60 family compatibles
  dt-bindings: clock: qcom: add lcc-msm8660 LPASS clock IDs
  clk: qcom: add MSM8x60 LCC (LPASS) driver

 .../devicetree/bindings/clock/qcom,lcc.yaml   |   6 +
 drivers/clk/qcom/Kconfig                      |   9 +
 drivers/clk/qcom/Makefile                     |   1 +
 drivers/clk/qcom/lcc-msm8660.c                | 551 ++++++++++++++++++
 include/dt-bindings/clock/qcom,lcc-msm8660.h  |  48 ++
 5 files changed, 615 insertions(+)
 create mode 100644 drivers/clk/qcom/lcc-msm8660.c
 create mode 100644 include/dt-bindings/clock/qcom,lcc-msm8660.h

-- 
2.43.0